From 85cfb0f91f4e1262cc4a5aa37664fe30d5027c15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 30 Apr 2026 16:03:54 +0200 Subject: [PATCH] xUSL/GFX: Add GFX initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- xUSL/CCX/Common/Kconfig | 2 +- xUSL/GFX/Common/Gfx.h | 7 + xUSL/GFX/Common/GfxConfigDflts.c | 62 +- xUSL/GFX/Common/GfxDisplayPhySettings.h | 61 +- xUSL/GFX/Common/GfxInit.c | 82 +- xUSL/GFX/Common/GfxV4.h | 237 ++++++ xUSL/GFX/Common/meson.build | 3 - xUSL/GFX/GfxClass-api.h | 14 +- xUSL/GFX/Phx/GfxDisplayPhySettings.c | 284 +++---- xUSL/GFX/Phx/GfxEnumConnectorsPhx.c | 747 ++++++++++++++++++ xUSL/GFX/Phx/GfxInfoCollectionPhx.c | 166 ++++ xUSL/GFX/Phx/GfxInitPhx.c | 412 ++++++++++ xUSL/GFX/Phx/GfxInitPhx.h | 63 ++ xUSL/GFX/Phx/GfxPhx.c | 16 +- xUSL/GFX/Phx/meson.build | 3 + xUSL/GFX/meson.build | 2 + xUSL/Mpio/Common/MpioTopology.c | 7 +- xUSL/Nbio/Common/PciStructs.h | 13 +- xUSL/Nbio/Phx/includePHX/PHX_AZALIA.h | 2 + .../Nbio/Phx/includePHX/PHX_GnbRegistersPhx.h | 8 + xUSL/Nbio/Phx/includePHX/PHX_IOHC.h | 5 + 21 files changed, 1912 insertions(+), 284 deletions(-) create mode 100644 xUSL/GFX/Common/GfxV4.h create mode 100644 xUSL/GFX/Phx/GfxEnumConnectorsPhx.c create mode 100644 xUSL/GFX/Phx/GfxInfoCollectionPhx.c create mode 100644 xUSL/GFX/Phx/GfxInitPhx.c create mode 100644 xUSL/GFX/Phx/GfxInitPhx.h diff --git a/xUSL/CCX/Common/Kconfig b/xUSL/CCX/Common/Kconfig index 923acde..9fba484 100644 --- a/xUSL/CCX/Common/Kconfig +++ b/xUSL/CCX/Common/Kconfig @@ -5,7 +5,7 @@ # ------------------------------ APIC Mode -------------------------- choice prompt "APIC - operational mode for this plaltform" - default CHOICE_APIC_AUTO + default APIC_AUTO help Ref: typedef enum{} APIC_MODE; diff --git a/xUSL/GFX/Common/Gfx.h b/xUSL/GFX/Common/Gfx.h index 3b62e80..0943c84 100644 --- a/xUSL/GFX/Common/Gfx.h +++ b/xUSL/GFX/Common/Gfx.h @@ -8,6 +8,7 @@ #include +#include #include #include #include @@ -40,3 +41,9 @@ GetGfxDdiConfig ( SIL_CONTEXT *SilContext, uint32_t *InfoDdiBlockDataSize ); + +SIL_STATUS +GetUmaInformation ( + SIL_CONTEXT *SilContext, + MEMORY_HOLE_DESCRIPTOR *UmaRange + ); diff --git a/xUSL/GFX/Common/GfxConfigDflts.c b/xUSL/GFX/Common/GfxConfigDflts.c index 451d5c3..79aa043 100644 --- a/xUSL/GFX/Common/GfxConfigDflts.c +++ b/xUSL/GFX/Common/GfxConfigDflts.c @@ -14,31 +14,31 @@ const GFXCLASS_INPUT_BLK GfxClassDflts = { * This becomes part of the IP API for the Host. */ .AmdGfxOpenSilEnable = 1, - .CfgDisableAllNumAudioEndpoints = 0, - .DpHBR2Disable0 = 0, - .DpHBR3Disable0 = 0, - .DpHBR2Disable1 = 0, - .DpHBR3Disable1 = 0, - .DpHBR2Disable2 = 0, - .DpHBR3Disable2 = 0, - .DpHBR2Disable3 = 0, - .DpHBR3Disable3 = 0, - .HDMI2Disable0 = 0, - .HDMIRetimerCaps0 = 0, - .HDMI2Disable1 = 0, - .HDMIRetimerCaps1 = 0, - .HDMI2Disable2 = 0, - .HDMIRetimerCaps2 = 0, - .HDMI2Disable3 = 0, - .HDMIRetimerCaps3 = 0, - .PeiGopEnable = 0, - .SysInfoTconInstantOnLogoSupport = 0, - .CfgSysInfoGpuCapsDdsSupport = 0, - .CfgSysInfoGpuCapsBr3SdrSupport = 0, - .Usb4Rt0En = 0, - .Usb4Rt0DpTnlEn = 0, - .Usb4Rt1En = 0, - .Usb4Rt1DpTnlEn = 0, + .CfgDisableAllNumAudioEndpoints = false, + .DpHBR2Disable0 = false, + .DpHBR3Disable0 = false, + .DpHBR2Disable1 = false, + .DpHBR3Disable1 = false, + .DpHBR2Disable2 = false, + .DpHBR3Disable2 = false, + .DpHBR2Disable3 = false, + .DpHBR3Disable3 = false, + .HDMI2Disable0 = false, + .HDMIRetimerCaps0 = false, + .HDMI2Disable1 = false, + .HDMIRetimerCaps1 = false, + .HDMI2Disable2 = false, + .HDMIRetimerCaps2 = false, + .HDMI2Disable3 = false, + .HDMIRetimerCaps3 = false, + .PeiGopEnable = true, + .SysInfoTconInstantOnLogoSupport = false, + .CfgSysInfoGpuCapsDdsSupport = false, + .CfgSysInfoGpuCapsBr3SdrSupport = false, + .Usb4Rt0En = true, + .Usb4Rt0DpTnlEn = true, + .Usb4Rt1En = true, + .Usb4Rt1DpTnlEn = true, .AmdPreSilCtrl1 = 0, .AmdDisplayPhyTuningSettingTableHeader = 0, .AmdDisplayPhyTuningSettingTableContent = 0, @@ -53,14 +53,16 @@ const GFXCLASS_INPUT_BLK GfxClassDflts = { .DisplayCapDdi3 = 0, .DisplayCapDdi4 = 0, .AmdBitMapDisaplyOnlyController = 0, - .CfgPcieRefClkSpreadSpectrum = 0, + .CfgPcieRefClkSpreadSpectrum = 375, .AmdDpPhyOverride = 0, - .BackLightPwmHz = 0, - .CfgMaxNumAudioEndpoints = 0, - .CfgIgpuControl = 0, - .DisplayFixVoltageSwing = 0, + .BackLightPwmHz = 200, + .CfgMaxNumAudioEndpoints = 4, + .CfgIgpuControl = 1, + .DisplayFixVoltageSwing = 2, .PwrOnVaryBlToBlon = 0, .PwrDownBloffToVaryBlOff = 0, .PwrOffDelay = 0, .Usb4DpiaDisable = 0, + .UmaMode = 2, + .AmdUmaCarveoutIndexMax = 1 }; diff --git a/xUSL/GFX/Common/GfxDisplayPhySettings.h b/xUSL/GFX/Common/GfxDisplayPhySettings.h index 2b03dcf..310f321 100644 --- a/xUSL/GFX/Common/GfxDisplayPhySettings.h +++ b/xUSL/GFX/Common/GfxDisplayPhySettings.h @@ -8,64 +8,7 @@ #pragma once +#include "GfxV4.h" + #define APU_TABLE_FORMAT_REVISION 1 #define APU_TABLE_CONTENT_REVISION 0 - - -/**************************************************************************** - * Common header for all tables (Data table, Command function). - * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. - * And the pointer actually points to this header. - ****************************************************************************/ -//IPCLEAN_END -typedef struct _atom_common_table_header { - uint16_t structuresize; - uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible - uint8_t content_revision; //change it when a data table has a structure change, - //or a hw function has a input/output parameter change -} ATOM_COMMON_TABLE_HEADER; -//IPCLEAN_START - -//ucEncoderMode -typedef enum { - ATOM_ENCODER_MODE_DP = 0, - ATOM_ENCODER_MODE_DP_SST = 0, - ATOM_ENCODER_MODE_RESERVED = 1, - ATOM_ENCODER_MODE_DVI = 2, - ATOM_ENCODER_MODE_HDMI = 3, - ATOM_ENCODER_MODE_HDMI_FRL = 4, - ATOM_ENCODER_MODE_DP_AUDIO = 5, - ATOM_ENCODER_MODE_DP_MST = 5, - ATOM_ENCODER_MODE_DP2 = 8, - ATOM_ENCODER_MODE_CRT = 15, - ATOM_ENCODER_MODE_DVO = 16, -} ATOM_ENCODE_MODE_DEF; - -typedef struct _atom_n6_display_phy_tuning_set { - uint8_t display_signal_type; - uint8_t phy_sel; - uint8_t preset_level; - uint8_t reserved1; - uint32_t reserved2; - uint32_t speed_upto; - uint8_t tx_vboost_level; - uint8_t tx_vreg_v2i; - uint8_t tx_vregdrv_byp; - uint8_t tx_term_cntl; - uint8_t tx_peak_level; - uint8_t tx_slew_en; - uint8_t tx_eq_pre; - uint8_t tx_eq_main; - uint8_t tx_eq_post; - uint8_t tx_en_inv_pre; - uint8_t tx_en_inv_post; - uint8_t tx_slew_ctrl_val; - uint32_t reserved4; - uint32_t reserved5; - uint32_t reserved6; -} ATOM_N6_DISPLAY_PHY_TUNING_SET; - -typedef struct _atom_display_phy_tuning_info { - ATOM_COMMON_TABLE_HEADER table_header; - ATOM_N6_DISPLAY_PHY_TUNING_SET disp_phy_tuning[]; -} ATOM_DISPLAY_PHY_TUNING_INFO; diff --git a/xUSL/GFX/Common/GfxInit.c b/xUSL/GFX/Common/GfxInit.c index 3ce8cbb..984526b 100644 --- a/xUSL/GFX/Common/GfxInit.c +++ b/xUSL/GFX/Common/GfxInit.c @@ -7,6 +7,8 @@ */ #include +#include +#include #include #include #include "Gfx.h" @@ -181,40 +183,6 @@ GetGfxN6Config ( return (void *)GfxN6InputData; } -// Move to GfxInitPhx.c file -void -SilDumpDdiTable ( - DDI_DESCRIPTOR *DdiConfigData - ) -{ - uint8_t index; - - for (index = 0; index < 5; index++) { - GFX_TRACEPOINT(SIL_TRACE_INFO, - "SIL: Ddi ConnectorType 0x%x \n", - DdiConfigData[index].Ddi.ConnectorType - ); - GFX_TRACEPOINT(SIL_TRACE_INFO, - "SIL: Ddi AuxInde 0x%x \n", - DdiConfigData[index].Ddi.AuxIndex - ); - GFX_TRACEPOINT(SIL_TRACE_INFO, - "SIL: Ddi HdpIndex 0x%x \n", - DdiConfigData[index].Ddi.HdpIndex - ); - GFX_TRACEPOINT(SIL_TRACE_INFO, - "SIL: Ddi LanePnInversionMask 0x%x \n", - DdiConfigData[index].Ddi.LanePnInversionMask - ); - GFX_TRACEPOINT(SIL_TRACE_INFO, - "SIL: Ddi Flags 0x%x \n", - DdiConfigData[index].Ddi.Flags - ); - GFX_TRACEPOINT(SIL_TRACE_INFO, "SIL: Flags 0x%x \n", DdiConfigData[index].Flags); - } - -} - /**-------------------------------------------------------------------- * GetGfxDdiConfig * @@ -270,3 +238,49 @@ GetGfxDdiConfig ( GFX_TRACEPOINT(SIL_TRACE_EXIT, "\n"); return (void *)GfxDdiInputData; } + + +SIL_STATUS +GetUmaInformation ( + SIL_CONTEXT *SilContext, + MEMORY_HOLE_DESCRIPTOR *UmaRange + ) +{ + SIL_STATUS Status; + uint8_t MemRangeIndex; + APOB_SYSTEM_MEMORY_MAP_TYPE_STRUCT *ApobEntry; + MEMORY_HOLE_DESCRIPTOR *HoleMapPtr; + APOB_IP2IP_API *ApobIp2IpApi; + + if (SilContext == NULL || UmaRange == NULL) { + return SilInvalidParameter; + } + + Status = SilGetIp2IpApi(SilContext, SilId_ApobClass, (void **) &ApobIp2IpApi); + if ((Status != SilPass) || (ApobIp2IpApi == NULL)) { + assert(Status == SilPass); + return Status; + } + + Status = ApobIp2IpApi->ApobAmdGetApobEntryInstance(SilContext, + APOB_FABRIC, + APOB_SYS_MAP_INFO_TYPE, + 0, + 0, + (APOB_TYPE_HEADER **) &ApobEntry + ); + if (Status != SilPass) { + return Status; + } + + /* Scan through all mem ranges to find the base address of UMA range. */ + for (MemRangeIndex = 0; MemRangeIndex < ApobEntry->ApobSystemMap.NumberOfHoles; MemRangeIndex++) { + HoleMapPtr = &ApobEntry->ApobSystemMap.HoleInfo[MemRangeIndex]; + if (HoleMapPtr->Type == UMA) { + memcpy(UmaRange, HoleMapPtr, sizeof(MEMORY_HOLE_DESCRIPTOR)); + return SilPass; + } + } + + return SilNotFound; +} diff --git a/xUSL/GFX/Common/GfxV4.h b/xUSL/GFX/Common/GfxV4.h new file mode 100644 index 0000000..82a9978 --- /dev/null +++ b/xUSL/GFX/Common/GfxV4.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. */ + +/** + * @file GfxV4.h + * @brief ATOM GFX structs and defines + */ + +#pragma once + +#define DEVICE_DFP 0x1 +#define DEVICE_CRT 0x2 +#define DEVICE_LCD 0x3 + +#define CONNECTOR_DISPLAYPORT_ENUM 0x3013 +#define CONNECTOR_HDMI_TYPE_A_ENUM 0x300c +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM 0x3003 +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM 0x3004 +#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM 0x3001 +#define CONNECTOR_DUAL_LINK_DVI_I_ENUM 0x3002 +#define CONNECTOR_VGA_ENUM 0x3005 +#define CONNECTOR_LVDS_ENUM 0x300E +#define CONNECTOR_eDP_ENUM 0x3014 +#define CONNECTOR_LVDS_eDP_ENUM 0x3016 + +#define ENCODER_DP2VGA_ENUM_ID1 0x2123 +#define ENCODER_DP2LVDS_ENUM_ID2 0x2223 +#define ENCODER_ALMOND_ENUM_ID1 0x2122 +#define ENCODER_NOT_PRESENT 0x0000 + +#define eDP_TO_LVDS_SWINIT_ID 0x02 + + +#define ATOM_DEVICE_CRT1_SUPPORT 0x0001 +#define ATOM_DEVICE_DFP1_SUPPORT 0x0008 +#define ATOM_DEVICE_DFP6_SUPPORT 0x0040 +#define ATOM_DEVICE_DFP2_SUPPORT 0x0080 +#define ATOM_DEVICE_DFP3_SUPPORT 0x0200 +#define ATOM_DEVICE_DFP4_SUPPORT 0x0400 +#define ATOM_DEVICE_DFP5_SUPPORT 0x0800 +#define ATOM_DEVICE_LCD1_SUPPORT 0x0002 +#define ATOM_DEVICE_LCD2_SUPPORT 0x0020 + +typedef enum { + ATOM_ENCODER_MODE_DP = 0, + ATOM_ENCODER_MODE_DP_SST = 0, + ATOM_ENCODER_MODE_LVDS = 1, + ATOM_ENCODER_MODE_DVI = 2, + ATOM_ENCODER_MODE_HDMI = 3, + ATOM_ENCODER_MODE_HDMI_FRL = 4, + ATOM_ENCODER_MODE_DP_AUDIO = 5, + ATOM_ENCODER_MODE_DP_MST = 5, + ATOM_ENCODER_MODE_DP2 = 8, + ATOM_ENCODER_MODE_CRT = 15, + ATOM_ENCODER_MODE_DVO = 16, +} ATOM_ENCODE_MODE_DEF; + +#pragma pack(1) +typedef struct _atom_common_table_header { + uint16_t structuresize; + uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible + uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change +} ATOM_COMMON_TABLE_HEADER; + +typedef struct _edp_info_table +{ + uint16_t edp_backlight_pwm_hz; + uint16_t edp_ss_percentage; + uint16_t edp_ss_rate_10hz; + uint16_t reserved1; + uint32_t reserved2; + uint8_t edp_pwr_on_off_delay; + uint8_t edp_pwr_on_vary_bl_to_blon; + uint8_t edp_pwr_down_bloff_to_vary_bloff; + uint8_t edp_panel_bpc; + uint8_t edp_bootup_bl_level; + uint8_t reserved3[3]; + uint32_t reserved4[3]; +} EDP_INFO_TABLE; + +typedef struct _ext_display_path +{ + uint16_t usDeviceTag; + uint16_t usDeviceACPIEnum; + uint16_t usDeviceConnector; + uint8_t ucExtAUXDDCLutIndex; + uint8_t ucExtHPDPINLutIndex; + uint16_t usExtEncoderObjId; + uint8_t ucChannelMapping; + uint8_t ucChPNInvert; + uint32_t usCaps; +} EXT_DISPLAY_PATH; + +//usCaps +typedef enum { + EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001, + EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002, + EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C, + EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), + EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), + EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2), + EXT_DISPLAY_PATH_CAPS__HBR3_DISABLE = 0x0080, + EXT_DISPLAY_PATH_CAPS__USB_C_TYPE = 0x100, + EXT_DISPLAY_PATH_CAPS__HDMI20_DISABLE = 0x200, + EXT_DISPLAY_PATH_CAPS__DFPx_INTERNAL_DISP_EN = 0x400, + EXT_DISPLAY_PATH_CAPS__DP_HAS_RETIMER = 0x800, + EXT_DISPLAY_PATH_CAPS__DP2 = 0x100000, + EXT_DISPLAY_PATH_CAPS__UHBR10_EN = 0x200000, + EXT_DISPLAY_PATH_CAPS__UHBR13_5_EN = 0x400000, + EXT_DISPLAY_PATH_CAPS__RECORD_UHBR20_EN = 0x800000, + EXT_DISPLAY_PATH_CAPS__HDMI_FRL = 0x2000000, + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_8GbEn = 0x4000000, + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_10GbEn = 0x8000000, + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_12GbEn = 0x10000000, + EXT_DISPLAY_PATH_CAPS__USB4_DPIA_ENABLE = 0x20000000, +} EXT_DISPLAY_PATH_CAP_DEF; + +typedef struct _atom_external_display_connection_info { + ATOM_COMMON_TABLE_HEADER sHeader; + uint8_t ucGuid[16]; // a GUID is a 16 byte long string + EXT_DISPLAY_PATH sPath[7]; // total of fixed 7 entries. + uint8_t ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. + uint8_t stereopinid; // use for eDP panel + uint8_t ucRemoteDisplayConfig; + uint8_t uceDPToLVDSRxId; + uint8_t ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value + uint8_t reserved[3]; // for potential expansion +} ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; + +typedef struct _atom_n6_display_phy_tuning_set { + uint8_t display_signal_type; + uint8_t phy_sel; + uint8_t preset_level; + uint8_t reserved1; + uint32_t reserved2; + uint32_t speed_upto; + uint8_t tx_vboost_level; + uint8_t tx_vreg_v2i; + uint8_t tx_vregdrv_byp; + uint8_t tx_term_cntl; + uint8_t tx_peak_level; + uint8_t tx_slew_en; + uint8_t tx_eq_pre; + uint8_t tx_eq_main; + uint8_t tx_eq_post; + uint8_t tx_en_inv_pre; + uint8_t tx_en_inv_post; + uint8_t tx_slew_ctrl_val; + uint32_t reserved4; + uint32_t reserved5; + uint32_t reserved6; +} ATOM_N6_DISPLAY_PHY_TUNING_SET; + +typedef struct _atom_display_phy_tuning_info { + ATOM_COMMON_TABLE_HEADER table_header; + ATOM_N6_DISPLAY_PHY_TUNING_SET disp_phy_tuning[]; +} ATOM_DISPLAY_PHY_TUNING_INFO; + +typedef struct _atom_integrated_system_info_v2_2 +{ + ATOM_COMMON_TABLE_HEADER table_header; + uint32_t vbios_misc; + uint32_t gpucapinfo; + uint32_t system_config; + uint32_t cpucapinfo; + uint16_t gpuclk_ss_percentage; + uint16_t gpuclk_ss_type; + uint16_t dpphy_override; + uint8_t memorytype; + uint8_t umachannelnumber; + uint8_t htc_hyst_limit; + uint8_t htc_tmp_limit; + uint8_t reserved1; + uint8_t gpu_package_id; + EDP_INFO_TABLE edp1_info; + EDP_INFO_TABLE edp2_info; + uint32_t reserved3[8]; + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO extdispconninfo; + uint32_t reserved4[25]; + uint32_t UMACarveoutIndexMax; + uint32_t UMACarveoutIndexDefault; + uint32_t UMACarveoutIndex; + uint8_t UMACarveoutID[4]; + uint32_t reserved5[160]; +} ATOM_INTEGRATED_SYSTEM_INFO_V2_2; + +// gpucapinfo +typedef enum { + SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, + SYS_INFO_GPUCAPS__EXT_HDMI_INIT_PER_PORT = 0x20, + SYS_INFO_GPUCAPS__DDS_SUPPORT = 0x40, + SYS_INFO_GPUCAPS__BR3_SDR_SUPPORT = 0x80, + SYS_INFO_GPUCAPS__SEAMLESS_SUPPORT = 0x100, + SYS_INFO_GPUCAPS__TCON_INSTANT_ON_LOGO = 0x01, + SYS_INFO_GPUCAPS__USB4_DPIA_BW_ALLOC = 0x02, +} ATOM_SYSTEM_GPUCAPINF_DEF; +typedef enum { + OtherMemType = 0x01, + UnknownMemType, + DramMemType, + EdramMemType, + VramMemType, + SramMemType, + RamMemType, + RomMemType, + FlashMemType, + EepromMemType, + FepromMemType, + EpromMemType, + CdramMemType, + ThreeDramMemType, + SdramMemType, + SgramMemType, + RdramMemType, + DdrMemType, + Ddr2MemType, + Ddr2FbdimmMemType, + Ddr3MemType = 0x18, + Fbd2MemType, + Ddr4MemType, + LpDdrMemType, + LpDdr2MemType, + LpDdr3MemType, + LpDdr4MemType, + GDdr6MemType, + HbmMemType, + Hbm2MemType, + Ddr5MemType = 0x22, + LpDdr5MemType, +} ATOM_DMI_T17_MEM_TYPE_DEF; + +typedef struct { + ATOM_INTEGRATED_SYSTEM_INFO_V2_2 sIntegratedSysInfo; + uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable +} ATOM_FUSION_SYSTEM_INFO_V6; + +#pragma pack() diff --git a/xUSL/GFX/Common/meson.build b/xUSL/GFX/Common/meson.build index 75c40ee..2a559a0 100644 --- a/xUSL/GFX/Common/meson.build +++ b/xUSL/GFX/Common/meson.build @@ -1,8 +1,5 @@ # SPDX-License-Identifier: MIT # Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. - - - xusl += files([ 'GfxConfigDflts.c', 'GfxInit.c' ]) diff --git a/xUSL/GFX/GfxClass-api.h b/xUSL/GFX/GfxClass-api.h index 4837996..0ce2ff5 100644 --- a/xUSL/GFX/GfxClass-api.h +++ b/xUSL/GFX/GfxClass-api.h @@ -68,12 +68,12 @@ typedef struct { bool Usb4Rt1En; bool Usb4Rt1DpTnlEn; uint32_t AmdPreSilCtrl1; - void *AmdDisplayPhyTuningSettingTableHeader; - void *AmdDisplayPhyTuningSettingTableContent; - void *AmdDdiContent; - uint32_t PeiGopConfigMemsize; - uint32_t PeiGopVmFbOffset; - uint32_t PeiGopVmFbLocationTop; + uint64_t AmdDisplayPhyTuningSettingTableHeader; + uint64_t AmdDisplayPhyTuningSettingTableContent; + uint64_t AmdDdiContent; + uint64_t PeiGopConfigMemsize; + uint64_t PeiGopVmFbOffset; + uint64_t PeiGopVmFbLocationTop; uint32_t BootMode; uint32_t DisplayCapDdi0; uint32_t DisplayCapDdi1; @@ -91,4 +91,6 @@ typedef struct { uint8_t PwrDownBloffToVaryBlOff; uint8_t PwrOffDelay; uint8_t Usb4DpiaDisable; + uint8_t UmaMode; + uint32_t AmdUmaCarveoutIndexMax; } GFXCLASS_INPUT_BLK; diff --git a/xUSL/GFX/Phx/GfxDisplayPhySettings.c b/xUSL/GFX/Phx/GfxDisplayPhySettings.c index 8ca55f0..1a37bda 100644 --- a/xUSL/GFX/Phx/GfxDisplayPhySettings.c +++ b/xUSL/GFX/Phx/GfxDisplayPhySettings.c @@ -35,7 +35,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -60,7 +60,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -85,7 +85,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -110,7 +110,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -135,7 +135,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 5, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -160,7 +160,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -185,7 +185,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -210,7 +210,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 11, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -235,7 +235,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 15, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -260,7 +260,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 20, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -285,7 +285,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -310,7 +310,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -335,7 +335,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -360,7 +360,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -385,7 +385,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 5, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -410,7 +410,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -435,7 +435,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -460,7 +460,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 11, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -485,7 +485,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 15, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -510,7 +510,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 20, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -535,7 +535,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -560,7 +560,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -585,7 +585,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -610,7 +610,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -635,7 +635,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 4, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -660,7 +660,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -685,7 +685,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 7, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -710,7 +710,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -735,7 +735,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 12, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -760,7 +760,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -785,7 +785,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -810,7 +810,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -835,7 +835,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -860,7 +860,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -885,7 +885,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 4, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -910,7 +910,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -935,7 +935,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 7, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -960,7 +960,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -985,7 +985,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 12, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1010,7 +1010,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1035,7 +1035,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1060,7 +1060,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1085,7 +1085,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 11, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1110,7 +1110,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 14, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1135,7 +1135,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 19, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1160,7 +1160,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1185,7 +1185,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1210,7 +1210,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 10, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1235,7 +1235,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 14, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1260,7 +1260,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 17, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1285,7 +1285,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1310,7 +1310,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1335,7 +1335,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1360,7 +1360,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 13, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1385,7 +1385,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1410,7 +1410,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 3, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1435,7 +1435,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1460,7 +1460,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1485,7 +1485,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1510,7 +1510,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1535,7 +1535,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 4, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1560,7 +1560,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1585,7 +1585,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 7, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1610,7 +1610,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1635,7 +1635,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 12, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1660,7 +1660,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1685,7 +1685,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1710,7 +1710,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1735,7 +1735,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1760,7 +1760,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1785,7 +1785,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 4, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1810,7 +1810,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1835,7 +1835,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 7, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1860,7 +1860,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1885,7 +1885,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 12, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1910,7 +1910,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1935,7 +1935,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1960,7 +1960,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -1985,7 +1985,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2010,7 +2010,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2035,7 +2035,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 4, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2060,7 +2060,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2085,7 +2085,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 7, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2110,7 +2110,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2135,7 +2135,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 12, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2160,7 +2160,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2185,7 +2185,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2210,7 +2210,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2235,7 +2235,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2260,7 +2260,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2285,7 +2285,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 4, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2310,7 +2310,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2335,7 +2335,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 7, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2360,7 +2360,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2385,7 +2385,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 12, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2410,7 +2410,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2435,7 +2435,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2460,7 +2460,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2485,7 +2485,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2510,7 +2510,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2535,7 +2535,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 4, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2560,7 +2560,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2585,7 +2585,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 7, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2610,7 +2610,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2635,7 +2635,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 12, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2660,7 +2660,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2685,7 +2685,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2710,7 +2710,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2735,7 +2735,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2760,7 +2760,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2785,7 +2785,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 4, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2810,7 +2810,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 6, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2835,7 +2835,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 7, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2860,7 +2860,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 9, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2885,7 +2885,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 12, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2910,7 +2910,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2935,7 +2935,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2960,7 +2960,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -2985,7 +2985,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3010,7 +3010,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3035,7 +3035,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3060,7 +3060,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 0, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3085,7 +3085,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 8, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3110,7 +3110,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 10, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3135,7 +3135,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 13, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3160,7 +3160,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3185,7 +3185,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 8, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3210,7 +3210,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 10, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3235,7 +3235,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 13, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3260,7 +3260,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3285,7 +3285,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 8, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3310,7 +3310,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 10, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3335,7 +3335,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 13, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3360,7 +3360,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3385,7 +3385,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 8, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3410,7 +3410,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 10, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3435,7 +3435,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 13, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3460,7 +3460,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3485,7 +3485,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 8, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3510,7 +3510,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 10, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3535,7 +3535,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 13, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; @@ -3560,7 +3560,7 @@ ATOM_N6_DISPLAY_PHY_TUNING_SET display_phy_tuning_info[] = { 16, //uint8_t tx_eq_post; 0, //uint8_t tx_en_inv_pre; 0, //uint8_t tx_en_inv_post; - 0, //uint8_t reserved3; + 0, //uint8_t tx_slew_ctrl_val; 0, //uint32_t reserved4; 0, //uint32_t reserved5; 0, //uint32_t reserved6; diff --git a/xUSL/GFX/Phx/GfxEnumConnectorsPhx.c b/xUSL/GFX/Phx/GfxEnumConnectorsPhx.c new file mode 100644 index 0000000..f2904c4 --- /dev/null +++ b/xUSL/GFX/Phx/GfxEnumConnectorsPhx.c @@ -0,0 +1,747 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. */ + +/** + * @file GfxEnumConnectorsPhx.c + * @brief Phoenix GFX connector enumeration routines + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "GfxInitPhx.h" +#include + +#define ATOM_ENCODER_CAP_RECORD_HBR2_DISABLE 0x0001 +#define ATOM_ENCODER_CAP_RECORD_DP_FIXED_VS_EN 0x0002 +#define ATOM_ENCODER_CAP_RECORD_EXT_CHIP_MASK 0x007C +#define ATOM_ENCODER_CAP_RECORD_HDMI20_PI3EQX1204 (0x01 << 2 ) //PI redriver chip +#define ATOM_ENCODER_CAP_RECORD_HDMI20_TISN65DP159RSBT (0x02 << 2 ) //TI retimer chip +#define ATOM_ENCODER_CAP_RECORD_HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recoverter chip +#define ATOM_ENCODER_CAP_RECORD_HBR3_DISABLE 0x0080 +#define ATOM_ENCODER_CAP_RECORD_USB_C_TYPE 0x100 // the DP connector is a USB-C type. +#define ATOM_ENCODER_CAP_RECORD_HDMI20_DISABLE 0x200 +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +static PCIe_ENGINE_CONFIG DdiComplexDataPHX[] = { + //Ddi0 + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_ALLOCATED, + 0, + 0, + 0 + }, + {PcieDdiEngine, 16, 19}, + 0, //Initialization Status + 0xFF, //Scratch + {.Ddi={{0}}} //PCIe_DDI_CONFIG + }, + //Ddi1 + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_ALLOCATED, + 0, + 0, + 0 + }, + {PcieDdiEngine, 20, 23}, + 0, //Initialization Status + 0xFF, //Scratch + {.Ddi={{0}}} //PCIe_DDI_CONFIG + }, + //Ddi2 + { + { + DESCRIPTOR_DDI_ENGINE, + 0, + 0, + 0 + }, + {PcieDdiEngine, 24, 27}, + 0, //Initialization Status + 0xFF, //Scratch + {.Ddi={{0}}} //PCIe_DDI_CONFIG + }, + //Ddi3 + { + { + DESCRIPTOR_DDI_ENGINE, + 0, + 0, + 0 + }, + {PcieDdiEngine, 28, 31}, + 0, //Initialization Status + 0xFF, //Scratch + {.Ddi={{0}}} //PCIe_DDI_CONFIG + }, + //Ddi4 + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST, + 0, + 0, + 0 + }, + {PcieDdiEngine, 32, 35}, + 0, //Initialization Status + 0xFF, //Scratch + {.Ddi={{0}}} //PCIe_DDI_CONFIG + } +}; + +static EXT_CONNECTOR_INFO ConnectorInfoTable[] = { + { + ConnectorTypeDP, + DEVICE_DFP, + CONNECTOR_DISPLAYPORT_ENUM, + ENCODER_NOT_PRESENT, + 0, + }, + { + ConnectorTypeEDP, + DEVICE_DFP, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeSingleLinkDVI, + DEVICE_DFP, + CONNECTOR_SINGLE_LINK_DVI_D_ENUM, + ENCODER_NOT_PRESENT, + 2 + }, + { + ConnectorTypeDualLinkDVI, + DEVICE_DFP, + CONNECTOR_DUAL_LINK_DVI_D_ENUM, + ENCODER_NOT_PRESENT, + 3 + }, + { + ConnectorTypeHDMI, + DEVICE_DFP, + CONNECTOR_HDMI_TYPE_A_ENUM, + ENCODER_NOT_PRESENT, + 4 + }, + { + ConnectorTypeDpToVga, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_DP2VGA_ENUM_ID1, + 5 + }, + { + ConnectorTypeDpToLvds, + DEVICE_LCD, + CONNECTOR_LVDS_ENUM, + ENCODER_DP2LVDS_ENUM_ID2, + 6 + }, + { + ConnectorTypeNutmegDpToVga, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_ALMOND_ENUM_ID1, + 5 + }, + { + ConnectorTypeSingleLinkDviI, + DEVICE_DFP, + CONNECTOR_SINGLE_LINK_DVI_I_ENUM, + ENCODER_NOT_PRESENT, + 5 + }, + { + ConnectorTypeDpWithTypeC, + DEVICE_DFP, + CONNECTOR_DISPLAYPORT_ENUM, + ENCODER_NOT_PRESENT, + 0 + }, + { + ConnectorTypeDpWithoutTypeC, + DEVICE_DFP, + CONNECTOR_DISPLAYPORT_ENUM, + ENCODER_NOT_PRESENT, + 0 + }, + { + ConnectorTypeEDPToLvds, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeEDPToLvdsSwInit, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeAutoDetect, + DEVICE_LCD, + CONNECTOR_LVDS_eDP_ENUM, + ENCODER_DP2LVDS_ENUM_ID2, + 7 + }, + { + UnusedType, + 0, + 0, + 0, + 0 + }, +}; + + +/** + * GfxIntegratedExtConnectorInfo + * + * @brief Enumerate all display connectors for specific display device type. + * + * + * @param ConnectorType Connector type (see PCIe_DDI_DATA::ConnectorType). + * @retval Pointer to EXT_CONNECTOR_INFO, NULL if connector type unknown. + */ +static EXT_CONNECTOR_INFO* +GfxIntegratedExtConnectorInfo ( + uint8_t ConnectorType + ) +{ + size_t Index; + + for (Index = 0; Index < SIL_ARRAY_SIZE(ConnectorInfoTable); Index++) { + if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) { + return &ConnectorInfoTable[Index]; + } + } + + return NULL; +} + +static EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = { + { + DEVICE_CRT, + 1, + ATOM_DEVICE_CRT1_SUPPORT, + 0x100, + }, + { + DEVICE_LCD, + 1, + ATOM_DEVICE_LCD1_SUPPORT, + 0x110, + }, + { + DEVICE_DFP, + 1, + ATOM_DEVICE_DFP1_SUPPORT, + 0x210, + }, + { + DEVICE_DFP, + 2, + ATOM_DEVICE_DFP2_SUPPORT, + 0x220, + }, + { + DEVICE_DFP, + 3, + ATOM_DEVICE_DFP3_SUPPORT, + 0x230, + }, + { + DEVICE_DFP, + 4, + ATOM_DEVICE_DFP4_SUPPORT, + 0x240, + }, + { + DEVICE_DFP, + 5, + ATOM_DEVICE_DFP5_SUPPORT, + 0x250, + }, + { + DEVICE_DFP, + 6, + ATOM_DEVICE_DFP6_SUPPORT, + 0x260, + } +}; + +static uint32_t +GfxMappingUserConfigPhx ( + DDI_DESCRIPTOR *DdiConfig, + PCIe_ENGINE_CONFIG *Engine, + uint8_t *PriorityConnectorType + ) +{ + bool LocalFlag; + uint32_t Index; + uint32_t DfpCounter; + uint8_t DpCounter; + uint32_t NumbersOfDdi; + uint8_t eDpCounter; + + NumbersOfDdi = 0; + Index = 0; + DfpCounter = 0; + DpCounter = 0; + LocalFlag = false; + eDpCounter = 0; + + do { + Engine[Index].Type.Ddi.DdiData.ConnectorType = DdiConfig[Index].Ddi.ConnectorType; + Engine[Index].Type.Ddi.DdiData.AuxIndex = DdiConfig[Index].Ddi.AuxIndex; + Engine[Index].Type.Ddi.DdiData.HdpIndex = DdiConfig[Index].Ddi.HdpIndex; + Engine[Index].Type.Ddi.DdiData.LanePnInversionMask = DdiConfig[Index].Ddi.LanePnInversionMask; + Engine[Index].Type.Ddi.DdiData.Flags = DdiConfig[Index].Ddi.Flags; + + if (DdiConfig[Index].Flags == DESCRIPTOR_TERMINATE_LIST) { + LocalFlag = true; + } + //Init Priority Array + if (DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeEDP) { + eDpCounter++; + PriorityConnectorType[Index] = eDpCounter; + } + if (DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeDP || + DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeHDMI || + DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeSingleLinkDVI + || DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeDpWithTypeC || + DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeDpWithoutTypeC) { + DfpCounter++; + } + NumbersOfDdi++; + Index++; + } while (LocalFlag != true); + + // Assign Tag + while (DfpCounter != 0) { + for (Index = 0; Index < NumbersOfDdi; Index++) { + // Treate All Usb type C the same as DP + if (DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeDP || + DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeDpWithTypeC || + DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeDpWithoutTypeC) { + DpCounter++; + DfpCounter--; + PriorityConnectorType[Index] = DpCounter; + } + } + for (Index = 0; Index < NumbersOfDdi; Index++) { + if (DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeHDMI) { + DpCounter++; + DfpCounter--; + PriorityConnectorType[Index] = DpCounter; + } + } + for (Index = 0; Index < NumbersOfDdi; Index++) { + if (DdiConfig[Index].Ddi.ConnectorType == ConnectorTypeSingleLinkDVI) { + DpCounter++; + DfpCounter--; + PriorityConnectorType[Index] = DpCounter; + } + } + } + + return NumbersOfDdi; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] DisplayDeviceEnum Display device enum + * @param[in] DisplayDeviceIndex Display device index + * @retval Pointer to EXT_DISPLAY_DEVICE_INFO + * @retval NULL if can not get display device info + */ +static EXT_DISPLAY_DEVICE_INFO* +GfxIntegratedExtDisplayDeviceInfo ( + uint8_t DisplayDeviceEnum, + uint8_t DisplayDeviceIndex + ) +{ + uint8_t Index; + uint8_t LastIndex; + + LastIndex = 0xff; + + for (Index = 0; Index < SIL_ARRAY_SIZE(DisplayDeviceInfoTable); Index++) { + if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) { + LastIndex = Index; + if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) { + return &DisplayDeviceInfoTable[Index]; + } + } + } + if (DisplayDeviceEnum == DEVICE_LCD && LastIndex != 0xff) { + return &DisplayDeviceInfoTable[LastIndex]; + } + return NULL; +} + +/** + * GfxIntegratedEnumerateAllConnectorsPhx + * + * @brief Enumerate all display connectors + * + * @param SilContext openSIL context + * @param InputBlk GFX IP block configuration input data pointer + * @param DisplayPathList Display path list + */ +SIL_STATUS +GfxIntegratedEnumerateAllConnectorsPhx ( + SIL_CONTEXT *SilContext, + GFXCLASS_INPUT_BLK *InputBlk, + EXT_DISPLAY_PATH *DisplayPathList + ) +{ + SIL_STATUS Status; + PCIe_ENGINE_CONFIG DdiComplexData[NUM_DDI_PORTS]; + MPIO_COMPLEX_DESCRIPTOR *PcieTopologyData; + GFX_DDI_CONFIG_INFO *GfxDdiInputData; + MPIOCLASS_COMMON_INPUT_BLK *MpioData; + EXT_CONNECTOR_INFO *ExtConnectorInfo; + EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; + uint32_t DdiCounter; + EXT_DISPLAY_PATH *StoreDisplayPathList; + uint8_t DisplayDeviceIndex; + SOC_LOGICAL_ID LogicalId; + size_t NumbersOfDdi; + uint8_t PriorityConnectorType[NUM_DDI_PORTS] = {0}; + + GFX_TRACEPOINT(SIL_TRACE_ENTRY, "\n"); + + ExtDisplayDeviceInfo = NULL; + LogicalId.Revision = AMD_REVISION_UNKNOWN; + LogicalId.Family = AMD_FAMILY_UNKNOWN; + NumbersOfDdi = 0; + + MpioData = (MPIOCLASS_COMMON_INPUT_BLK *)xUslFindStructure(SilContext, + SilId_MpioClass, + MPIOCLASS_COMMON_INSTANCE + ); + + if (MpioData == NULL) { + return SilNotFound; + } + + memcpy(DdiComplexData, DdiComplexDataPHX, sizeof (PCIe_ENGINE_CONFIG) * NUM_DDI_PORTS); + PcieTopologyData = MpioData->PcieTopologyData.PlatformData; + GfxDdiInputData = (GFX_DDI_CONFIG_INFO *)xUslFindStructure(SilContext, + SilId_GfxClass, + GFXCLASS_DDI_INSTANCE + ); + + if ((PcieTopologyData->DdiLinkList == NULL) && (GfxDdiInputData != NULL)) { + PcieTopologyData->DdiLinkList = (MPIO_DDI_DESCRIPTOR *)GfxDdiInputData->ddi_descriptor; + } + + if (PcieTopologyData->DdiLinkList != NULL) { + NumbersOfDdi = GfxMappingUserConfigPhx ( + (DDI_DESCRIPTOR *)PcieTopologyData->DdiLinkList, + &DdiComplexData[0], + &PriorityConnectorType[0] + ); + } + + GFX_TRACEPOINT(SIL_TRACE_INFO, "NumbersOfDdi %x\n", NumbersOfDdi); + + StoreDisplayPathList = DisplayPathList; + DisplayDeviceIndex = 1; + + Status = GetSocLogicalIdOnCurrentCore (&LogicalId); + if (Status != SilPass) { + return Status; + } + + for (DdiCounter = 0; DdiCounter < NumbersOfDdi; DdiCounter++) { + ExtConnectorInfo = GfxIntegratedExtConnectorInfo( + DdiComplexData[DdiCounter].Type.Ddi.DdiData.ConnectorType + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, "Ddi[%d]\n", DdiCounter); + GFX_TRACEPOINT(SIL_TRACE_INFO, "ExtConnectorInfo %x\n", ExtConnectorInfo); + GFX_TRACEPOINT(SIL_TRACE_INFO, "ExtConnectorInfo->ConnectorType %x\n", + ExtConnectorInfo->ConnectorType); + + StoreDisplayPathList->usDeviceConnector = ExtConnectorInfo->ConnectorEnum | + (PriorityConnectorType[DdiCounter] << 8); + + GFX_TRACEPOINT(SIL_TRACE_INFO, "DisplayPathList->usDeviceConnector %x\n", + DisplayPathList->usDeviceConnector); + ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo( + ExtConnectorInfo->DisplayDeviceEnum, + PriorityConnectorType[DdiCounter] + ); + if (ExtDisplayDeviceInfo != NULL) { + StoreDisplayPathList->usDeviceTag = ExtDisplayDeviceInfo->DeviceTag; + StoreDisplayPathList->usDeviceACPIEnum = ExtDisplayDeviceInfo->DeviceAcpiEnum; + } else { + GFX_TRACEPOINT(SIL_TRACE_INFO, "Returned NULL ExtDisplayDeviceInfo\n"); + StoreDisplayPathList->usDeviceTag = 0; + StoreDisplayPathList->usDeviceACPIEnum = 0; + } + + //eDP Case + if (ExtConnectorInfo->ConnectorType == ConnectorTypeEDP) { + GFX_TRACEPOINT(SIL_TRACE_INFO, "StoreDisplayPathList->usDeviceConnector %x\n", \ + StoreDisplayPathList->usDeviceConnector); + if (StoreDisplayPathList->usDeviceConnector == (CONNECTOR_eDP_ENUM + (1 << 8))) { + StoreDisplayPathList->usDeviceTag = ATOM_DEVICE_LCD1_SUPPORT; + StoreDisplayPathList->usDeviceACPIEnum = 0x110; + } else { + StoreDisplayPathList->usDeviceTag = ATOM_DEVICE_LCD2_SUPPORT; + StoreDisplayPathList->usDeviceACPIEnum = 0x120; + } + } + + StoreDisplayPathList->ucExtAUXDDCLutIndex = DdiComplexData[DdiCounter].Type.Ddi.DdiData.AuxIndex; + StoreDisplayPathList->ucExtHPDPINLutIndex = DdiComplexData[DdiCounter].Type.Ddi.DdiData.HdpIndex; + StoreDisplayPathList->ucChannelMapping = 0xE4; + StoreDisplayPathList->ucChPNInvert = 0; + StoreDisplayPathList->usCaps = DdiComplexData[DdiCounter].Type.Ddi.DdiData.Flags; + + switch (DdiCounter) { + case 0: + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDP) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__DP2 | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeHDMI) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__HDMI_FRL_12GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_10GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_8GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL); + } + if (InputBlk->DisplayCapDdi0 != 0) { + StoreDisplayPathList->usCaps = InputBlk->DisplayCapDdi0; + } + break; + case 1: + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDP) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__DP2 | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeHDMI) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__HDMI_FRL_12GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_10GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_8GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL); + } + if (InputBlk->DisplayCapDdi1 != 0) { + StoreDisplayPathList->usCaps = InputBlk->DisplayCapDdi1; + } + break; + case 2: + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDP) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__DP2 | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeHDMI) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__HDMI_FRL_12GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_10GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_8GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDpWithTypeC) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__USB4_DPIA_ENABLE | + ATOM_ENCODER_CAP_RECORD_DP_FIXED_VS_EN); + + StoreDisplayPathList->usCaps |= (ATOM_ENCODER_CAP_RECORD_USB_C_TYPE | + EXT_DISPLAY_PATH_CAPS__DP2 | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDpWithoutTypeC) { + StoreDisplayPathList->usCaps &= (~ATOM_ENCODER_CAP_RECORD_USB_C_TYPE); + StoreDisplayPathList->usCaps &= (~EXT_DISPLAY_PATH_CAPS__USB4_DPIA_ENABLE); + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__DP2 | + ATOM_ENCODER_CAP_RECORD_DP_FIXED_VS_EN | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (InputBlk->DisplayCapDdi2 != 0) { + StoreDisplayPathList->usCaps = InputBlk->DisplayCapDdi2; + } + break; + case 3: + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDP) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__DP2 | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeHDMI) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__HDMI_FRL_12GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_10GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_8GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDpWithTypeC) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__USB4_DPIA_ENABLE | + ATOM_ENCODER_CAP_RECORD_DP_FIXED_VS_EN); + + StoreDisplayPathList->usCaps |= (ATOM_ENCODER_CAP_RECORD_USB_C_TYPE | + EXT_DISPLAY_PATH_CAPS__DP2 | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDpWithoutTypeC) { + StoreDisplayPathList->usCaps &= (~ATOM_ENCODER_CAP_RECORD_USB_C_TYPE); + StoreDisplayPathList->usCaps &= (~EXT_DISPLAY_PATH_CAPS__USB4_DPIA_ENABLE); + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__DP2 | + ATOM_ENCODER_CAP_RECORD_DP_FIXED_VS_EN | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (InputBlk->DisplayCapDdi3 != 0) { + StoreDisplayPathList->usCaps = InputBlk->DisplayCapDdi3; + } + break; + case 4: + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDP) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__DP2 | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeHDMI) { + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__HDMI_FRL_12GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_10GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL_8GbEn | + EXT_DISPLAY_PATH_CAPS__HDMI_FRL); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDpWithTypeC || + ExtConnectorInfo->ConnectorType == ConnectorTypeDpWithoutTypeC) { + if (LogicalId.Family == AMD_FAMILY_PHX) { + // Check if it is PHX2 AM5 + if (ISSOCPHX2AM5) { + GFX_TRACEPOINT(SIL_TRACE_INFO, "PHX2 AM5 GFX\n"); + StoreDisplayPathList->usCaps |= ATOM_ENCODER_CAP_RECORD_DP_FIXED_VS_EN; + } + if (ISSOCPHX1AM5) { + GFX_TRACEPOINT(SIL_TRACE_INFO, "PHX AM5 GFX\n"); + StoreDisplayPathList->usCaps |= ATOM_ENCODER_CAP_RECORD_DP_FIXED_VS_EN; + } + } + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDpWithTypeC) { + StoreDisplayPathList->usCaps |= ATOM_ENCODER_CAP_RECORD_USB_C_TYPE; + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__DP2 | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (ExtConnectorInfo->ConnectorType == ConnectorTypeDpWithoutTypeC) { + StoreDisplayPathList->usCaps &= (~ATOM_ENCODER_CAP_RECORD_USB_C_TYPE); + StoreDisplayPathList->usCaps &= (~EXT_DISPLAY_PATH_CAPS__USB4_DPIA_ENABLE); + StoreDisplayPathList->usCaps |= (EXT_DISPLAY_PATH_CAPS__DP2 | + EXT_DISPLAY_PATH_CAPS__UHBR10_EN); + } + if (InputBlk->DisplayCapDdi4 != 0) { + StoreDisplayPathList->usCaps = InputBlk->DisplayCapDdi4; + } + break; + default: + break; + } + + if (!InputBlk->Usb4Rt0En || !InputBlk->Usb4Rt0DpTnlEn) { + if (DdiCounter == 2) { + StoreDisplayPathList->usCaps &= (~EXT_DISPLAY_PATH_CAPS__USB4_DPIA_ENABLE); + } + } + + if (!InputBlk->Usb4Rt1En || !InputBlk->Usb4Rt1DpTnlEn) { + if (DdiCounter == 3) { + StoreDisplayPathList->usCaps &= (~EXT_DISPLAY_PATH_CAPS__USB4_DPIA_ENABLE); + } + } + + if (InputBlk->Usb4DpiaDisable){ + StoreDisplayPathList->usCaps &= (~EXT_DISPLAY_PATH_CAPS__USB4_DPIA_ENABLE); + } + + if (ExtConnectorInfo->ConnectorType == UnusedType) { + StoreDisplayPathList->usDeviceTag = 0; + StoreDisplayPathList->usDeviceACPIEnum = 0; + StoreDisplayPathList->usDeviceConnector = 0; + StoreDisplayPathList->ucExtAUXDDCLutIndex = 0; + StoreDisplayPathList->ucExtHPDPINLutIndex = 0; + StoreDisplayPathList->ucChannelMapping = 0; + StoreDisplayPathList->ucChPNInvert = 0; + StoreDisplayPathList->usCaps = 0; + StoreDisplayPathList->usExtEncoderObjId = 0; + } + + GFX_TRACEPOINT(SIL_TRACE_INFO, "Address of StoreDisplayPathList %x\n", + StoreDisplayPathList); + GFX_TRACEPOINT(SIL_TRACE_INFO, "Address of ExtConnectorInfo %x\n", + ExtConnectorInfo); + GFX_TRACEPOINT(SIL_TRACE_INFO, "StoreDisplayPathList usCaps: %x\n", + StoreDisplayPathList->usCaps); + + StoreDisplayPathList++; + if(ExtDisplayDeviceInfo != NULL) { + ExtDisplayDeviceInfo++; + } + DisplayDeviceIndex++; + } + + GFX_TRACEPOINT(SIL_TRACE_INFO, "AmdBitMapDisaplyOnlyController [0x%x]\n", + InputBlk->AmdBitMapDisaplyOnlyController); + + GFX_TRACEPOINT(SIL_TRACE_EXIT, "\n"); + + return SilPass; +} + +/** + * Dump display path settings + * + * @param[in] DisplayPath Display path + */ + +void +GfxIntegratedDebugDumpDisplayPath ( + EXT_DISPLAY_PATH *DisplayPath + ) +{ + GFX_TRACEPOINT(SIL_TRACE_INFO, " usDeviceConnector = 0x%x\n", + DisplayPath->usDeviceConnector + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, " usDeviceTag = 0x%x\n", + DisplayPath->usDeviceTag + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, " usDeviceACPIEnum = 0x%x\n", + DisplayPath->usDeviceACPIEnum + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, " ucExtAUXDDCLutIndex = 0x%x\n", + DisplayPath->ucExtAUXDDCLutIndex + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, " ucExtHPDPINLutIndex = 0x%x\n", + DisplayPath->ucExtHPDPINLutIndex + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, " usExtEncoderObjId = 0x%x\n", + DisplayPath->usExtEncoderObjId + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, " ucChannelMapping = 0x%x\n", + DisplayPath->ucChannelMapping + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, " ucChPNInvert = 0x%x\n", + DisplayPath->ucChPNInvert + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, " usCaps = 0x%x\n", + DisplayPath->usCaps + ); +} diff --git a/xUSL/GFX/Phx/GfxInfoCollectionPhx.c b/xUSL/GFX/Phx/GfxInfoCollectionPhx.c new file mode 100644 index 0000000..4f4a8e9 --- /dev/null +++ b/xUSL/GFX/Phx/GfxInfoCollectionPhx.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. */ + +/** + * @file GfxInfoCollectionPhx.c + * @brief Phoenix GFX device information collection + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "GfxInitPhx.h" +#include + +static bool +IsNonInterleavingRegionExist ( + SIL_CONTEXT *SilContext + ) +{ + uint32_t Index; + SIL_STATUS Status; + SIL_RESERVED_UNION_0009 DramAddressCtl; + DRAM_ADDRESS_INTLV_REGISTER DramAddressIntlv; + DF_IP2IP_API *DfIp2IpApi; + + Status = SilGetIp2IpApi(SilContext, SilId_DfClass, (void **) &DfIp2IpApi); + assert(Status == SilPass); + + for (Index = 0; Index < 2; Index++) { + DramAddressCtl.Value = DfIp2IpApi->DfFabricRegisterAccRead(SilContext, + 0, + 0, + DRAMADDRESSCTL0_FUNC, + (DFXFABx208 + (Index * (DFXFABx218 - DFXFABx208))), + PHX_IOM0_INSTANCE_ID + ); + DramAddressIntlv.Value = DfIp2IpApi->DfFabricRegisterAccRead(SilContext, + 0, + 0, + DRAMADDRESSINTLV_0_FUNC, + (DFXFABx20C + (Index * (DFXFABx21C - DFXFABx20C))), + PHX_IOM0_INSTANCE_ID + ); + if ((DramAddressCtl.Field.field_bit_0 == 1) && (DramAddressIntlv.Field.IntLvNumChan == 0)) { + GFX_TRACEPOINT(SIL_TRACE_INFO, " non-interleaving region exist: TRUE\n"); + return true; + } + } + + GFX_TRACEPOINT(SIL_TRACE_INFO, " non-interleaving region exist: FALSE\n"); + return false; +} + +/** + * PopulateSystemInfoTablePhx + * + * @brief Populate SystemInfoTable with values from input block + * + * @param SilContext openSIL context + * @param InputBlk Pointer to the GFX iP block input data + * @param SystemInfoTable Pointer to a SystemInfoTable + */ +void +PopulateSystemInfoTablePhx ( + SIL_CONTEXT *SilContext, + GFXCLASS_INPUT_BLK *InputBlk, + ATOM_FUSION_SYSTEM_INFO_V6 *SystemInfoTable + ) +{ + uint8_t Index; + uint32_t PackageType; + + GFX_TRACEPOINT(SIL_TRACE_ENTRY, "\n"); + + memset(SystemInfoTable, 0, sizeof (ATOM_FUSION_SYSTEM_INFO_V6)); + + SystemInfoTable->sIntegratedSysInfo.table_header.structuresize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V2_2); + SystemInfoTable->sIntegratedSysInfo.table_header.format_revision = 2; + SystemInfoTable->sIntegratedSysInfo.table_header.content_revision = 2; + GFX_TRACEPOINT(SIL_TRACE_INFO, "ATOM_INTEGRATED_SYSTEM_INFO_V2_2 size[%x] Ver%d.%d\n", + SystemInfoTable->sIntegratedSysInfo.table_header.structuresize, + SystemInfoTable->sIntegratedSysInfo.table_header.format_revision, + SystemInfoTable->sIntegratedSysInfo.table_header.content_revision + ); + + SystemInfoTable->sIntegratedSysInfo.vbios_misc = 0; + if (IsNonInterleavingRegionExist (SilContext)) { + SystemInfoTable->sIntegratedSysInfo.vbios_misc |= BIT_32(7); + } + + SystemInfoTable->sIntegratedSysInfo.UMACarveoutIndexMax = InputBlk->AmdUmaCarveoutIndexMax; + SystemInfoTable->sIntegratedSysInfo.UMACarveoutIndexDefault = (InputBlk->UmaMode == 3) ? 2 : 1; + SystemInfoTable->sIntegratedSysInfo.UMACarveoutID[0] = 1; + SystemInfoTable->sIntegratedSysInfo.UMACarveoutID[1] = 2; + + if (InputBlk->UmaMode == 1) { + SystemInfoTable->sIntegratedSysInfo.UMACarveoutIndexMax = 0; + } + + SystemInfoTable->sIntegratedSysInfo.gpucapinfo = 0; + SystemInfoTable->sIntegratedSysInfo.system_config = 0; + + SystemInfoTable->sIntegratedSysInfo.cpucapinfo = 0; + SystemInfoTable->sIntegratedSysInfo.gpuclk_ss_percentage = InputBlk->CfgPcieRefClkSpreadSpectrum; + SystemInfoTable->sIntegratedSysInfo.gpuclk_ss_type = 0; + SystemInfoTable->sIntegratedSysInfo.dpphy_override = InputBlk->AmdDpPhyOverride; + + SystemInfoTable->sIntegratedSysInfo.htc_hyst_limit = 0; + SystemInfoTable->sIntegratedSysInfo.htc_tmp_limit = 0; + + SystemInfoTable->sIntegratedSysInfo.extdispconninfo.sHeader.structuresize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); + SystemInfoTable->sIntegratedSysInfo.extdispconninfo.sHeader.format_revision = 1; + SystemInfoTable->sIntegratedSysInfo.extdispconninfo.sHeader.content_revision = 1; + SystemInfoTable->sIntegratedSysInfo.extdispconninfo.stereopinid = 0; + SystemInfoTable->sIntegratedSysInfo.extdispconninfo.ucRemoteDisplayConfig = 0; + SystemInfoTable->sIntegratedSysInfo.extdispconninfo.ucFixDPVoltageSwing = InputBlk->DisplayFixVoltageSwing; + + SystemInfoTable->sIntegratedSysInfo.edp1_info.edp_backlight_pwm_hz = InputBlk->BackLightPwmHz; + SystemInfoTable->sIntegratedSysInfo.edp1_info.edp_pwr_on_vary_bl_to_blon = InputBlk->PwrOnVaryBlToBlon; + SystemInfoTable->sIntegratedSysInfo.edp1_info.edp_pwr_down_bloff_to_vary_bloff = InputBlk->PwrDownBloffToVaryBlOff; + SystemInfoTable->sIntegratedSysInfo.edp1_info.edp_pwr_on_off_delay = InputBlk->PwrOffDelay; + + SystemInfoTable->sIntegratedSysInfo.edp2_info.edp_backlight_pwm_hz = InputBlk->BackLightPwmHz; + SystemInfoTable->sIntegratedSysInfo.edp2_info.edp_pwr_on_vary_bl_to_blon = InputBlk->PwrOnVaryBlToBlon; + SystemInfoTable->sIntegratedSysInfo.edp2_info.edp_pwr_down_bloff_to_vary_bloff = InputBlk->PwrDownBloffToVaryBlOff; + SystemInfoTable->sIntegratedSysInfo.edp2_info.edp_pwr_on_off_delay =InputBlk->PwrOffDelay; + + if (InputBlk->SysInfoTconInstantOnLogoSupport) { + SystemInfoTable->sIntegratedSysInfo.gpucapinfo |= SYS_INFO_GPUCAPS__TCON_INSTANT_ON_LOGO; + } + if (InputBlk->CfgSysInfoGpuCapsDdsSupport) { + SystemInfoTable->sIntegratedSysInfo.gpucapinfo |= SYS_INFO_GPUCAPS__DDS_SUPPORT; + } + if (InputBlk->CfgSysInfoGpuCapsBr3SdrSupport) { + SystemInfoTable->sIntegratedSysInfo.gpucapinfo |= SYS_INFO_GPUCAPS__BR3_SDR_SUPPORT; + } + + PackageType = xUSLGetPackageType(); + if ((1 << ZEN4_PKG_FP8) == PackageType) { + SystemInfoTable->sIntegratedSysInfo.gpu_package_id = ZEN4_PKG_FP8; + } else if ((1 << ZEN4_PKG_FP7) == PackageType) { + SystemInfoTable->sIntegratedSysInfo.gpu_package_id = ZEN4_PKG_FP7; + } else if ((1 << ZEN4_PKG_FP7r2) == PackageType) { + SystemInfoTable->sIntegratedSysInfo.gpu_package_id = ZEN4_PKG_FP7r2; + } + + GfxIntegratedEnumerateAllConnectorsPhx(SilContext, + InputBlk, + &SystemInfoTable->sIntegratedSysInfo.extdispconninfo.sPath[0] + ); + + for (Index = 0; Index < NUM_DDI_PORTS; Index++) { + GFX_TRACEPOINT(SIL_TRACE_INFO, "sPath[%x] address 0x%x\n", + Index, &SystemInfoTable->sIntegratedSysInfo.extdispconninfo.sPath[Index]); + GfxIntegratedDebugDumpDisplayPath( + &SystemInfoTable->sIntegratedSysInfo.extdispconninfo.sPath[Index] + ); + } + + GFX_TRACEPOINT(SIL_TRACE_EXIT, "\n"); +} diff --git a/xUSL/GFX/Phx/GfxInitPhx.c b/xUSL/GFX/Phx/GfxInitPhx.c new file mode 100644 index 0000000..6fb1412 --- /dev/null +++ b/xUSL/GFX/Phx/GfxInitPhx.c @@ -0,0 +1,412 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. */ + +/** + * @file GfxPhx.c + * @brief GFX configuration routines + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "GfxInitPhx.h" +#include "GfxPhx.h" +#include + +#define MAX_DMCUB_SIZE (1024 * 1024) //1024KB is max DMCUB size +#define MAX_IP_DISCOVERY_SIZE (64 * 1024) //64KB is max IP discovery size + +/** + * ApplyIntegratedSysInfoOverride + * + * @brief To apply IntegratedSysInfo Override + * + * @param SysInfoBuffer Pointer to ATOM_FUSION_SYSTEM_INFO_V6 buffer + * + * @return SIL_STATUS + */ +static void +ApplyIntegratedSysInfoOverridePhx ( + SIL_CONTEXT *SilContext, + GNB_HANDLE *GnbHandle, + ATOM_FUSION_SYSTEM_INFO_V6 *SysInfoBuffer + ) +{ + uint32_t DdrType; + uint32_t NumOfUmcPerSoc; + uint32_t NumOfUmcPerChan; + uint32_t NumOfActiveChan; + uint32_t Umc; + uint32_t AddrMaskDimm0; + uint32_t AddrMaskDimm1; + uint32_t UmcConfig; + + // Soc relevant + NumOfUmcPerSoc = 2; + NumOfUmcPerChan = 0; + + // Check Dram Type + DdrType = 0; + for (Umc = 0; Umc < NumOfUmcPerSoc; Umc++) { + UmcConfig = 0; + UmcConfig = xUSLSmnRead( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + 0x50100 + (Umc << 20)); + DdrType |= (UmcConfig & 0x7); + } + + + switch (DdrType) { + case 1: // DDR5 + NumOfUmcPerChan = 1; + SysInfoBuffer->sIntegratedSysInfo.memorytype = Ddr5MemType; + break; + case 6: // LPDDR5 + NumOfUmcPerChan = 1; + SysInfoBuffer->sIntegratedSysInfo.memorytype = LpDdr5MemType; + break; + default: + GFX_TRACEPOINT(SIL_TRACE_ERROR, "Invalid Dram Type!\n"); + assert (false); + break; + } + + GFX_TRACEPOINT(SIL_TRACE_INFO, "Memory Type = 0x%x\n", SysInfoBuffer->sIntegratedSysInfo.memorytype); + + // Check Active Package Channel + NumOfActiveChan = 0; + for (Umc = 0; Umc < NumOfUmcPerSoc; Umc += NumOfUmcPerChan) { + AddrMaskDimm0 = xUSLSmnRead( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + 0x50020 + (Umc << 20)); + AddrMaskDimm1 = xUSLSmnRead( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + 0x50024 + (Umc << 20)); + + if ((AddrMaskDimm0 | AddrMaskDimm1) != 0) { + NumOfActiveChan ++; + } + } + + SysInfoBuffer->sIntegratedSysInfo.umachannelnumber = (uint8_t) NumOfActiveChan; + GFX_TRACEPOINT(SIL_TRACE_INFO, "Umachannelnumber %x\n", SysInfoBuffer->sIntegratedSysInfo.umachannelnumber); +} + +static void +WriteRecoveryBiosram ( + void + ) +{ + xUSLMemReadModifyWrite8((void *)(size_t)(ACPI_MMIO_BASE + PMIO_BASE + FCH_PM_ISACONTROL), + (uint8_t) ~BIT_8(1), + BIT_8(1) + ); + + xUSLMemWrite8((void *)(size_t)(0xFED10088), 0x5A); +} + +/** + * ProgramUMARegister + * + * @brief ProgramUMARegister for PHX + * + * @return SIL_STATUS + */ +static SIL_STATUS +ProgramUMARegister ( + GFXCLASS_INPUT_BLK *InputBlk, + GNB_HANDLE *GnbHandle, + MEMORY_HOLE_DESCRIPTOR *MemoryRange, + bool IsRecovery + ) +{ + uint64_t TopOfMemory; + uint64_t TopOfMemory2; + uint32_t Value; + + GFX_TRACEPOINT (SIL_TRACE_ENTRY, "\n"); + + if (IsRecovery && InputBlk->PeiGopEnable) { + if (ISSOCPHXAM5) { + GFX_TRACEPOINT (SIL_TRACE_INFO, "PHX or PHX2 AM5 SMU MemoryRange->Base %lx \n", MemoryRange->Base); + if ((MemoryRange->Base > 0x100000000ULL) && (sizeof(uintptr_t) < 8)) { + GFX_TRACEPOINT (SIL_TRACE_INFO, "UMA is above4G, set Recovery Flag as 0x5A for ABL setting \n"); + WriteRecoveryBiosram(); + GFX_TRACEPOINT (SIL_TRACE_INFO, "Issue cf9 reset\n"); + return SilResetRequestColdImm; + } + } + } + + InputBlk->PeiGopConfigMemsize = MemoryRange->Size >> 20; + InputBlk->PeiGopVmFbOffset = MemoryRange->Base >> 24; + InputBlk->PeiGopVmFbLocationTop = (MemoryRange->Base + MemoryRange->Size - 1) >> 24; + GFX_TRACEPOINT (SIL_TRACE_INFO, "PeiGopConfigMemsize : %lx\n", InputBlk->PeiGopConfigMemsize); + GFX_TRACEPOINT (SIL_TRACE_INFO, "PeiGopVmFbOffset : %lx\n", InputBlk->PeiGopVmFbOffset); + GFX_TRACEPOINT (SIL_TRACE_INFO, "PeiGopVmFbLocationTop : %lx\n", InputBlk->PeiGopVmFbLocationTop); + + TopOfMemory = xUslRdMsr(MSR_TOM); + xUSLSmnReadModifyWrite( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + GNBREGx6a350, + ~(uint32_t)(0xff800000), + (uint32_t)TopOfMemory + ); + + TopOfMemory2 = xUslRdMsr(MSR_TOM2); + xUSLSmnReadModifyWrite( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + GNBREGx6a354, + ~(uint32_t)(0xff800001), + (uint32_t)(TopOfMemory2 | 1) + ); + + xUSLSmnReadModifyWrite( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + GNBREGx6a358, + ~(uint32_t)(0xfff), + (uint32_t)(TopOfMemory2 >> 32) + ); + + Value = xUSLSmnRead( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + IOHCx13b1005c); + xUSLSmnWrite( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + GNBREGx6a340, + Value); + + Value = xUSLSmnRead( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + IOHCx13b10060); + xUSLSmnWrite( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + GNBREGx6a344, + Value); + + Value = xUSLSmnRead( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + IOHCx13b00084); + xUSLSmnReadModifyWrite( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + GNBREGx6a34c, + ~BIT_32(3), + Value & BIT_32(3) + ); + + Value = xUSLSmnRead( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + IOHCx13b0004c); + + xUSLSmnReadModifyWrite( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + GNBREGx6a348, + ~BIT_32(23), + Value & BIT_32(23) + ); + + if (InputBlk->CfgMaxNumAudioEndpoints != 0) { + Value = (7 - InputBlk->CfgMaxNumAudioEndpoints) & 7; + Value |= BIT_32(4); + xUSLSmnWrite( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + AZALIAxe370, + Value); + } + + if (InputBlk->CfgDisableAllNumAudioEndpoints) { + xUSLSmnWrite( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + AZALIAxe370, + (7 | BIT_32(4)) + ); + } + + GFX_TRACEPOINT (SIL_TRACE_EXIT, "\n"); + + return SilPass; +} + +/** + * GfxInitPhx + * + * @brief Gfx driver entry point for PHX + * + * @param[in] SilContext Pointer to openSIL context + * @param[in] InputBlk Pointer to the GFX IP block input data + * + * @retval SIL_STATUS + */ +SIL_STATUS +GfxInitPhx ( + SIL_CONTEXT *SilContext, + GFXCLASS_INPUT_BLK *InputBlk + ) +{ + SIL_STATUS Status; + ATOM_FUSION_SYSTEM_INFO_V6 SystemInfoTable; + uintptr_t UMAPeiGopDestination; + bool ProgramValues; + MEMORY_HOLE_DESCRIPTOR Range = {0}; + GNB_HANDLE *GnbHandle; + bool IsRecovery; + ATOM_DISPLAY_PHY_TUNING_INFO *DispPhyTuningInfo; + NBIO_IP2IP_API *NbioIp2Ip; + NBIOCLASS_DATA_BLOCK *NbioData; + + GFX_TRACEPOINT(SIL_TRACE_ENTRY, "\n"); + + IsRecovery = false; + UMAPeiGopDestination = 0; + IsRecovery = (InputBlk->BootMode == 0x20); /* EFI_BOOT_IN_RECOVERY_MODE */ + + NbioData = GetNbioBlockData(SilContext); + if (NbioData != NULL) { + InputBlk->CfgIgpuControl = NbioData->NbioConfigData.CfgIgpuControl; + /* Sync with NBIO data, as it could change the config value based on fuse */ + InputBlk->CfgIgpuControl = NbioData->NbioConfigData.CfgIgpuControl; + } + + if ((InputBlk->AmdPreSilCtrl1 & BIT_32(12)) != 0) { + return SilPass; + } + + if (SilGetIp2IpApi(SilContext, SilId_NbioClass, (void **)(&NbioIp2Ip)) != SilPass) { + GFX_TRACEPOINT(SIL_TRACE_ERROR, " NBIO API is not found.\n"); + return SilNotFound; + } + + GnbHandle = NbioIp2Ip->GetGnbHandle(SilContext); + if (GnbHandle == NULL) { + return SilNotFound; + } + + // Get memory location for system info table + Status = GetUmaInformation(SilContext, &Range); + ProgramValues = (Status == SilPass); + + if (!ProgramValues) { + return SilPass; + } + + if (SilFchReadSleepType () == 0x3) { + return SilPass; + } + + PopulateSystemInfoTablePhx(SilContext, InputBlk, &SystemInfoTable); + ApplyIntegratedSysInfoOverridePhx(SilContext, GnbHandle, &SystemInfoTable); + Status = ProgramUMARegister(InputBlk, GnbHandle, &Range, IsRecovery); + /* ProgramUMARegister may return reset request, so return immediately */ + if (Status != SilPass) { + return Status; + } + + if ((IsRecovery || (sizeof(uintptr_t) == 8)) && InputBlk->PeiGopEnable) { + /* + * In this case, UMA integrated table need report in PEI phase. + * Copy integrated table to UMA - IP discovery - DMCUB. + */ + UMAPeiGopDestination = (uintptr_t)(Range.Base + Range.Size); + UMAPeiGopDestination -= MAX_IP_DISCOVERY_SIZE; + UMAPeiGopDestination -= MAX_DMCUB_SIZE; + UMAPeiGopDestination -= sizeof(ATOM_FUSION_SYSTEM_INFO_V6); + + GFX_TRACEPOINT(SIL_TRACE_INFO, "UMAPeiGopDestination %p\n", (void *)UMAPeiGopDestination); + + memcpy((void *)UMAPeiGopDestination, &SystemInfoTable, sizeof(ATOM_FUSION_SYSTEM_INFO_V6)); + + // UMA Top - IP Discovery - Integrated table - Phy header - phy tunning setting data + UMAPeiGopDestination -= sizeof(ATOM_COMMON_TABLE_HEADER); + DispPhyTuningInfo = (ATOM_DISPLAY_PHY_TUNING_INFO *)SilFindStructure(SilContext, + SilId_GfxClass, + GFXCLASS_N6_INSTANCE + ); + + if (DispPhyTuningInfo != NULL) { + GFX_TRACEPOINT(SIL_TRACE_INFO, "Done DispPhyTuningInfo->table_header.structuresize %x\n", + DispPhyTuningInfo->table_header.structuresize); + GFX_TRACEPOINT(SIL_TRACE_INFO, "Done DispPhyTuningInfo->table_header.content_revision %x\n", + DispPhyTuningInfo->table_header.content_revision); + GFX_TRACEPOINT(SIL_TRACE_INFO, "Done DispPhyTuningInfo->table_header.format_revision %x\n", + DispPhyTuningInfo->table_header.format_revision); + + memcpy ((void *)UMAPeiGopDestination, + (void *)&DispPhyTuningInfo->table_header, + sizeof(ATOM_COMMON_TABLE_HEADER) + ); + + GFX_TRACEPOINT(SIL_TRACE_INFO, "Done ATOM_COMMON_TABLE_HEADER %p\n", (void *)UMAPeiGopDestination); + UMAPeiGopDestination = (UMAPeiGopDestination + sizeof(ATOM_COMMON_TABLE_HEADER)) - (DispPhyTuningInfo->table_header.structuresize); + memcpy((void *)UMAPeiGopDestination, + (void *)&DispPhyTuningInfo->disp_phy_tuning, + (DispPhyTuningInfo->table_header.structuresize - sizeof(ATOM_COMMON_TABLE_HEADER))); + + GFX_TRACEPOINT(SIL_TRACE_INFO, "Done UMAPeiGopDestination %p\n", (void *)UMAPeiGopDestination); + } + } + + GFX_TRACEPOINT(SIL_TRACE_ENTRY, "\n"); + + return SilPass; +} + +void +SilDumpDdiTable ( + DDI_DESCRIPTOR *DdiConfigData + ) +{ + uint8_t index; + + for (index = 0; index < 5; index++) { + GFX_TRACEPOINT(SIL_TRACE_INFO, + "SIL: Ddi ConnectorType 0x%x \n", + DdiConfigData[index].Ddi.ConnectorType + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, + "SIL: Ddi AuxInde 0x%x \n", + DdiConfigData[index].Ddi.AuxIndex + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, + "SIL: Ddi HdpIndex 0x%x \n", + DdiConfigData[index].Ddi.HdpIndex + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, + "SIL: Ddi LanePnInversionMask 0x%x \n", + DdiConfigData[index].Ddi.LanePnInversionMask + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, + "SIL: Ddi Flags 0x%x \n", + DdiConfigData[index].Ddi.Flags + ); + GFX_TRACEPOINT(SIL_TRACE_INFO, "SIL: Flags 0x%x \n", DdiConfigData[index].Flags); + } + +} diff --git a/xUSL/GFX/Phx/GfxInitPhx.h b/xUSL/GFX/Phx/GfxInitPhx.h new file mode 100644 index 0000000..439123e --- /dev/null +++ b/xUSL/GFX/Phx/GfxInitPhx.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. */ + +/** + * @file GfxInitPhx.h + * @brief GFX function prototypes, structs, and defines + */ + +#pragma once + +#include +#include +#include + +#define NUM_DDI_PORTS 5 + +typedef struct { + PCIE_CONNECTOR_TYPE ConnectorType; + uint8_t DisplayDeviceEnum; + uint16_t ConnectorEnum; + uint16_t EncoderEnum; + uint8_t ConnectorIndex; +} EXT_CONNECTOR_INFO; + +typedef struct { + uint8_t DisplayDeviceEnum; + uint8_t DeviceIndex; + uint16_t DeviceTag; + uint16_t DeviceAcpiEnum; +} EXT_DISPLAY_DEVICE_INFO; + +typedef struct { + SIL_STATUS Status; + uint8_t DisplayDeviceEnum; + uint8_t RequestedPriorityIndex; + uint8_t CurrentPriorityIndex; + PCIe_ENGINE_CONFIG *Engine; +} CONNECTOR_ENUM_INFO; + +void +GfxIntegratedDebugDumpDisplayPath ( + EXT_DISPLAY_PATH *DisplayPath + ); + +SIL_STATUS +GfxIntegratedEnumerateAllConnectorsPhx ( + SIL_CONTEXT *SilContext, + GFXCLASS_INPUT_BLK *InputBlk, + EXT_DISPLAY_PATH *DisplayPathList + ); + +void +PopulateSystemInfoTablePhx ( + SIL_CONTEXT *SilContext, + GFXCLASS_INPUT_BLK *InputBlk, + ATOM_FUSION_SYSTEM_INFO_V6 *SystemInfoTable + ); + +SIL_STATUS +GfxInitPhx ( + SIL_CONTEXT *SilContext, + GFXCLASS_INPUT_BLK *InputBlk + ); diff --git a/xUSL/GFX/Phx/GfxPhx.c b/xUSL/GFX/Phx/GfxPhx.c index fdea1d9..8dbf7ed 100644 --- a/xUSL/GFX/Phx/GfxPhx.c +++ b/xUSL/GFX/Phx/GfxPhx.c @@ -14,6 +14,7 @@ #include #include #include +#include "GfxInitPhx.h" #include "GfxPhx.h" /** @@ -31,6 +32,8 @@ InitializeGfxPhxTp1 ( SIL_CONTEXT *SilContext ) { + SIL_STATUS Status; + GFXCLASS_INPUT_BLK *GfxConfigData; uint32_t InfoN6BlockDataSize; uint32_t InfoDdiBlockDataSize; @@ -40,11 +43,22 @@ InitializeGfxPhxTp1 ( */ GFX_TRACEPOINT(SIL_TRACE_ENTRY, "\n"); + GfxConfigData = (GFXCLASS_INPUT_BLK *)xUslFindStructure(SilContext, + SilId_GfxClass, + GFXCLASS_INSTANCE + ); + + if (GfxConfigData == NULL) { + GFX_TRACEPOINT(SIL_TRACE_ERROR, "GFX input block not found\n"); + return SilNotFound; + } + GetGfxN6Config(SilContext, &InfoN6BlockDataSize); GetGfxDdiConfig(SilContext, &InfoDdiBlockDataSize); + Status = GfxInitPhx(SilContext, GfxConfigData); GFX_TRACEPOINT(SIL_TRACE_EXIT, "\n"); - return SilPass; + return Status; } /** diff --git a/xUSL/GFX/Phx/meson.build b/xUSL/GFX/Phx/meson.build index e4f2ac1..c03d177 100644 --- a/xUSL/GFX/Phx/meson.build +++ b/xUSL/GFX/Phx/meson.build @@ -5,4 +5,7 @@ xusl += files([ 'GfxDisplayPhySettings.c', 'GfxDisplayTypeSettings.c', + 'GfxEnumConnectorsPhx.c', + 'GfxInfoCollectionPhx.c', + 'GfxInitPhx.c', 'GfxPhx.c' ]) diff --git a/xUSL/GFX/meson.build b/xUSL/GFX/meson.build index 3accfbe..27f6f5e 100644 --- a/xUSL/GFX/meson.build +++ b/xUSL/GFX/meson.build @@ -1,6 +1,8 @@ # SPDX-License-Identifier: MIT # Copyright (C) 2021 - 2025 Advanced Micro Devices, Inc. All rights reserved. +incdir += include_directories( '.' ) + subdir('Common') subdir('Phx') diff --git a/xUSL/Mpio/Common/MpioTopology.c b/xUSL/Mpio/Common/MpioTopology.c index 73065db..c000c7f 100644 --- a/xUSL/Mpio/Common/MpioTopology.c +++ b/xUSL/Mpio/Common/MpioTopology.c @@ -36,8 +36,11 @@ MpioUserDescriptorConfigDump ( (EngineDescriptor->EngineData.EngineType == MpioUnusedEngine) ? "Unused" : "Invalid") ); MPIO_TRACEPOINT(SIL_TRACE_INFO, - " Start Phy Lane - %d\n End Phy Lane - %d\n", - EngineDescriptor->EngineData.StartLane, + " Start Phy Lane - %d\n", + EngineDescriptor->EngineData.StartLane + ); + MPIO_TRACEPOINT(SIL_TRACE_INFO, + " End Phy Lane - %d\n", EngineDescriptor->EngineData.EndLane ); MPIO_TRACEPOINT(SIL_TRACE_INFO, " Hotplug - %d\n", EngineDescriptor->EngineData.HotPluggable); diff --git a/xUSL/Nbio/Common/PciStructs.h b/xUSL/Nbio/Common/PciStructs.h index 1629688..4e5f3aa 100644 --- a/xUSL/Nbio/Common/PciStructs.h +++ b/xUSL/Nbio/Common/PciStructs.h @@ -334,15 +334,16 @@ typedef enum { ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D ConnectorTypeHDMI, ///< HDMI ConnectorTypeDpToVga, ///< DP-to-VGA - ConnectorTypeReserved1, ///< Reserved - ConnectorTypeReserved2, ///< Reserved + ConnectorTypeDpToLvds, ///< DP-to-LVDS + ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I ConnectorTypeDpWithTypeC, ///< DP with USB type C + ConnectorTypeDpWithTypeCWithoutRetimer, ///< DP with USB type C without Retimer ConnectorTypeDpWithoutTypeC, ///< DP without USB type C - ConnectorTypeReserved3, ///< Reserved - ConnectorTypeReserved4, ///< Reserved - ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type - UnusedType, ///< UnusedType + ConnectorTypeEDPToLvds, ///< 3rd party common eDP-to-LVDS translator chip without AMD SW init + ConnectorTypeEDPToLvdsSwInit, ///< 3rd party eDP-to-LVDS translator which requires AMD SW init + ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or DP-to-LVDS) + UnusedType, ///< UnusedType MaxConnectorType ///< Not valid value, used to verify input } PCIE_CONNECTOR_TYPE; diff --git a/xUSL/Nbio/Phx/includePHX/PHX_AZALIA.h b/xUSL/Nbio/Phx/includePHX/PHX_AZALIA.h index 37777f2..0c49908 100644 --- a/xUSL/Nbio/Phx/includePHX/PHX_AZALIA.h +++ b/xUSL/Nbio/Phx/includePHX/PHX_AZALIA.h @@ -7,4 +7,6 @@ #pragma once +#define AZALIAxe370 0xe370UL + #define AZALIAx1200008 0x1200008UL diff --git a/xUSL/Nbio/Phx/includePHX/PHX_GnbRegistersPhx.h b/xUSL/Nbio/Phx/includePHX/PHX_GnbRegistersPhx.h index 734c47a..138530d 100644 --- a/xUSL/Nbio/Phx/includePHX/PHX_GnbRegistersPhx.h +++ b/xUSL/Nbio/Phx/includePHX/PHX_GnbRegistersPhx.h @@ -60,3 +60,11 @@ #define PCIECOREx1128047c 0x1128047cUL #define GNBREGx5d978 0x5d978UL + +#define GNBREGx6a340 0x6a340UL +#define GNBREGx6a344 0x6a344UL +#define GNBREGx6a348 0x6a348UL +#define GNBREGx6a34c 0x6a34cUL +#define GNBREGx6a350 0x6a350UL +#define GNBREGx6a354 0x6a354UL +#define GNBREGx6a358 0x6a358UL diff --git a/xUSL/Nbio/Phx/includePHX/PHX_IOHC.h b/xUSL/Nbio/Phx/includePHX/PHX_IOHC.h index 82cecf6..5f6c445 100644 --- a/xUSL/Nbio/Phx/includePHX/PHX_IOHC.h +++ b/xUSL/Nbio/Phx/includePHX/PHX_IOHC.h @@ -431,3 +431,8 @@ typedef union { * Visibility : 0x2 ************************************************************/ #define IOHCx14300000 0x14300000UL + +#define IOHCx13b0004c 0x13b0004cul +#define IOHCx13b1005c 0x13b1005cul +#define IOHCx13b10060 0x13b10060ul +#define IOHCx13b00084 0x13b00084ul