Currently Vector Mask Register is defined as "VM": RegisterFile("VM", 1, 1, 66)
We have to check if we can alter the logic to define it as "VM": RegisterFile("VM", 1, 64, 1)
That is make Vector Mask a 64 1-bit element Vector Register, from the current configuration as a 1 66-bit element Register.
Code File
Currently Vector Mask Register is defined as
"VM": RegisterFile("VM", 1, 1, 66)We have to check if we can alter the logic to define it as
"VM": RegisterFile("VM", 1, 64, 1)That is make Vector Mask a 64 1-bit element Vector Register, from the current configuration as a 1 66-bit element Register.
Code File