From 4a06590a9414e3ed42f9943e54dff654d86de8af Mon Sep 17 00:00:00 2001
From: AvangardAA <artemnzr@gmail.com>
Date: Mon, 13 Oct 2025 17:51:59 +0000
Subject: [PATCH] Add working lab5 (variant 2)

---
 lab5/task2/task2.sv    | 49 ++++++++++++++++++++++++++++++++++
 lab5/task2/task2_tb.sv | 60 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 109 insertions(+)
 create mode 100644 lab5/task2/task2.sv
 create mode 100644 lab5/task2/task2_tb.sv

diff --git a/lab5/task2/task2.sv b/lab5/task2/task2.sv
new file mode 100644
index 0000000..0f04a95
--- /dev/null
+++ b/lab5/task2/task2.sv
@@ -0,0 +1,49 @@
+module task2(
+	input logic clk, reset, ready, add_sub,
+	input logic [3:0] a, b,
+	output logic [3:0] out_res,
+	output logic out_valid
+	);
+	
+	typedef enum logic [1:0] {INIT, RDY, ADD, SUB} st_type;
+	
+	st_type state, nextstate;
+	
+	always_ff @(posedge clk or posedge reset)
+		if (reset) state <= INIT;
+		else state <= nextstate;
+		
+	always_comb begin
+		case (state)
+			INIT: nextstate = (ready ? RDY : INIT);
+			RDY: nextstate = (add_sub ? ADD : SUB);
+			ADD: nextstate = INIT;
+			SUB: nextstate = INIT;
+			default: nextstate = INIT;
+		endcase
+	end
+		
+	always_ff @(posedge clk or posedge reset) begin
+		if (reset) begin
+			out_res <= 4'b0000;
+			out_valid <= 1'b0;
+		end
+		else begin
+			case (state)
+				ADD: begin
+					out_res <= a + b;
+					out_valid <= 1'b1;
+				end
+				SUB: begin
+					out_res <= a - b;
+					out_valid <= 1'b1;
+				end
+				default: begin
+					out_res <= 4'b0000;
+					out_valid <= 1'b0;
+				end
+			endcase
+		end
+	end
+	
+endmodule
\ No newline at end of file
diff --git a/lab5/task2/task2_tb.sv b/lab5/task2/task2_tb.sv
new file mode 100644
index 0000000..56bc1dc
--- /dev/null
+++ b/lab5/task2/task2_tb.sv
@@ -0,0 +1,60 @@
+`timescale 1ns / 1ps
+
+module task2_tb;
+    logic clk, reset, ready, add_sub;
+    logic [3:0] a, b;
+    logic [3:0] out_res;
+    logic out_valid;
+
+    task2 DUT (
+        .clk(clk),
+        .reset(reset),
+        .ready(ready),
+        .add_sub(add_sub),
+        .a(a),
+        .b(b),
+        .out_res(out_res),
+        .out_valid(out_valid)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    initial begin
+        reset = 1;
+        ready = 0;
+        add_sub = 0;
+        a = 0;
+        b = 0;
+
+        #20;
+        reset = 0;
+
+        @(negedge clk);
+        a = 4'd5;
+        b = 4'd3;
+        add_sub = 1;
+        ready = 1;
+
+        @(negedge clk);
+        ready = 0;
+
+        @(negedge clk);
+        @(negedge clk);
+
+        @(negedge clk);
+        a = 4'd10;
+        b = 4'd6;
+        add_sub = 0;
+        ready = 1;
+
+        @(negedge clk);
+        ready = 0;
+
+        @(negedge clk);
+        @(negedge clk);
+
+        $stop;
+    end
+
+endmodule