From af7888dfc09989d2cc5d58f78568703f20b15667 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 01:27:28 -0700 Subject: [PATCH 01/14] Delete Multimeter.ref.net --- examples/Multimeter/Multimeter.ref.net | 1616 ------------------------ 1 file changed, 1616 deletions(-) delete mode 100644 examples/Multimeter/Multimeter.ref.net diff --git a/examples/Multimeter/Multimeter.ref.net b/examples/Multimeter/Multimeter.ref.net deleted file mode 100644 index bdd1b55b2..000000000 --- a/examples/Multimeter/Multimeter.ref.net +++ /dev/null @@ -1,1616 +0,0 @@ -(export (version D) -(components -(comp (ref "H1") - (value "") - (footprint "edg:JlcToolingHole_1.152mm") - (property (name "Sheetname") (value "jlc_th")) - (property (name "Sheetfile") (value "edg.BoardTop.JlcToolingHoles")) - (property (name "edg_path") (value "jlc_th.th1")) - (property (name "edg_short_path") (value "jlc_th.th1")) - (property (name "edg_refdes") (value "H1")) - (property (name "edg_part") (value "")) - (sheetpath (names "/jlc_th/") (tstamps "/08970275/")) - (tstamps "0260010e")) -(comp (ref "H2") - (value "") - (footprint "edg:JlcToolingHole_1.152mm") - (property (name "Sheetname") (value "jlc_th")) - (property (name "Sheetfile") (value "edg.BoardTop.JlcToolingHoles")) - (property (name "edg_path") (value "jlc_th.th2")) - (property (name "edg_short_path") (value "jlc_th.th2")) - (property (name "edg_refdes") (value "H2")) - (property (name "edg_part") (value "")) - (sheetpath (names "/jlc_th/") (tstamps "/08970275/")) - (tstamps "0261010f")) -(comp (ref "H3") - (value "") - (footprint "edg:JlcToolingHole_1.152mm") - (property (name "Sheetname") (value "jlc_th")) - (property (name "Sheetfile") (value "edg.BoardTop.JlcToolingHoles")) - (property (name "edg_path") (value "jlc_th.th3")) - (property (name "edg_short_path") (value "jlc_th.th3")) - (property (name "edg_refdes") (value "H3")) - (property (name "edg_part") (value "")) - (sheetpath (names "/jlc_th/") (tstamps "/08970275/")) - (tstamps "02620110")) -(comp (ref "U1") - (value "2460") - (footprint "Battery:BatteryHolder_Keystone_2460_1xAA") - (property (name "Sheetname") (value "")) - (property (name "Sheetfile") (value "")) - (property (name "edg_path") (value "bat")) - (property (name "edg_short_path") (value "bat")) - (property (name "edg_refdes") (value "U1")) - (property (name "edg_part") (value "2460 (Keystone)")) - (sheetpath (names "/") (tstamps "/")) - (tstamps "025f0138")) -(comp (ref "J1") - (value "COM-15111") - (footprint "Connector_USB:USB_C_Receptacle_XKB_U262-16XN-4BVC11") - (property (name "Sheetname") (value "data_usb")) - (property (name "Sheetfile") (value "edg.parts.UsbPorts.UsbCReceptacle")) - (property (name "edg_path") (value "data_usb.conn")) - (property (name "edg_short_path") (value "data_usb.conn")) - (property (name "edg_refdes") (value "J1")) - (property (name "edg_part") (value "COM-15111 (Sparkfun)")) - (sheetpath (names "/data_usb/") (tstamps "/0e8f0344/")) - (tstamps "042701af")) -(comp (ref "R1") - (value "±1% 1/10W Thick Film Resistors 75V ±100ppm/℃ -55℃~+155℃ 5.1kΩ 0603 Chip Resistor - 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(node (ref D7) (pin 1))) -(net (code 32) (name "meas_chain_0") - (node (ref U13) (pin 3)) - (node (ref R19) (pin 2)) - (node (ref R20) (pin 1)) - (node (ref R21) (pin 1)) - (node (ref R22) (pin 1))) -(net (code 33) (name "meas_chain_1") - (node (ref U14) (pin 5)) - (node (ref U13) (pin 4)) - (node (ref TP5) (pin 1)) - (node (ref U13) (pin 1))) -(net (code 34) (name "adc.spi.sck") - (node (ref U14) (pin 14)) - (node (ref U5) (pin 37))) -(net (code 35) (name "adc.spi.mosi") - (node (ref U14) (pin 15)) - (node (ref U5) (pin 26))) -(net (code 36) (name "adc.spi.miso") - (node (ref U14) (pin 16)) - (node (ref U5) (pin 24))) -(net (code 37) (name "mcu.gpio.measure_select_0_0") - (node (ref U5) (pin 42)) - (node (ref U10) (pin 6)) - (node (ref U11) (pin 6))) -(net (code 38) (name "mcu.gpio.measure_select_1_0") - (node (ref U5) (pin 43)) - (node (ref U12) (pin 6))) -(net (code 39) (name "adc.cs") - (node (ref U5) (pin 39)) - (node (ref U14) (pin 13))) -(net (code 40) (name "driver_dac.input") - (node (ref U5) (pin 45)) - (node (ref R29) (pin 1))) -(net (code 41) (name "driver_dac.output") - (node (ref U15) (pin 3)) - (node (ref R29) (pin 2)) - (node (ref C31) (pin 1))) -(net (code 42) (name "mcu.gpio.driver_select_0_0") - (node (ref U5) (pin 46)) - (node (ref U16) (pin 6)) - (node (ref U17) (pin 6))) -(net (code 43) (name "mcu.gpio.driver_select_1_0") - (node (ref U5) (pin 44)) - (node (ref U18) (pin 6))) -(net (code 44) (name "driver.enable") - (node (ref U5) (pin 48)) - (node (ref U19) (pin 6))) -(net (code 45) (name "data_usb.conn.cc.cc1") - (node (ref J1) (pin A5)) - (node (ref R1) (pin 2))) -(net (code 46) (name "data_usb.conn.cc.cc2") - (node (ref J1) (pin B5)) - (node (ref R2) (pin 2))) -(net (code 47) (name "gate.pwr_gate.btn_in") - (node (ref D2) (pin 1)) - (node (ref D1) (pin 1)) - (node (ref SW1) (pin 1))) -(net (code 48) (name "gate.pwr_gate.pull_res.b") - (node (ref R3) (pin 2)) - (node (ref D1) (pin 2)) - (node (ref Q1) (pin 1)) - (node (ref Q2) (pin 3))) -(net (code 49) (name "reg_5v.power_path.switch") - (node (ref U2) (pin 5)) - (node (ref L1) (pin 2))) -(net (code 50) (name "reg_5v.ic.ce") - (node (ref U2) (pin 1)) - (node (ref R5) (pin 2))) -(net (code 51) (name "mcu.swd_node.swdio") - (node (ref U5) (pin 51)) - (node (ref J2) (pin 10))) -(net (code 52) (name "mcu.swd_node.swclk") - (node (ref U5) (pin 53)) - (node (ref J2) (pin 9))) -(net (code 53) (name "mcu.reset_node") - (node (ref U5) (pin 40)) - (node (ref J2) (pin 6))) -(net (code 54) (name "mcu.usb_chain_0.d_P") - (node (ref U5) (pin 35)) - (node (ref R6) (pin 1))) -(net (code 55) (name "mcu.usb_chain_0.d_N") - (node (ref U5) (pin 34)) - (node (ref R7) (pin 1))) -(net (code 56) (name "mcu.swd.swo") - (node (ref U5) (pin 47)) - (node (ref J2) (pin 8))) -(net (code 57) (name "mcu.swd.tdi") - (node (ref J2) (pin 7))) -(net (code 58) (name "rgb.red_res.a") - (node (ref R10) (pin 1)) - (node (ref D6) (pin 3))) -(net (code 59) (name "rgb.green_res.a") - (node (ref R11) (pin 1)) - (node (ref D6) (pin 4))) -(net (code 60) (name "rgb.blue_res.a") - (node (ref R12) (pin 1)) - (node (ref D6) (pin 1))) -(net (code 61) (name "lcd.led_res.b") - (node (ref R13) (pin 2)) - (node (ref J3) (pin 1))) -(net (code 62) (name "spk_drv.inp_cap.pos") - (node (ref C13) (pin 1)) - (node (ref R15) (pin 1))) -(net (code 63) (name "spk_drv.inp_res.b") - (node (ref R15) (pin 2)) - (node (ref U7) (pin 4))) -(net (code 64) (name "spk_drv.inn_cap.pos") - (node (ref C14) (pin 1)) - (node (ref R16) (pin 1))) -(net (code 65) (name "spk_drv.inn_res.b") - (node (ref R16) (pin 2)) - (node (ref U7) (pin 3))) -(net (code 66) (name "measure.range.res[0].b") - (node (ref R20) (pin 2)) - (node (ref U10) (pin 3))) -(net (code 67) (name "measure.range.res[1].b") - (node (ref R21) (pin 2)) - (node (ref U10) (pin 1))) -(net (code 68) (name "measure.range.res[2].b") - (node (ref R22) (pin 2)) - (node (ref U11) (pin 3))) -(net (code 69) (name "measure.range.dummy.io") - (node (ref U11) (pin 1))) -(net (code 70) (name "measure.range.switch.sw[0_0].com") - (node (ref U12) (pin 3)) - (node (ref U10) (pin 4))) -(net (code 71) (name "measure.range.switch.sw[0_1].com") - (node (ref U12) (pin 1)) - (node (ref U11) (pin 4))) -(net (code 72) (name "adc.mclkin") - (node (ref U14) (pin 18))) -(net (code 73) (name "adc.vins.2") - (node (ref U14) (pin 7))) -(net (code 74) (name "adc.vins.3") - (node (ref U14) (pin 8))) -(net (code 75) (name "adc.vins.4") - (node (ref U14) (pin 9))) -(net (code 76) (name "adc.vins.5") - (node (ref U14) (pin 10))) -(net (code 77) (name "adc.vins.6") - (node (ref U14) (pin 11))) -(net (code 78) (name "adc.vins.7") - (node (ref U14) (pin 12))) -(net (code 79) (name "adc.ic.avdd") - (node (ref U14) (pin 1)) - (node (ref R23) (pin 2)) - (node (ref C21) (pin 1)) - (node (ref C22) (pin 1))) -(net (code 80) (name "adc.ic.dvdd") - (node (ref U14) (pin 20)) - (node (ref R24) (pin 2)) - (node (ref C23) (pin 1)) - (node (ref C24) (pin 1))) -(net (code 81) (name "adc.ic.vrefp") - (node (ref U14) (pin 4)) - (node (ref C25) (pin 1))) -(net (code 82) (name "driver.fet.source") - (node (ref Q3) (pin 2)) - (node (ref U15) (pin 4)) - (node (ref U19) (pin 3)) - (node (ref U18) (pin 4))) -(net (code 83) (name "driver.amp.out") - (node (ref U15) (pin 1)) - (node (ref U19) (pin 1))) -(net (code 84) (name "driver.fet.gate") - (node (ref Q3) (pin 1)) - (node (ref U19) (pin 4))) -(net (code 85) (name "driver.fet.drain") - (node (ref Q3) (pin 3)) - (node (ref D7) (pin 2))) -(net (code 86) (name "driver.range.res[0].b") - (node (ref R25) (pin 2)) - (node (ref U16) (pin 3))) -(net (code 87) (name "driver.range.res[1].b") - (node (ref R26) (pin 2)) - (node (ref U16) (pin 1))) -(net (code 88) (name "driver.range.res[2].b") - (node (ref R27) (pin 2)) - (node (ref U17) (pin 3))) -(net (code 89) (name "driver.range.res[3].b") - (node (ref R28) (pin 2)) - (node (ref U17) (pin 1))) -(net (code 90) (name "driver.range.switch.sw[0_0].com") - (node (ref U18) (pin 3)) - (node (ref U16) (pin 4))) -(net (code 91) (name "driver.range.switch.sw[0_1].com") - (node (ref U18) (pin 1)) - (node (ref U17) (pin 4)))) -) \ No newline at end of file From 4f8f3023899f859f49649282ef793d87ec8fdca5 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 11:32:28 -0700 Subject: [PATCH 02/14] wip --- edg/electronics_model/SubboardBlock.py | 45 ++++++++++++++++++++------ edg/electronics_model/__init__.py | 2 +- 2 files changed, 37 insertions(+), 10 deletions(-) diff --git a/edg/electronics_model/SubboardBlock.py b/edg/electronics_model/SubboardBlock.py index 95458f9ab..de29dc2df 100644 --- a/edg/electronics_model/SubboardBlock.py +++ b/edg/electronics_model/SubboardBlock.py @@ -7,20 +7,14 @@ from .. import edgir -class SubboardBlock(Block): - """A block that is a sub-board, where all its blocks not marked external are part of a different board. - Provides the export_tap construct to tack connectors onto ports without breaking modeling. - - IMPORTANT: pseudo-blocks like bridges and adapters are considered internal blocks and do not affect - netlisting in the exterior board. In general, external blocks should only be connected via export-tap - and not direct connections where they may generate pseudo-blocks that end up in the wrong board.""" +@non_library +class HasSubboardBlockApi(Block): + """Base class that provides the subboard construction API.""" def __init__(self) -> None: super().__init__() self._external_blocks: List[Block] = [] self._export_taps: List[Tuple[BasePort, BasePort]] = [] - - self.fp_subboard = self.Metadata("A") # dummy distinct value self.fp_external_blocks = self.Parameter(ArrayStringExpr()) # names of all external blocks BlockType = TypeVar("BlockType", bound=Block) @@ -70,6 +64,19 @@ def _populate_def_proto_hierarchy(self, pb: edgir.HierarchyBlock, ref_map: Refab constraint_pb.exported.tap = True +class SubboardBlock(HasSubboardBlockApi, Block): + """A block that is a sub-board, where all its blocks not marked external are part of a different board. + Provides the export_tap construct to tack connectors onto ports without breaking modeling. + + IMPORTANT: pseudo-blocks like bridges and adapters are considered internal blocks and do not affect + netlisting in the exterior board. In general, external blocks should only be connected via export-tap + and not direct connections where they may generate pseudo-blocks that end up in the wrong board.""" + + def __init__(self) -> None: + super().__init__() + self.fp_subboard = self.Metadata("A") # dummy distinct value + + class WrapperSubboardBlock(SubboardBlock): """A wrapper block where the internal blocks are skipped for netlisting and used for modeling only. Useful for eg, dev boards that only generate a connector or socket but re-use modeling from the raw subcircuit.""" @@ -77,3 +84,23 @@ class WrapperSubboardBlock(SubboardBlock): def __init__(self) -> None: super().__init__() self.fp_subblocks_ignored = self.Metadata("B") # dummy distinct value + + +class SubboardConnectorPair(HasSubboardBlockApi, Block): + """A block meant for a connector pair, one in the exterior and one in the interior, of a SubboardBlock. + When in a SubboardBlock scope and marked external, this inherits the parent and self board scope of its container, + so inner Blocks marked external are part of the SubboardBlock's parent scope, while internal Blocks + are part of the SubboardBlock's inner scope. + + Inner SubboardConnectorPairs marked external similarly inherit board scopes of its containing + SubboardConnectorPair. + + Recommended convention, similar to SubboardBlock, is to directly export ports from the internal Block + while export-tapping ports from the external Block. + + These should not be instantiated outside a SubboardBlock or SubblockConnectorPair. + """ + + def __init__(self) -> None: + super().__init__() + self.fp_subboard_connector_pair = self.Metadata("C") # dummy distinct value diff --git a/edg/electronics_model/__init__.py b/edg/electronics_model/__init__.py index 22e13774c..cf3438bd4 100644 --- a/edg/electronics_model/__init__.py +++ b/edg/electronics_model/__init__.py @@ -7,7 +7,7 @@ NetBlock, CircuitPort, ) -from .SubboardBlock import SubboardBlock, WrapperSubboardBlock +from .SubboardBlock import SubboardBlock, WrapperSubboardBlock, SubboardConnectorPair from .Units import Farad, uFarad, nFarad, pFarad, MOhm, kOhm, Ohm, mOhm, Henry, uHenry, nHenry from .Units import Volt, mVolt, Watt, Amp, mAmp, uAmp, nAmp, pAmp From 9fd6c37520d061f60c3a958b6fee9a444e4df5a6 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 12:15:06 -0700 Subject: [PATCH 03/14] Create test_netlist_connector_pair.py --- .../test_netlist_connector_pair.py | 205 ++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100644 edg/electronics_model/test_netlist_connector_pair.py diff --git a/edg/electronics_model/test_netlist_connector_pair.py b/edg/electronics_model/test_netlist_connector_pair.py new file mode 100644 index 000000000..122120ccc --- /dev/null +++ b/edg/electronics_model/test_netlist_connector_pair.py @@ -0,0 +1,205 @@ +import unittest + +from typing_extensions import override + +from .NetlistGenerator import NetlistTransform +from .. import FootprintBlock, DesignTop, ScalaCompiler, RefdesRefinementPass, SubboardConnectorPair +from ..core import TransformUtil +from .test_netlist import TestFakeSource, TestFakeSink, NetBlock, Net, NetPin +from . import SubboardBlock, VoltageSink, Passive + + +class SinkExteriorConnector(FootprintBlock): + def __init__(self) -> None: + super().__init__() + + self.pos = self.Port(Passive.empty()) # must remain empty + self.neg = self.Port(Passive.empty()) + + @override + def contents(self) -> None: + super().contents() + + self.footprint( # only this footprint shows up + "J", + "Connector_PinSocket_2.54mm:PinSocket_1x02_P2.54mm_Vertical", + {"1": self.pos, "2": self.neg}, + ) + + +class SinkInternalConnector(FootprintBlock): + def __init__(self) -> None: + super().__init__() + + self.pos = self.Port(Passive.empty()) # must remain empty + self.neg = self.Port(Passive.empty()) + + @override + def contents(self) -> None: + super().contents() + + self.footprint( # only this footprint shows up + "J", + "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical", + {"1": self.pos, "2": self.neg}, + ) + + +class SinkConnectorPair(SubboardConnectorPair): + def __init__(self) -> None: + super().__init__() + + self.internal = self.Block(SinkInternalConnector()) + self.pos = self.Export(self.internal.pos) + self.neg = self.Export(self.internal.neg) + self.external = self.Block(SinkExteriorConnector(), external=True) + self.export_tap(self.pos, self.external.pos) + self.export_tap(self.neg, self.external.neg) + + +class SinkConnectorPairBlock(SubboardBlock): + """Subboard block with a connector pair and internal circuits.""" + + def __init__(self) -> None: + super().__init__() + + self.pos = self.Port(VoltageSink.empty()) + self.neg = self.Port(VoltageSink.empty()) + + @override + def contents(self) -> None: + super().contents() + + # these blocks are part of the sub-board + self.inner1 = self.Block(TestFakeSink()) + self.inner2 = self.Block(TestFakeSink()) + self.vpos = self.connect(self.pos, self.inner1.pos, self.inner2.pos) + self.gnd = self.connect(self.neg, self.inner1.neg, self.inner2.neg) + + # these define the external interface block + self.conn = self.Block(SinkConnectorPair(), external=True) + self.export_tap(self.pos.net, self.conn.pos) + self.export_tap(self.neg.net, self.conn.neg) + + +class TestConnectorPairCircuit(DesignTop): + @override + def contents(self) -> None: + super().contents() + + self.source = self.Block(TestFakeSource()) + self.sink = self.Block(SinkConnectorPairBlock()) + + self.vpos = self.connect(self.source.pos, self.sink.pos) + self.gnd = self.connect(self.source.neg, self.sink.neg) + + +class NetlistConnectorPairTestCase(unittest.TestCase): + def test_subboard_netlist(self) -> None: + compiled = ScalaCompiler.compile(TestConnectorPairCircuit) + compiled.append_values(RefdesRefinementPass().run(compiled)) + board_netlists = NetlistTransform(compiled).run() + + top_net = board_netlists[TransformUtil.Path.empty()] + + self.assertIn( + NetBlock( + "Connector_PinSocket_2.54mm:PinSocket_1x02_P2.54mm_Vertical", + "J1", + "", + "", + ["sink", "conn", "external"], + [ + "edg.electronics_model.test_netlist_connector_pair.SinkConnectorPairBlock", + "edg.electronics_model.test_netlist_connector_pair.SinkConnectorPair", + "edg.electronics_model.test_netlist_connector_pair.SinkExteriorConnector", + ], + ), + top_net.blocks, + ) + self.assertEqual(len(top_net.blocks), 2) # should only generate top-level source and sink + + self.assertIn( + Net( + "vpos", + [NetPin(["source"], "1"), NetPin(["sink", "wrapper"], "1")], # ensure extraneous nets not generated + [ + TransformUtil.Path.empty().append_block("source").append_port("pos", "net"), + TransformUtil.Path.empty().append_block("sink").append_port("pos", "net"), + TransformUtil.Path.empty().append_block("sink", "wrapper").append_port("pos", "net"), + ], + ), + top_net.nets, + ) + self.assertIn( + Net( + "gnd", + [NetPin(["source"], "2"), NetPin(["sink", "wrapper"], "2")], + [ + TransformUtil.Path.empty().append_block("source").append_port("neg", "net"), + TransformUtil.Path.empty().append_block("sink").append_port("neg", "net"), + TransformUtil.Path.empty().append_block("sink", "wrapper").append_port("neg", "net"), + ], + ), + top_net.nets, + ) + self.assertEqual(len(top_net.nets), 2) # ensure empty nets pruned + + inner_net = board_netlists[TransformUtil.Path.empty().append_block("sink")] + self.assertIn( + NetBlock( + "Resistor_SMD:R_0603_1608Metric", + "R1", + "", + "1k", + ["sink", "inner1"], + [ + "edg.electronics_model.test_netlist_subboard.SinkSubboardBlock", + "edg.electronics_model.test_netlist.TestFakeSink", + ], + ), + inner_net.blocks, + ) + self.assertIn( + NetBlock( + "Resistor_SMD:R_0603_1608Metric", + "R2", + "", + "1k", + ["sink", "inner2"], + [ + "edg.electronics_model.test_netlist_subboard.SinkSubboardBlock", + "edg.electronics_model.test_netlist.TestFakeSink", + ], + ), + inner_net.blocks, + ) + self.assertEqual(len(inner_net.blocks), 2) + + self.assertIn( + Net( + "sink.vpos", + [NetPin(["sink", "inner1"], "1"), NetPin(["sink", "inner2"], "1")], + [ + TransformUtil.Path.empty().append_block("sink").append_port("pos", "net"), + TransformUtil.Path.empty().append_block("sink", "wrapper").append_port("pos", "net"), + TransformUtil.Path.empty().append_block("sink", "inner1").append_port("pos", "net"), + TransformUtil.Path.empty().append_block("sink", "inner2").append_port("pos", "net"), + ], + ), + inner_net.nets, + ) + self.assertIn( + Net( + "sink.gnd", + [NetPin(["sink", "inner1"], "2"), NetPin(["sink", "inner2"], "2")], + [ + TransformUtil.Path.empty().append_block("sink").append_port("neg", "net"), + TransformUtil.Path.empty().append_block("sink", "wrapper").append_port("neg", "net"), + TransformUtil.Path.empty().append_block("sink", "inner1").append_port("neg", "net"), + TransformUtil.Path.empty().append_block("sink", "inner2").append_port("neg", "net"), + ], + ), + inner_net.nets, + ) + self.assertEqual(len(inner_net.nets), 2) # ensure empty nets pruned From b924d51e771f495d55824f9a291ed45949a2d577 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 12:30:48 -0700 Subject: [PATCH 04/14] progress but not quite --- edg/electronics_model/BoardScopedTransform.py | 4 +++- edg/electronics_model/test_netlist_connector_pair.py | 9 ++++++--- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/edg/electronics_model/BoardScopedTransform.py b/edg/electronics_model/BoardScopedTransform.py index b82ee69f2..ae7aca4b5 100644 --- a/edg/electronics_model/BoardScopedTransform.py +++ b/edg/electronics_model/BoardScopedTransform.py @@ -39,12 +39,14 @@ def visit_linkarray_scoped( def visit_block(self, context: TransformContext, block: edgir.HierarchyBlock) -> None: parent_scope = self._board_parent_scopes[context.path] - if "fp_subboard" in block.meta.members.node: + if "fp_subboard" in block.meta.members.node or "fp_subboard_connector_pair" in block.meta.members.node: fp_external_blocks = self._design.get_value(context.path.to_tuple() + ("fp_external_blocks",)) assert isinstance(fp_external_blocks, list) external_blocks: Optional[List[str]] = cast(List[str], fp_external_blocks) if "fp_subblocks_ignored" in block.meta.members.node: internal_scope = None + elif "fp_subboard_connector_pair" in block.meta.members.node: + internal_scope = self._board_scopes[TransformUtil.Path.empty().append_block(*context.path.blocks[:-1])] else: internal_scope = context.path else: diff --git a/edg/electronics_model/test_netlist_connector_pair.py b/edg/electronics_model/test_netlist_connector_pair.py index 122120ccc..ebd73fe19 100644 --- a/edg/electronics_model/test_netlist_connector_pair.py +++ b/edg/electronics_model/test_netlist_connector_pair.py @@ -105,7 +105,7 @@ def test_subboard_netlist(self) -> None: self.assertIn( NetBlock( "Connector_PinSocket_2.54mm:PinSocket_1x02_P2.54mm_Vertical", - "J1", + "J2", "", "", ["sink", "conn", "external"], @@ -122,11 +122,14 @@ def test_subboard_netlist(self) -> None: self.assertIn( Net( "vpos", - [NetPin(["source"], "1"), NetPin(["sink", "wrapper"], "1")], # ensure extraneous nets not generated + [ + NetPin(["source"], "1"), + NetPin(["sink", "conn", "external"], "1"), + ], # ensure extraneous nets not generated [ TransformUtil.Path.empty().append_block("source").append_port("pos", "net"), TransformUtil.Path.empty().append_block("sink").append_port("pos", "net"), - TransformUtil.Path.empty().append_block("sink", "wrapper").append_port("pos", "net"), + TransformUtil.Path.empty().append_block("sink", "conn", "external").append_port("pos", "net"), ], ), top_net.nets, From 74cde3003bb8fc8f1c2af6739b1b869c22d1cb20 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 15:21:59 -0700 Subject: [PATCH 05/14] moles being whacked --- edg/electronics_model/NetlistGenerator.py | 5 ++- .../test_netlist_connector_pair.py | 33 +++++++++++++++---- 2 files changed, 28 insertions(+), 10 deletions(-) diff --git a/edg/electronics_model/NetlistGenerator.py b/edg/electronics_model/NetlistGenerator.py index 9856358fd..5bf32c71b 100644 --- a/edg/electronics_model/NetlistGenerator.py +++ b/edg/electronics_model/NetlistGenerator.py @@ -98,10 +98,9 @@ def process_blocklike( else: scope_obj = None - if isinstance(block, edgir.HierarchyBlock) and "fp_subboard" in block.meta.members.node: - # only valid for sub-board blocks, where some things happen in the parent scope + if isinstance(block, edgir.HierarchyBlock): parent_scope = self._board_parent_scopes[path] - if parent_scope is not None: + if parent_scope is not None and parent_scope is not scope_obj: parent_scope_obj: Optional[BoardScope] = self.scopes[parent_scope] else: parent_scope_obj = None diff --git a/edg/electronics_model/test_netlist_connector_pair.py b/edg/electronics_model/test_netlist_connector_pair.py index ebd73fe19..ce7e76081 100644 --- a/edg/electronics_model/test_netlist_connector_pair.py +++ b/edg/electronics_model/test_netlist_connector_pair.py @@ -125,11 +125,13 @@ def test_subboard_netlist(self) -> None: [ NetPin(["source"], "1"), NetPin(["sink", "conn", "external"], "1"), - ], # ensure extraneous nets not generated + ], [ TransformUtil.Path.empty().append_block("source").append_port("pos", "net"), TransformUtil.Path.empty().append_block("sink").append_port("pos", "net"), - TransformUtil.Path.empty().append_block("sink", "conn", "external").append_port("pos", "net"), + TransformUtil.Path.empty().append_block("sink", "conn").append_port("pos"), + TransformUtil.Path.empty().append_block("sink", "conn", "internal").append_port("pos"), + TransformUtil.Path.empty().append_block("sink", "conn", "external").append_port("pos"), ], ), top_net.nets, @@ -137,11 +139,13 @@ def test_subboard_netlist(self) -> None: self.assertIn( Net( "gnd", - [NetPin(["source"], "2"), NetPin(["sink", "wrapper"], "2")], + [NetPin(["source"], "2"), NetPin(["sink", "conn", "external"], "2")], [ TransformUtil.Path.empty().append_block("source").append_port("neg", "net"), TransformUtil.Path.empty().append_block("sink").append_port("neg", "net"), - TransformUtil.Path.empty().append_block("sink", "wrapper").append_port("neg", "net"), + TransformUtil.Path.empty().append_block("sink", "conn").append_port("neg"), + TransformUtil.Path.empty().append_block("sink", "conn", "internal").append_port("neg"), + TransformUtil.Path.empty().append_block("sink", "conn", "external").append_port("neg"), ], ), top_net.nets, @@ -149,6 +153,21 @@ def test_subboard_netlist(self) -> None: self.assertEqual(len(top_net.nets), 2) # ensure empty nets pruned inner_net = board_netlists[TransformUtil.Path.empty().append_block("sink")] + self.assertIn( + NetBlock( + "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical", + "J1", + "", + "", + ["sink", "conn", "internal"], + [ + "edg.electronics_model.test_netlist_connector_pair.SinkConnectorPairBlock", + "edg.electronics_model.test_netlist_connector_pair.SinkConnectorPair", + "edg.electronics_model.test_netlist_connector_pair.SinkInternalConnector", + ], + ), + inner_net.blocks, + ) self.assertIn( NetBlock( "Resistor_SMD:R_0603_1608Metric", @@ -157,7 +176,7 @@ def test_subboard_netlist(self) -> None: "1k", ["sink", "inner1"], [ - "edg.electronics_model.test_netlist_subboard.SinkSubboardBlock", + "edg.electronics_model.test_netlist_connector_pair.SinkConnectorPairBlock", "edg.electronics_model.test_netlist.TestFakeSink", ], ), @@ -171,13 +190,13 @@ def test_subboard_netlist(self) -> None: "1k", ["sink", "inner2"], [ - "edg.electronics_model.test_netlist_subboard.SinkSubboardBlock", + "edg.electronics_model.test_netlist_connector_pair.SinkConnectorPairBlock", "edg.electronics_model.test_netlist.TestFakeSink", ], ), inner_net.blocks, ) - self.assertEqual(len(inner_net.blocks), 2) + self.assertEqual(len(inner_net.blocks), 3) self.assertIn( Net( From a8bf98e2c795ca90de7dab0d733a89824fe047e9 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 15:35:20 -0700 Subject: [PATCH 06/14] Update test_netlist_connector_pair.py --- .../test_netlist_connector_pair.py | 20 +++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/edg/electronics_model/test_netlist_connector_pair.py b/edg/electronics_model/test_netlist_connector_pair.py index ce7e76081..0c723dc00 100644 --- a/edg/electronics_model/test_netlist_connector_pair.py +++ b/edg/electronics_model/test_netlist_connector_pair.py @@ -201,10 +201,16 @@ def test_subboard_netlist(self) -> None: self.assertIn( Net( "sink.vpos", - [NetPin(["sink", "inner1"], "1"), NetPin(["sink", "inner2"], "1")], + [ + NetPin(["sink", "inner1"], "1"), + NetPin(["sink", "inner2"], "1"), + NetPin(["sink", "conn", "internal"], "1"), + ], [ TransformUtil.Path.empty().append_block("sink").append_port("pos", "net"), - TransformUtil.Path.empty().append_block("sink", "wrapper").append_port("pos", "net"), + TransformUtil.Path.empty().append_block("sink", "conn").append_port("pos"), + TransformUtil.Path.empty().append_block("sink", "conn", "internal").append_port("pos"), + TransformUtil.Path.empty().append_block("sink", "conn", "external").append_port("pos"), TransformUtil.Path.empty().append_block("sink", "inner1").append_port("pos", "net"), TransformUtil.Path.empty().append_block("sink", "inner2").append_port("pos", "net"), ], @@ -214,10 +220,16 @@ def test_subboard_netlist(self) -> None: self.assertIn( Net( "sink.gnd", - [NetPin(["sink", "inner1"], "2"), NetPin(["sink", "inner2"], "2")], + [ + NetPin(["sink", "inner1"], "2"), + NetPin(["sink", "inner2"], "2"), + NetPin(["sink", "conn", "internal"], "2"), + ], [ TransformUtil.Path.empty().append_block("sink").append_port("neg", "net"), - TransformUtil.Path.empty().append_block("sink", "wrapper").append_port("neg", "net"), + TransformUtil.Path.empty().append_block("sink", "conn").append_port("neg"), + TransformUtil.Path.empty().append_block("sink", "conn", "internal").append_port("neg"), + TransformUtil.Path.empty().append_block("sink", "conn", "external").append_port("neg"), TransformUtil.Path.empty().append_block("sink", "inner1").append_port("neg", "net"), TransformUtil.Path.empty().append_block("sink", "inner2").append_port("neg", "net"), ], From 65319387ad06891123f6793db736b3b523c052bd Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 15:42:08 -0700 Subject: [PATCH 07/14] rename + 2.54 pins --- .../test_netlist_connector_pair.py | 44 +++++++++---------- edg/parts/PassiveConnector_Header.py | 11 +++++ 2 files changed, 33 insertions(+), 22 deletions(-) diff --git a/edg/electronics_model/test_netlist_connector_pair.py b/edg/electronics_model/test_netlist_connector_pair.py index 0c723dc00..e9abb3a51 100644 --- a/edg/electronics_model/test_netlist_connector_pair.py +++ b/edg/electronics_model/test_netlist_connector_pair.py @@ -49,12 +49,12 @@ class SinkConnectorPair(SubboardConnectorPair): def __init__(self) -> None: super().__init__() - self.internal = self.Block(SinkInternalConnector()) - self.pos = self.Export(self.internal.pos) - self.neg = self.Export(self.internal.neg) - self.external = self.Block(SinkExteriorConnector(), external=True) - self.export_tap(self.pos, self.external.pos) - self.export_tap(self.neg, self.external.neg) + self.ext = self.Block(SinkExteriorConnector(), external=True) + self.int = self.Block(SinkInternalConnector()) + self.pos = self.Export(self.int.pos) + self.neg = self.Export(self.int.neg) + self.export_tap(self.pos, self.ext.pos) + self.export_tap(self.neg, self.ext.neg) class SinkConnectorPairBlock(SubboardBlock): @@ -105,10 +105,10 @@ def test_subboard_netlist(self) -> None: self.assertIn( NetBlock( "Connector_PinSocket_2.54mm:PinSocket_1x02_P2.54mm_Vertical", - "J2", + "J1", "", "", - ["sink", "conn", "external"], + ["sink", "conn", "ext"], [ "edg.electronics_model.test_netlist_connector_pair.SinkConnectorPairBlock", "edg.electronics_model.test_netlist_connector_pair.SinkConnectorPair", @@ -124,14 +124,14 @@ def test_subboard_netlist(self) -> None: "vpos", [ NetPin(["source"], "1"), - NetPin(["sink", "conn", "external"], "1"), + NetPin(["sink", "conn", "ext"], "1"), ], [ TransformUtil.Path.empty().append_block("source").append_port("pos", "net"), TransformUtil.Path.empty().append_block("sink").append_port("pos", "net"), TransformUtil.Path.empty().append_block("sink", "conn").append_port("pos"), - TransformUtil.Path.empty().append_block("sink", "conn", "internal").append_port("pos"), - TransformUtil.Path.empty().append_block("sink", "conn", "external").append_port("pos"), + TransformUtil.Path.empty().append_block("sink", "conn", "int").append_port("pos"), + TransformUtil.Path.empty().append_block("sink", "conn", "ext").append_port("pos"), ], ), top_net.nets, @@ -139,13 +139,13 @@ def test_subboard_netlist(self) -> None: self.assertIn( Net( "gnd", - [NetPin(["source"], "2"), NetPin(["sink", "conn", "external"], "2")], + [NetPin(["source"], "2"), NetPin(["sink", "conn", "ext"], "2")], [ TransformUtil.Path.empty().append_block("source").append_port("neg", "net"), TransformUtil.Path.empty().append_block("sink").append_port("neg", "net"), TransformUtil.Path.empty().append_block("sink", "conn").append_port("neg"), - TransformUtil.Path.empty().append_block("sink", "conn", "internal").append_port("neg"), - TransformUtil.Path.empty().append_block("sink", "conn", "external").append_port("neg"), + TransformUtil.Path.empty().append_block("sink", "conn", "int").append_port("neg"), + TransformUtil.Path.empty().append_block("sink", "conn", "ext").append_port("neg"), ], ), top_net.nets, @@ -156,10 +156,10 @@ def test_subboard_netlist(self) -> None: self.assertIn( NetBlock( "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical", - "J1", + "J2", "", "", - ["sink", "conn", "internal"], + ["sink", "conn", "int"], [ "edg.electronics_model.test_netlist_connector_pair.SinkConnectorPairBlock", "edg.electronics_model.test_netlist_connector_pair.SinkConnectorPair", @@ -204,13 +204,13 @@ def test_subboard_netlist(self) -> None: [ NetPin(["sink", "inner1"], "1"), NetPin(["sink", "inner2"], "1"), - NetPin(["sink", "conn", "internal"], "1"), + NetPin(["sink", "conn", "int"], "1"), ], [ TransformUtil.Path.empty().append_block("sink").append_port("pos", "net"), TransformUtil.Path.empty().append_block("sink", "conn").append_port("pos"), - TransformUtil.Path.empty().append_block("sink", "conn", "internal").append_port("pos"), - TransformUtil.Path.empty().append_block("sink", "conn", "external").append_port("pos"), + TransformUtil.Path.empty().append_block("sink", "conn", "int").append_port("pos"), + TransformUtil.Path.empty().append_block("sink", "conn", "ext").append_port("pos"), TransformUtil.Path.empty().append_block("sink", "inner1").append_port("pos", "net"), TransformUtil.Path.empty().append_block("sink", "inner2").append_port("pos", "net"), ], @@ -223,13 +223,13 @@ def test_subboard_netlist(self) -> None: [ NetPin(["sink", "inner1"], "2"), NetPin(["sink", "inner2"], "2"), - NetPin(["sink", "conn", "internal"], "2"), + NetPin(["sink", "conn", "int"], "2"), ], [ TransformUtil.Path.empty().append_block("sink").append_port("neg", "net"), TransformUtil.Path.empty().append_block("sink", "conn").append_port("neg"), - TransformUtil.Path.empty().append_block("sink", "conn", "internal").append_port("neg"), - TransformUtil.Path.empty().append_block("sink", "conn", "external").append_port("neg"), + TransformUtil.Path.empty().append_block("sink", "conn", "int").append_port("neg"), + TransformUtil.Path.empty().append_block("sink", "conn", "ext").append_port("neg"), TransformUtil.Path.empty().append_block("sink", "inner1").append_port("neg", "net"), TransformUtil.Path.empty().append_block("sink", "inner2").append_port("neg", "net"), ], diff --git a/edg/parts/PassiveConnector_Header.py b/edg/parts/PassiveConnector_Header.py index 3041425ab..694a5d790 100644 --- a/edg/parts/PassiveConnector_Header.py +++ b/edg/parts/PassiveConnector_Header.py @@ -53,6 +53,17 @@ def part_footprint_mfr_name(self, length: int) -> Tuple[str, str, str]: ) +class PinSocket254Pair(SubboardConnectorPair): + """2.54mm pin socket (external) - header (internal) pair for sub-board connectors.""" + + def __init__(self, length: IntLike = 0) -> None: + super().__init__() + self.ext = self.Block(PinSocket254(length), external=True) + self.int = self.Block(PinHeader254(length)) + self.pins = self.Export(self.int.pins) + self.export_tap(self.pins, self.ext.pins) + + class PinHeader254DualShroudedInline(FootprintPassiveConnector): """Generic 2.54mm dual-row pin header in edge-inline.""" From 1afa1bd3e582c9f62f23738b17fca71f2df03f93 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 16:07:46 -0700 Subject: [PATCH 08/14] FPC pair --- edg/electronics_model/NetlistGenerator.py | 2 +- edg/electronics_model/SubboardBlock.py | 5 +- edg/parts/PassiveConnector_Fpc.py | 66 +++++++++++++++++++++++ edg/parts/PassiveConnector_Header.py | 3 +- edg/parts/__init__.py | 9 +++- 5 files changed, 80 insertions(+), 5 deletions(-) diff --git a/edg/electronics_model/NetlistGenerator.py b/edg/electronics_model/NetlistGenerator.py index 5bf32c71b..67d58971c 100644 --- a/edg/electronics_model/NetlistGenerator.py +++ b/edg/electronics_model/NetlistGenerator.py @@ -100,7 +100,7 @@ def process_blocklike( if isinstance(block, edgir.HierarchyBlock): parent_scope = self._board_parent_scopes[path] - if parent_scope is not None and parent_scope is not scope_obj: + if parent_scope is not None and parent_scope != scope: parent_scope_obj: Optional[BoardScope] = self.scopes[parent_scope] else: parent_scope_obj = None diff --git a/edg/electronics_model/SubboardBlock.py b/edg/electronics_model/SubboardBlock.py index de29dc2df..21bba3e96 100644 --- a/edg/electronics_model/SubboardBlock.py +++ b/edg/electronics_model/SubboardBlock.py @@ -96,9 +96,10 @@ class SubboardConnectorPair(HasSubboardBlockApi, Block): SubboardConnectorPair. Recommended convention, similar to SubboardBlock, is to directly export ports from the internal Block - while export-tapping ports from the external Block. + while export-tapping ports from the external Block. The external Block should be generated first + for refdes ordering. This block's pin numbering should correspond to the external Block. - These should not be instantiated outside a SubboardBlock or SubblockConnectorPair. + These should not be instantiated outside a SubboardBlock or SubblockConnectorPair. Bad things can happen. """ def __init__(self) -> None: diff --git a/edg/parts/PassiveConnector_Fpc.py b/edg/parts/PassiveConnector_Fpc.py index dd6ccae32..50b3748e1 100644 --- a/edg/parts/PassiveConnector_Fpc.py +++ b/edg/parts/PassiveConnector_Fpc.py @@ -23,6 +23,71 @@ class Fpc050Bottom(Fpc050): IMPORTANT: the pin numbering scheme differs for top- and bottom-contact connectors.""" +class Fpc050Pair(SubboardConnectorPair, GeneratorBlock): + """Pair of FPC connectors for sub-board connectors, parameterized by length (pins), cable geometry / type, + and connector contact side. + + Parameters: + cable = "same" | "opposite: whether the FPC cable has contacts on the same side (Type A, mirror pin numbering) + or opposite sides (Type B, same pin numbering both sides) + ext_contact, int_contact = "top" | "bottom": the contact side for the external and internal connectors, respectively. + """ + + def __init__( + self, + length: IntLike = 0, + cable: StringLike = "same", + ext_contact: StringLike = "bot", + int_contact: StringLike = "bot", + ) -> None: + super().__init__() + self.length = self.ArgParameter(length) + self.cable = self.ArgParameter(cable) + self.ext_contact = self.ArgParameter(ext_contact) + self.int_contact = self.ArgParameter(int_contact) + self.pins = self.Port(Vector(Passive.empty())) + self.generator_param(self.length, self.cable, self.ext_contact, self.int_contact) + + @override + def generate(self) -> None: + super().generate() + ext_contact = self.get(self.ext_contact) + int_contact = self.get(self.int_contact) + + if ext_contact == "top": + self.ext: Fpc050 = self.Block(Fpc050Top(self.length), external=True) + elif ext_contact == "bot": + self.ext = self.Block(Fpc050Bottom(self.length), external=True) + else: + raise ValueError(f"invalid ext_contact") + + if int_contact == "top": + self.int: Fpc050 = self.Block(Fpc050Top(self.length)) + elif int_contact == "bot": + self.int = self.Block(Fpc050Bottom(self.length)) + else: + raise ValueError(f"invalid int_contact") + + length = self.get(self.length) + assert length > 0, "explicit length required" + + if self.get(self.cable) == "same": # assuming same side contact side connectors + mirror = True + else: + mirror = False + if ext_contact != int_contact: # account for different contact side + mirror = not mirror + + self.pins.defined() + for pin_num in self.get(self.pins.requested()): + pin = self.pins.append_elt(Passive.empty(), pin_num) + self.export_tap(pin, self.ext.pins.request(pin_num)) + if mirror: + self.connect(pin, self.int.pins.request(str(length - (int(pin_num) - 1)))) + else: + self.connect(pin, self.int.pins.request(pin_num)) + + class Fpc050BottomFlip(Fpc050Bottom, GeneratorBlock): """Flipped FPC connector - bottom entry connector is top entry on the opposite board side. Reverses the pin ordering to reflect the mirroring.""" @@ -37,6 +102,7 @@ def generate(self) -> None: super().generate() self.conn = self.Block(Fpc050Top(self.length)) length = self.get(self.length) + assert length > 0, "explicit length required" for pin in self.get(self.pins.requested()): self.connect( self.pins.append_elt(Passive.empty(), pin), self.conn.pins.request(str(length - (int(pin) - 1))) diff --git a/edg/parts/PassiveConnector_Header.py b/edg/parts/PassiveConnector_Header.py index 694a5d790..4a494f144 100644 --- a/edg/parts/PassiveConnector_Header.py +++ b/edg/parts/PassiveConnector_Header.py @@ -54,7 +54,8 @@ def part_footprint_mfr_name(self, length: int) -> Tuple[str, str, str]: class PinSocket254Pair(SubboardConnectorPair): - """2.54mm pin socket (external) - header (internal) pair for sub-board connectors.""" + """2.54mm pin socket (external) - header (internal) pair for sub-board connectors, + matching same pin-number to pin-number.""" def __init__(self, length: IntLike = 0) -> None: super().__init__() diff --git a/edg/parts/__init__.py b/edg/parts/__init__.py index d0f1c9946..fe569d746 100644 --- a/edg/parts/__init__.py +++ b/edg/parts/__init__.py @@ -40,7 +40,13 @@ from .Inamp_Ina826 import Ina826 from .CeramicResonator_Cstne import Cstne -from .PassiveConnector_Header import PinHeader254, PinHeader254Vertical, PinHeader254Horizontal, PinSocket254 +from .PassiveConnector_Header import ( + PinHeader254, + PinHeader254Vertical, + PinHeader254Horizontal, + PinSocket254, + PinSocket254Pair, +) from .PassiveConnector_Header import PinHeader254DualShroudedInline from .PassiveConnector_Header import PinHeader127DualShrouded from .PassiveConnector_Header import ( @@ -63,6 +69,7 @@ Fpc050, Fpc050Top, Fpc050Bottom, + Fpc050Pair, Fpc050BottomFlip, HiroseFh12sh, Afc01, From 44d16f39f4846fc5d3fe8baeae36cf265b7d000b Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 16:13:45 -0700 Subject: [PATCH 09/14] Update PassiveConnector_Fpc.py --- edg/parts/PassiveConnector_Fpc.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/edg/parts/PassiveConnector_Fpc.py b/edg/parts/PassiveConnector_Fpc.py index 50b3748e1..c4142e7d7 100644 --- a/edg/parts/PassiveConnector_Fpc.py +++ b/edg/parts/PassiveConnector_Fpc.py @@ -28,7 +28,7 @@ class Fpc050Pair(SubboardConnectorPair, GeneratorBlock): and connector contact side. Parameters: - cable = "same" | "opposite: whether the FPC cable has contacts on the same side (Type A, mirror pin numbering) + cable = "same" | "opposite": whether the FPC cable has contacts on the same side (Type A, mirror pin numbering) or opposite sides (Type B, same pin numbering both sides) ext_contact, int_contact = "top" | "bottom": the contact side for the external and internal connectors, respectively. """ @@ -71,6 +71,7 @@ def generate(self) -> None: length = self.get(self.length) assert length > 0, "explicit length required" + # this determines whether to mirror the internal-side pinning if self.get(self.cable) == "same": # assuming same side contact side connectors mirror = True else: From 9c98b4797f5385be4eed432d9d72110a156e6205 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 16:23:57 -0700 Subject: [PATCH 10/14] use connector pairs in ble joystick --- edg/parts/PassiveConnector_Fpc.py | 2 +- examples/BleJoystick/BleJoystick.net.ref | 25 +++--- examples/BleJoystick/BleJoystick.svgpcb.js | 82 +++++++++---------- .../BleJoystick/BleJoystick_stick.net.ref | 46 +++++++++++ examples/test_ble_joystick.py | 21 ++++- 5 files changed, 119 insertions(+), 57 deletions(-) create mode 100644 examples/BleJoystick/BleJoystick_stick.net.ref diff --git a/edg/parts/PassiveConnector_Fpc.py b/edg/parts/PassiveConnector_Fpc.py index c4142e7d7..f52bb801e 100644 --- a/edg/parts/PassiveConnector_Fpc.py +++ b/edg/parts/PassiveConnector_Fpc.py @@ -46,7 +46,7 @@ def __init__( self.ext_contact = self.ArgParameter(ext_contact) self.int_contact = self.ArgParameter(int_contact) self.pins = self.Port(Vector(Passive.empty())) - self.generator_param(self.length, self.cable, self.ext_contact, self.int_contact) + self.generator_param(self.length, self.pins.requested(), self.cable, self.ext_contact, self.int_contact) @override def generate(self) -> None: diff --git a/examples/BleJoystick/BleJoystick.net.ref b/examples/BleJoystick/BleJoystick.net.ref index a17d87465..0f9fda683 100644 --- a/examples/BleJoystick/BleJoystick.net.ref +++ b/examples/BleJoystick/BleJoystick.net.ref @@ -360,16 +360,16 @@ (property (name "edg_value") (value "50V 1uF X5R ±10% 0603 Multilayer Ceramic Capacitors MLCC - SMD/SMT ROHS")) (sheetpath (names "/mcu/en_pull/") (tstamps "/02850146/0b9c02f0/")) (tstamps "00640064")) -(comp (ref "JU4") +(comp (ref "JJ4") (value "stick") - (footprint "edg:Joystick_XboxElite2") + (footprint "Connector_FFC-FPC:Hirose_FH12-6S-0.5SH_1x06-1MP_P0.50mm_Horizontal") (property (name "Sheetname") (value "")) (property (name "Sheetfile") (value "")) - (property (name "edg_path") (value "stick")) + (property (name "edg_path") (value "stick.conn.ext")) (property (name "edg_short_path") (value "stick")) - (property (name "edg_refdes") (value "JU4")) - (property (name "edg_part") (value "")) - (property (name "edg_value") (value "")) + (property (name "edg_refdes") (value "JJ4")) + (property (name "edg_part") (value "AFC01-S06FC*-00 (Jushuo)")) + (property (name "edg_value") (value "AFC01-S06FC*-00")) (sheetpath (names "/") (tstamps "/")) (tstamps "0680021f")) (comp (ref "JR4") @@ -619,9 +619,7 @@ (node (ref JJ3) (pin 5)) (node (ref JSW1) (pin 2)) (node (ref JC11) (pin 2)) - (node (ref JU4) (pin 2)) - (node (ref JU4) (pin 3)) - (node (ref JU4) (pin 8)) + (node (ref JJ4) (pin 1)) (node (ref JR5) (pin 2)) (node (ref JR7) (pin 2)) (node (ref JU5) (pin 3)) @@ -643,8 +641,7 @@ (node (ref JC10) (pin 1)) (node (ref JJ3) (pin 1)) (node (ref JR3) (pin 1)) - (node (ref JU4) (pin 5)) - (node (ref JU4) (pin 6)) + (node (ref JJ4) (pin 2)) (node (ref JU5) (pin 1)) (node (ref JC12) (pin 1)) (node (ref JD2) (pin 2)) @@ -678,7 +675,7 @@ (net (code 12) (name "Jmp2722.rst") (node (ref JU1) (pin 17)) (node (ref JU3) (pin 5)) - (node (ref JU4) (pin 1))) + (node (ref JJ4) (pin 4))) (net (code 13) (name "Jmp2722.int") (node (ref JU1) (pin 8))) (net (code 14) (name "Jmp2722.stat") @@ -727,10 +724,10 @@ (node (ref JSW1) (pin 1)) (node (ref JR10) (pin 2))) (net (code 28) (name "Jstick.ax1") - (node (ref JU4) (pin 4)) + (node (ref JJ4) (pin 5)) (node (ref JR4) (pin 1))) (net (code 29) (name "Jstick.ax2") - (node (ref JU4) (pin 7)) + (node (ref JJ4) (pin 6)) (node (ref JR6) (pin 1))) (net (code 30) (name "Jax1_div.output") (node (ref JU3) (pin 3)) diff --git a/examples/BleJoystick/BleJoystick.svgpcb.js b/examples/BleJoystick/BleJoystick.svgpcb.js index 53e489459..45a63cd02 100644 --- a/examples/BleJoystick/BleJoystick.svgpcb.js +++ b/examples/BleJoystick/BleJoystick.svgpcb.js @@ -2,22 +2,22 @@ const board = new PCB(); // jlc_th.th1 const JH1 = board.add(JlcToolingHole_1_152mm, { - translate: pt(1.481, 1.534), rotate: 0, + translate: pt(1.950, 1.551), rotate: 0, id: 'JH1' }) // jlc_th.th2 const JH2 = board.add(JlcToolingHole_1_152mm, { - translate: pt(1.520, 1.534), rotate: 0, + translate: pt(1.989, 1.551), rotate: 0, id: 'JH2' }) // jlc_th.th3 const JH3 = board.add(JlcToolingHole_1_152mm, { - translate: pt(1.481, 1.573), rotate: 0, + translate: pt(1.950, 1.591), rotate: 0, id: 'JH3' }) // bat.conn const JJ1 = board.add(JST_PH_B2B_PH_K_1x02_P2_00mm_Vertical, { - translate: pt(0.756, 1.252), rotate: 0, + translate: pt(1.233, 1.252), rotate: 0, id: 'JJ1' }) // usb.conn @@ -27,17 +27,17 @@ const JJ2 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { }) // tp_bat.tp const JTP1 = board.add(TestPoint_TE_RCT_0805, { - translate: pt(0.301, 1.571), rotate: 0, + translate: pt(0.770, 1.589), rotate: 0, id: 'JTP1' }) // tp_usb.tp const JTP2 = board.add(TestPoint_TE_RCT_0805, { - translate: pt(0.551, 1.571), rotate: 0, + translate: pt(1.020, 1.589), rotate: 0, id: 'JTP2' }) // tp_gnd.tp const JTP3 = board.add(TestPoint_TE_RCT_0805, { - translate: pt(0.802, 1.571), rotate: 0, + translate: pt(1.271, 1.589), rotate: 0, id: 'JTP3' }) // mp2722.ic @@ -82,37 +82,37 @@ const JC6 = board.add(C_0805_2012Metric, { }) // reg_3v3.ic const JU2 = board.add(SOT_89_3, { - translate: pt(0.112, 1.220), rotate: 0, + translate: pt(0.589, 1.220), rotate: 0, id: 'JU2' }) // reg_3v3.in_cap.cap const JC7 = board.add(C_0603_1608Metric, { - translate: pt(0.058, 1.387), rotate: 0, + translate: pt(0.535, 1.387), rotate: 0, id: 'JC7' }) // reg_3v3.out_cap.cap const JC8 = board.add(C_0603_1608Metric, { - translate: pt(0.214, 1.387), rotate: 0, + translate: pt(0.691, 1.387), rotate: 0, id: 'JC8' }) // tp_3v3.tp const JTP4 = board.add(TestPoint_TE_RCT_0805, { - translate: pt(1.052, 1.571), rotate: 0, + translate: pt(1.521, 1.589), rotate: 0, id: 'JTP4' }) // prot_3v3.diode const JD1 = board.add(D_SOD_323, { - translate: pt(1.300, 1.571), rotate: 0, + translate: pt(1.769, 1.589), rotate: 0, id: 'JD1' }) // fake_ntc.div.top_res const JR1 = board.add(R_0603_1608Metric, { - translate: pt(1.343, 1.151), rotate: 0, + translate: pt(1.819, 1.151), rotate: 0, id: 'JR1' }) // fake_ntc.div.bottom_res const JR2 = board.add(R_0603_1608Metric, { - translate: pt(1.343, 1.248), rotate: 0, + translate: pt(1.819, 1.248), rotate: 0, id: 'JR2' }) // mcu.ic @@ -150,102 +150,102 @@ const JC11 = board.add(C_0603_1608Metric, { translate: pt(1.376, 0.519), rotate: 0, id: 'JC11' }) -// stick -const JU4 = board.add(Joystick_XboxElite2, { - translate: pt(1.993, 1.534), rotate: 0, - id: 'JU4' +// stick.conn.ext +const JJ4 = board.add(Hirose_FH12_6S_0_5SH_1x06_1MP_P0_50mm_Horizontal, { + translate: pt(0.179, 1.315), rotate: 0, + id: 'JJ4' }) // ax1_div.div.top_res const JR4 = board.add(R_0603_1608Metric, { - translate: pt(1.577, 1.151), rotate: 0, + translate: pt(2.054, 1.151), rotate: 0, id: 'JR4' }) // ax1_div.div.bottom_res const JR5 = board.add(R_0603_1608Metric, { - translate: pt(1.577, 1.248), rotate: 0, + translate: pt(2.054, 1.248), rotate: 0, id: 'JR5' }) // ax2_div.div.top_res const JR6 = board.add(R_0603_1608Metric, { - translate: pt(1.812, 1.151), rotate: 0, + translate: pt(2.288, 1.151), rotate: 0, id: 'JR6' }) // ax2_div.div.bottom_res const JR7 = board.add(R_0603_1608Metric, { - translate: pt(1.812, 1.248), rotate: 0, + translate: pt(2.288, 1.248), rotate: 0, id: 'JR7' }) // trig.ic const JU5 = board.add(SOT_23, { - translate: pt(0.466, 1.189), rotate: 0, + translate: pt(0.943, 1.189), rotate: 0, id: 'JU5' }) // trig.cbyp.cap const JC12 = board.add(C_0603_1608Metric, { - translate: pt(0.449, 1.324), rotate: 0, + translate: pt(0.925, 1.324), rotate: 0, id: 'JC12' }) // trig_div.div.top_res const JR8 = board.add(R_0603_1608Metric, { - translate: pt(2.047, 1.151), rotate: 0, + translate: pt(0.058, 1.580), rotate: 0, id: 'JR8' }) // trig_div.div.bottom_res const JR9 = board.add(R_0603_1608Metric, { - translate: pt(2.047, 1.248), rotate: 0, + translate: pt(0.058, 1.677), rotate: 0, id: 'JR9' }) // sw[0].package const JSW2 = board.add(MembraneSwitch_4mm, { - translate: pt(1.638, 1.534), rotate: 0, + translate: pt(2.107, 1.551), rotate: 0, id: 'JSW2' }) // sw[1].package const JSW3 = board.add(MembraneSwitch_4mm, { - translate: pt(1.756, 1.534), rotate: 0, + translate: pt(2.226, 1.551), rotate: 0, id: 'JSW3' }) // sw[2].package const JSW4 = board.add(MembraneSwitch_4mm, { - translate: pt(1.874, 1.534), rotate: 0, + translate: pt(2.344, 1.551), rotate: 0, id: 'JSW4' }) // ledr.package const JD2 = board.add(LED_0603_1608Metric, { - translate: pt(1.108, 1.151), rotate: 0, + translate: pt(1.584, 1.151), rotate: 0, id: 'JD2' }) // ledr.res const JR10 = board.add(R_0603_1608Metric, { - translate: pt(1.108, 1.248), rotate: 0, + translate: pt(1.584, 1.248), rotate: 0, id: 'JR10' }) // vbat_sense.div.top_res const JR11 = board.add(R_0603_1608Metric, { - translate: pt(2.281, 1.151), rotate: 0, + translate: pt(0.293, 1.580), rotate: 0, id: 'JR11' }) // vbat_sense.div.bottom_res const JR12 = board.add(R_0603_1608Metric, { - translate: pt(2.281, 1.248), rotate: 0, + translate: pt(0.293, 1.677), rotate: 0, id: 'JR12' }) // i2c_pull.scl_res.res const JR13 = board.add(R_0603_1608Metric, { - translate: pt(0.058, 1.563), rotate: 0, + translate: pt(0.528, 1.580), rotate: 0, id: 'JR13' }) // i2c_pull.sda_res.res const JR14 = board.add(R_0603_1608Metric, { - translate: pt(0.058, 1.659), rotate: 0, + translate: pt(0.528, 1.677), rotate: 0, id: 'JR14' }) board.setNetlist([ {name: "Jvbat", pads: [["JJ1", "2"], ["JTP1", "1"], ["JU1", "12"], ["JU1", "14"], ["JC3", "1"], ["JR11", "1"]]}, {name: "Jvusb", pads: [["JJ2", "A4"], ["JJ2", "A9"], ["JJ2", "B4"], ["JJ2", "B9"], ["JTP2", "1"], ["JU1", "2"], ["JC5", "1"]]}, - {name: "Jgnd", pads: [["JJ1", "1"], ["JJ2", "A1"], ["JJ2", "A12"], ["JJ2", "B1"], ["JJ2", "B12"], ["JJ2", "S1"], ["JTP3", "1"], ["JU1", "18"], ["JU1", "5"], ["JC2", "2"], ["JC3", "2"], ["JC4", "2"], ["JC5", "2"], ["JC6", "2"], ["JU2", "1"], ["JC7", "2"], ["JC8", "2"], ["JD1", "2"], ["JR2", "2"], ["JU3", "19"], ["JU3", "9"], ["JC9", "2"], ["JC10", "2"], ["JJ3", "5"], ["JSW1", "2"], ["JC11", "2"], ["JU4", "2"], ["JU4", "3"], ["JU4", "8"], ["JR5", "2"], ["JR7", "2"], ["JU5", "3"], ["JC12", "2"], ["JR9", "2"], ["JSW2", "2"], ["JSW3", "2"], ["JSW4", "2"], ["JR12", "2"]]}, - {name: "Jv3v3", pads: [["JU2", "3"], ["JC8", "1"], ["JTP4", "1"], ["JD1", "1"], ["JU3", "1"], ["JU3", "16"], ["JU3", "7"], ["JC9", "1"], ["JC10", "1"], ["JJ3", "1"], ["JR3", "1"], ["JU4", "5"], ["JU4", "6"], ["JU5", "1"], ["JC12", "1"], ["JD2", "2"], ["JR13", "1"], ["JR14", "1"]]}, + {name: "Jgnd", pads: [["JJ1", "1"], ["JJ2", "A1"], ["JJ2", "A12"], ["JJ2", "B1"], ["JJ2", "B12"], ["JJ2", "S1"], ["JTP3", "1"], ["JU1", "18"], ["JU1", "5"], ["JC2", "2"], ["JC3", "2"], ["JC4", "2"], ["JC5", "2"], ["JC6", "2"], ["JU2", "1"], ["JC7", "2"], ["JC8", "2"], ["JD1", "2"], ["JR2", "2"], ["JU3", "19"], ["JU3", "9"], ["JC9", "2"], ["JC10", "2"], ["JJ3", "5"], ["JSW1", "2"], ["JC11", "2"], ["JJ4", "1"], ["JR5", "2"], ["JR7", "2"], ["JU5", "3"], ["JC12", "2"], ["JR9", "2"], ["JSW2", "2"], ["JSW3", "2"], ["JSW4", "2"], ["JR12", "2"]]}, + {name: "Jv3v3", pads: [["JU2", "3"], ["JC8", "1"], ["JTP4", "1"], ["JD1", "1"], ["JU3", "1"], ["JU3", "16"], ["JU3", "7"], ["JC9", "1"], ["JC10", "1"], ["JJ3", "1"], ["JR3", "1"], ["JJ4", "2"], ["JU5", "1"], ["JC12", "1"], ["JD2", "2"], ["JR13", "1"], ["JR14", "1"]]}, {name: "Jusb.usb.dp", pads: [["JJ2", "A6"], ["JJ2", "B6"]]}, {name: "Jusb.usb.dm", pads: [["JJ2", "A7"], ["JJ2", "B7"]]}, {name: "Jusb.cc.cc1", pads: [["JJ2", "A5"], ["JU1", "1"]]}, @@ -253,7 +253,7 @@ board.setNetlist([ {name: "Jmp2722.pwr_out", pads: [["JU1", "13"], ["JL1", "2"], ["JC6", "1"], ["JU2", "2"], ["JC7", "1"]]}, {name: "Jmp2722.vrntc", pads: [["JU1", "7"], ["JR1", "1"]]}, {name: "Jmp2722.ntc1", pads: [["JU1", "10"], ["JR1", "2"], ["JR2", "1"]]}, - {name: "Jmp2722.rst", pads: [["JU1", "17"], ["JU3", "5"], ["JU4", "1"]]}, + {name: "Jmp2722.rst", pads: [["JU1", "17"], ["JU3", "5"], ["JJ4", "4"]]}, {name: "Jmp2722.int", pads: [["JU1", "8"]]}, {name: "Jmp2722.stat", pads: [["JU1", "11"]]}, {name: "Jmp2722.pg", pads: [["JU1", "9"]]}, @@ -269,8 +269,8 @@ board.setNetlist([ {name: "Jmcu.program_uart_node.b_tx", pads: [["JU3", "11"], ["JJ3", "4"]]}, {name: "Jmcu.program_en_node", pads: [["JU3", "2"], ["JJ3", "6"], ["JR3", "2"], ["JC11", "1"]]}, {name: "Jmcu.program_boot_node", pads: [["JU3", "8"], ["JJ3", "2"], ["JSW1", "1"], ["JR10", "2"]]}, - {name: "Jstick.ax1", pads: [["JU4", "4"], ["JR4", "1"]]}, - {name: "Jstick.ax2", pads: [["JU4", "7"], ["JR6", "1"]]}, + {name: "Jstick.ax1", pads: [["JJ4", "5"], ["JR4", "1"]]}, + {name: "Jstick.ax2", pads: [["JJ4", "6"], ["JR6", "1"]]}, {name: "Jax1_div.output", pads: [["JU3", "3"], ["JR4", "2"], ["JR5", "1"]]}, {name: "Jax2_div.output", pads: [["JU3", "15"], ["JR6", "2"], ["JR7", "1"]]}, {name: "Jtrig.out", pads: [["JU5", "2"], ["JR8", "1"]]}, @@ -283,7 +283,7 @@ board.setNetlist([ ]) const limit0 = pt(-0.07874015748031496, -0.07874015748031496); -const limit1 = pt(2.457677165354331, 1.8062992125984254); +const limit1 = pt(2.464763779527559, 1.8236220472440945); const xMin = Math.min(limit0[0], limit1[0]); const xMax = Math.max(limit0[0], limit1[0]); const yMin = Math.min(limit0[1], limit1[1]); diff --git a/examples/BleJoystick/BleJoystick_stick.net.ref b/examples/BleJoystick/BleJoystick_stick.net.ref new file mode 100644 index 000000000..c6b66197f --- /dev/null +++ b/examples/BleJoystick/BleJoystick_stick.net.ref @@ -0,0 +1,46 @@ +(export (version D) +(components +(comp (ref "JU4") + (value "stick.stick") + (footprint "edg:Joystick_XboxElite2") + (property (name "Sheetname") (value "stick")) + (property (name "Sheetfile") (value "examples.test_ble_joystick.JoystickSubboard")) + (property (name "edg_path") (value "stick.stick")) + (property (name "edg_short_path") (value "stick.stick")) + (property (name "edg_refdes") (value "JU4")) + (property (name "edg_part") (value "")) + (property (name "edg_value") (value "")) + (sheetpath (names "/stick/") (tstamps "/0680021f/")) + (tstamps "0680021f")) +(comp (ref "JJ5") + (value "stick.conn") + (footprint "Connector_FFC-FPC:Hirose_FH12-6S-0.5SH_1x06-1MP_P0.50mm_Horizontal") + (property (name "Sheetname") (value "stick")) + (property (name "Sheetfile") (value "examples.test_ble_joystick.JoystickSubboard")) + (property (name "edg_path") (value "stick.conn.int")) + (property (name "edg_short_path") (value "stick.conn")) + (property (name "edg_refdes") (value "JJ5")) + (property (name "edg_part") (value "AFC01-S06FC*-00 (Jushuo)")) + (property (name "edg_value") (value "AFC01-S06FC*-00")) + (sheetpath (names "/stick/") (tstamps "/0680021f/")) + (tstamps "042701af"))) +(nets +(net (code 1) (name "Jstick.gnd") + (node (ref JU4) (pin 2)) + (node (ref JU4) (pin 3)) + (node (ref JU4) (pin 8)) + (node (ref JJ5) (pin 6))) +(net (code 2) (name "Jstick.pwr") + (node (ref JU4) (pin 5)) + (node (ref JU4) (pin 6)) + (node (ref JJ5) (pin 5))) +(net (code 3) (name "Jstick.sw") + (node (ref JU4) (pin 1)) + (node (ref JJ5) (pin 3))) +(net (code 4) (name "Jstick.ax1") + (node (ref JU4) (pin 4)) + (node (ref JJ5) (pin 2))) +(net (code 5) (name "Jstick.ax2") + (node (ref JU4) (pin 7)) + (node (ref JJ5) (pin 1)))) +) \ No newline at end of file diff --git a/examples/test_ble_joystick.py b/examples/test_ble_joystick.py index 840f3f40b..4ec1f8cf5 100644 --- a/examples/test_ble_joystick.py +++ b/examples/test_ble_joystick.py @@ -6,6 +6,25 @@ from .util import run_test_board +class JoystickSubboard(SubboardBlock): + def __init__(self) -> None: + super().__init__() + + self.stick = self.Block(XboxElite2Joystick()) + self.gnd = self.Export(self.stick.gnd, [Common]) + self.pwr = self.Export(self.stick.pwr, [Power]) + self.sw = self.Export(self.stick.sw) + self.ax1 = self.Export(self.stick.ax1) + self.ax2 = self.Export(self.stick.ax2) + + self.conn = self.Block(Fpc050Pair(6), external=True) + self.export_tap(self.gnd.net, self.conn.pins.request("1")) + self.export_tap(self.pwr.net, self.conn.pins.request("2")) + self.export_tap(self.sw.net, self.conn.pins.request("4")) + self.export_tap(self.ax1.net, self.conn.pins.request("5")) + self.export_tap(self.ax2.net, self.conn.pins.request("6")) + + class BleJoystick(JlcBoardTop): """BLE joystick with XYAB buttons""" @@ -69,7 +88,7 @@ def contents(self) -> None: self.mcu = imp.Block(IoController()) self.mcu.with_mixin(IoControllerWifi()) - self.stick = imp.Block(XboxElite2Joystick()) + self.stick = imp.Block(JoystickSubboard()) (self.ax1_div,), _ = self.chain( self.stick.ax1, imp.Block(SignalDivider(ratio=(0.45, 0.55), impedance=(1, 10) * kOhm)), From 1c60ff16d1d35fd2551bcf65fd8f6d3818ef938b Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 16:28:34 -0700 Subject: [PATCH 11/14] Update PassiveConnector_Fpc.py --- edg/parts/PassiveConnector_Fpc.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/edg/parts/PassiveConnector_Fpc.py b/edg/parts/PassiveConnector_Fpc.py index f52bb801e..6ceb3f824 100644 --- a/edg/parts/PassiveConnector_Fpc.py +++ b/edg/parts/PassiveConnector_Fpc.py @@ -52,8 +52,6 @@ def __init__( def generate(self) -> None: super().generate() ext_contact = self.get(self.ext_contact) - int_contact = self.get(self.int_contact) - if ext_contact == "top": self.ext: Fpc050 = self.Block(Fpc050Top(self.length), external=True) elif ext_contact == "bot": @@ -61,6 +59,7 @@ def generate(self) -> None: else: raise ValueError(f"invalid ext_contact") + int_contact = self.get(self.int_contact) if int_contact == "top": self.int: Fpc050 = self.Block(Fpc050Top(self.length)) elif int_contact == "bot": From e332abc5c98570b92da0ea8c3ee500e5ace4048b Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 16:52:35 -0700 Subject: [PATCH 12/14] multi netlsit diff --- examples/util.py | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/examples/util.py b/examples/util.py index d259eaca2..4e72e62bb 100644 --- a/examples/util.py +++ b/examples/util.py @@ -9,15 +9,23 @@ def run_test_board(design: Type[Block]) -> None: compile_board_inplace(design) - designfile = inspect.getfile(design) - with open(os.path.join(os.path.dirname(designfile), design.__name__, design.__name__ + ".net"), newline=None) as f: - generated_netlist = f.read() - - with open( - os.path.join(os.path.dirname(designfile), design.__name__, design.__name__ + ".net.ref"), newline=None - ) as f: - reference_netlist = f.read() - - assert ( - generated_netlist == reference_netlist - ), f"netlist differs from reference for {design.__name__}, if this is expected you may need to update the reference" + dirname = os.path.dirname(inspect.getfile(design)) + ref_net_filenames = [ + f[:-4] for f in os.listdir(dirname) if f.startswith(design.__name__) and f.endswith(".net.ref") + ] + net_filenames = [f for f in os.listdir(dirname) if f.startswith(design.__name__) and f.endswith(".net")] + + assert set(ref_net_filenames) == set( + net_filenames + ), f"reference netlist files {ref_net_filenames} do not match generated netlist files {net_filenames}" + + for net_filename in net_filenames: + with open(os.path.join(dirname, net_filename), newline=None) as f: + generated_netlist = f.read() + + with open(os.path.join(dirname, net_filename + ".ref"), newline=None) as f: + reference_netlist = f.read() + + assert ( + generated_netlist == reference_netlist + ), f"netlist differs from reference for {design.__name__}, if this is expected you may need to update the reference" From 6152a817689a0dd23ad2f8ab2b5f3a111505d28f Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 16:55:18 -0700 Subject: [PATCH 13/14] Update util.py --- examples/util.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/examples/util.py b/examples/util.py index 4e72e62bb..2433173fb 100644 --- a/examples/util.py +++ b/examples/util.py @@ -9,13 +9,12 @@ def run_test_board(design: Type[Block]) -> None: compile_board_inplace(design) - dirname = os.path.dirname(inspect.getfile(design)) - ref_net_filenames = [ - f[:-4] for f in os.listdir(dirname) if f.startswith(design.__name__) and f.endswith(".net.ref") - ] + dirname = os.path.join(os.path.dirname(inspect.getfile(design)), design.__name__) + ref_net_filenames = [f for f in os.listdir(dirname) if f.startswith(design.__name__) and f.endswith(".net.ref")] net_filenames = [f for f in os.listdir(dirname) if f.startswith(design.__name__) and f.endswith(".net")] - assert set(ref_net_filenames) == set( + assert net_filenames, "no netlist files found" + assert set(f[:-4] for f in ref_net_filenames) == set( net_filenames ), f"reference netlist files {ref_net_filenames} do not match generated netlist files {net_filenames}" From 7b34189392a8e1933164f6337ca986aeb0154005 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 17:06:33 -0700 Subject: [PATCH 14/14] cleaning --- edg/electronics_model/SubboardBlock.py | 2 +- edg/parts/PassiveConnector_Fpc.py | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/edg/electronics_model/SubboardBlock.py b/edg/electronics_model/SubboardBlock.py index 21bba3e96..5b6eba0a9 100644 --- a/edg/electronics_model/SubboardBlock.py +++ b/edg/electronics_model/SubboardBlock.py @@ -99,7 +99,7 @@ class SubboardConnectorPair(HasSubboardBlockApi, Block): while export-tapping ports from the external Block. The external Block should be generated first for refdes ordering. This block's pin numbering should correspond to the external Block. - These should not be instantiated outside a SubboardBlock or SubblockConnectorPair. Bad things can happen. + These should not be instantiated outside a SubboardBlock or SubboardConnectorPair. Bad things can happen. """ def __init__(self) -> None: diff --git a/edg/parts/PassiveConnector_Fpc.py b/edg/parts/PassiveConnector_Fpc.py index 6ceb3f824..5ee224208 100644 --- a/edg/parts/PassiveConnector_Fpc.py +++ b/edg/parts/PassiveConnector_Fpc.py @@ -71,10 +71,13 @@ def generate(self) -> None: assert length > 0, "explicit length required" # this determines whether to mirror the internal-side pinning - if self.get(self.cable) == "same": # assuming same side contact side connectors + cable = self.get(self.cable) + if cable == "same": # assuming same side contact side connectors mirror = True - else: + elif cable == "opposite": mirror = False + else: + raise ValueError(f"invalid cable") if ext_contact != int_contact: # account for different contact side mirror = not mirror