Basic-Verilog-Codes/encoder_4x2.v at main · Bharadwaj-R/Basic-Verilog-Codes · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

module encoder_4x2(out, in);

output reg [1:0] out;
input [3:0] in;

/* Dataflow model

assign out[0] = in[1] + in[3];
assign out[1] = in[2] + in[3];

*/


/*Structural Model

or o1(out[0], in[1], in[3]);
or o2(out[1], in[2], in[3]);

*/


/* Behavioral model - output is reg */

always @(in) begin

case(in)

4'b0001: out = 2'b00;
4'b0010: out = 2'b01;
4'b0100: out = 2'b10;
4'b1000: out = 2'b11;

endcase
end


endmodule


/* Testbench

module testbench;

reg [3:0] in;
wire [1:0] out;

encoder_4x2 enc(out, in);

initial begin

     in = 4'b0001;
#100 in = 4'b0010;
#100 in = 4'b0100;
#100 in = 4'b1000;

end

endmodule

*/

/* New Testbench

module testbench;

reg [3:0] i;
wire [1:0] o;

encoder_4x2 enc(.out(o), .in(i));

initial begin

     in = 4'b0001;
#100 in = 4'b0010;
#100 in = 4'b0100;
#100 in = 4'b1000;

end

endmodule

*/