From 6496279ea2e51e43de5b764d17bfa34c5126cf5a Mon Sep 17 00:00:00 2001 From: Rob Taylor Date: Fri, 27 Feb 2026 06:33:28 +0000 Subject: [PATCH] Fix wrap_openframe.py: use ~ instead of ! for OEB inversion Loom's sverilogparse cannot parse `!\escaped_name` (! immediately before backslash-escaped identifier). Using ~ (bitwise NOT) instead of ! (logical NOT) produces the same result for single-bit signals and is valid Verilog that the parser can handle. Co-developed-by: Claude Code v2.1.44 (claude-opus-4-6) --- scripts/wrap_openframe.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/wrap_openframe.py b/scripts/wrap_openframe.py index fff13c6..a6f2da9 100644 --- a/scripts/wrap_openframe.py +++ b/scripts/wrap_openframe.py @@ -240,7 +240,7 @@ def generate_wrapper(mappings: dict, top_ports: list[dict]) -> str: lines.append(f" assign gpio_out[{gpio_idx}] = {io_port} ; // {port_name} output") used_out_gpio.add(gpio_idx) oe_port = f"\\io${port_name}$oe" - lines.append(f" assign gpio_oeb[{gpio_idx}] = !{oe_port} ; // {port_name} OEB") + lines.append(f" assign gpio_oeb[{gpio_idx}] = ~{oe_port} ; // {port_name} OEB") used_oeb_gpio.add(gpio_idx) else: # Multi-bit port @@ -262,7 +262,7 @@ def generate_wrapper(mappings: dict, top_ports: list[dict]) -> str: if individual_oe: lines.append(f" assign gpio_oeb[{gpio_idx}] = ~{oe_port} [{bit}]; // {port_name}[{bit}] OEB") else: - lines.append(f" assign gpio_oeb[{gpio_idx}] = !{oe_port} ; // {port_name} OEB") + lines.append(f" assign gpio_oeb[{gpio_idx}] = ~{oe_port} ; // {port_name} OEB") used_oeb_gpio.add(gpio_idx) lines.append("")