Curated IP cores for use with chipflow-lib
This is a set of parameteriased and configurable RTL cores implmented or wrapped with Amaranth along with metadata for use with the ChipFlow platform. The cores also include verification tests.
Includes:
- Platform timer peripheral
- SoC ID peripheral
- GPIO peripheral
- I2C peripheral
- UART peripheral
- (Q)SPI peripheral
- QSPI Flash memory peripheral
- Hyperram memory peripheral
- Bus-attached SRAM peripheral
- Minerva RISC-V core
All existing code retains the copyright and license of its original developers; see original files for further details.