uboot.patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ba29e70acf..f029e7573a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -24,6 +24,9 @@ config TARGET_SIFIVE_UNMATCHED
 	bool "Support SiFive Unmatched Board"
 	select SYS_CACHE_SHIFT_6
 
+config TARGET_VIVADO_RISCV64
+	bool "Support RISC-V in Xilinx Vivado"
+
 config TARGET_SIPEED_MAIX
 	bool "Support Sipeed Maix Board"
 	select SYS_CACHE_SHIFT_6
@@ -61,6 +64,7 @@ config SPL_SYS_DCACHE_OFF
 source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
+source "board/xilinx/vivado_riscv64/Kconfig"
 source "board/sifive/unleashed/Kconfig"
 source "board/sifive/unmatched/Kconfig"
 source "board/openpiton/riscv64/Kconfig"
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 8d90c5e6b8..c5039bda9f 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -95,6 +95,9 @@ int arch_cpu_init_dm(void)
 		csr_write(CSR_FCSR, 0);
 	}
 
+	// Enable custom instructions
+	csr_set(MODE_PREFIX(status), (MSTATUS_XS & (MSTATUS_XS >> 1)));
+
 	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
 		/*
 		 * Enable perf counters for cycle, time,