A LUT 'lock/passSetFlag_i_2' is driving clock pin of 5 registers. This could lead to large hold time violations

[Darthpbal]

[Place 30-568] A LUT 'lock/passSetFlag_i_2' is driving clock pin of 5 registers. This could lead to large hold time violations. First few involved registers are:
stateMachine/rstCountFlag_reg {FDCE}
stateMachine/passSetFlag_reg {FDCE}
stateMachine/nextState_reg[0] {FDPE}
stateMachine/errFlag_reg {FDCE}
stateMachine/nextState_reg[1] {FDPE}

[Darthpbal]

Ugh, I still haven't fixed this fpga combo lock error.