From 71dcb2af7242e6ad358c648d5b203dd3f1d1e161 Mon Sep 17 00:00:00 2001
From: helloradiosky <839034809@qq.com>
Date: Wed, 5 Aug 2026 21:46:23 +0800
Subject: [PATCH] V14/V14LCD had no usable RTC battery reading because VBAT is
 ADC1-only, Route stick/pot/switch sampling through ADC2 (DMA2 Stream3) and
 keep RTC VBAT as a single-channel ADC1 EXT conversion . Add DMA Stream3 flag
 clearing in stm32_adc so ADC2 DMA IRQs are handled.

---
 radio/src/boards/hw_defs/v14.json             | 22 ++++++++-----------
 radio/src/boards/hw_defs/v14lcd.json          | 22 ++++++++-----------
 .../targets/common/arm/stm32/stm32_adc.cpp    | 10 +++++++--
 3 files changed, 26 insertions(+), 28 deletions(-)

diff --git a/radio/src/boards/hw_defs/v14.json b/radio/src/boards/hw_defs/v14.json
index 7d61618a693..fe44d2ad297 100644
--- a/radio/src/boards/hw_defs/v14.json
+++ b/radio/src/boards/hw_defs/v14.json
@@ -3,22 +3,18 @@
     "adcs": [
       {
         "name": "MAIN",
-        "adc": "ADC1",
+        "adc": "ADC2",
         "dma": "DMA2",
-        "dma_channel": "LL_DMA_CHANNEL_0",
-        "dma_stream": "LL_DMA_STREAM_4",
-        "dma_stream_irq": "DMA2_Stream4_IRQn",
-        "dma_stream_irq_handler": "DMA2_Stream4_IRQHandler",
+        "dma_channel": "LL_DMA_CHANNEL_1",
+        "dma_stream": "LL_DMA_STREAM_3",
+        "dma_stream_irq": "DMA2_Stream3_IRQn",
+        "dma_stream_irq_handler": "DMA2_Stream3_IRQHandler",
         "sample_time": "LL_ADC_SAMPLINGTIME_28CYCLES"
       },
       {
         "name": "EXT",
-        "adc": "ADC3",
-        "dma": "DMA2",
-        "dma_channel": "LL_DMA_CHANNEL_2",
-        "dma_stream": "LL_DMA_STREAM_0",
-        "dma_stream_irq": "DMA2_Stream0_IRQn",
-        "dma_stream_irq_handler": "DMA2_Stream0_IRQHandler",
+        "adc": "ADC1",
+        "dma": null,
         "sample_time": "LL_ADC_SAMPLINGTIME_56CYCLES"
       }
     ],
@@ -84,7 +80,7 @@
       {
         "name": "P3",
         "type": "FLEX",
-        "adc": "EXT",
+        "adc": "MAIN",
         "gpio": "GPIOC",
         "pin": "LL_GPIO_PIN_2",
         "channel": "LL_ADC_CHANNEL_12",
@@ -95,7 +91,7 @@
       {
         "name": "RTC_BAT",
         "type": "RTC_BAT",
-        "adc": "MAIN",
+        "adc": "EXT",
         "gpio": null,
         "pin": null,
         "channel": "LL_ADC_CHANNEL_VBAT"
diff --git a/radio/src/boards/hw_defs/v14lcd.json b/radio/src/boards/hw_defs/v14lcd.json
index 11fc24b6e6b..286a2736b76 100644
--- a/radio/src/boards/hw_defs/v14lcd.json
+++ b/radio/src/boards/hw_defs/v14lcd.json
@@ -3,22 +3,18 @@
     "adcs": [
       {
         "name": "MAIN",
-        "adc": "ADC1",
+        "adc": "ADC2",
         "dma": "DMA2",
-        "dma_channel": "LL_DMA_CHANNEL_0",
-        "dma_stream": "LL_DMA_STREAM_4",
-        "dma_stream_irq": "DMA2_Stream4_IRQn",
-        "dma_stream_irq_handler": "DMA2_Stream4_IRQHandler",
+        "dma_channel": "LL_DMA_CHANNEL_1",
+        "dma_stream": "LL_DMA_STREAM_3",
+        "dma_stream_irq": "DMA2_Stream3_IRQn",
+        "dma_stream_irq_handler": "DMA2_Stream3_IRQHandler",
         "sample_time": "LL_ADC_SAMPLINGTIME_28CYCLES"
       },
       {
         "name": "EXT",
-        "adc": "ADC3",
-        "dma": "DMA2",
-        "dma_channel": "LL_DMA_CHANNEL_2",
-        "dma_stream": "LL_DMA_STREAM_0",
-        "dma_stream_irq": "DMA2_Stream0_IRQn",
-        "dma_stream_irq_handler": "DMA2_Stream0_IRQHandler",
+        "adc": "ADC1",
+        "dma": null,
         "sample_time": "LL_ADC_SAMPLINGTIME_56CYCLES"
       }
     ],
@@ -84,7 +80,7 @@
       {
         "name": "P3",
         "type": "FLEX",
-        "adc": "EXT",
+        "adc": "MAIN",
         "gpio": "GPIOC",
         "pin": "LL_GPIO_PIN_2",
         "channel": "LL_ADC_CHANNEL_12",
@@ -95,7 +91,7 @@
       {
         "name": "RTC_BAT",
         "type": "RTC_BAT",
-        "adc": "MAIN",
+        "adc": "EXT",
         "gpio": null,
         "pin": null,
         "channel": "LL_ADC_CHANNEL_VBAT"
diff --git a/radio/src/targets/common/arm/stm32/stm32_adc.cpp b/radio/src/targets/common/arm/stm32/stm32_adc.cpp
index d4ccf128105..ef72cb95af9 100644
--- a/radio/src/targets/common/arm/stm32/stm32_adc.cpp
+++ b/radio/src/targets/common/arm/stm32/stm32_adc.cpp
@@ -577,7 +577,11 @@ static inline DMA_Stream_TypeDef* _dma_get_stream(DMA_TypeDef *DMAx, uint32_t St
 #define DMA_Stream0_IT_MASK     (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \
                                            DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \
                                            DMA_LISR_TCIF0)
-  
+
+#define DMA_Stream3_IT_MASK     (uint32_t)(DMA_LISR_FEIF3 | DMA_LISR_DMEIF3 | \
+                                           DMA_LISR_TEIF3 | DMA_LISR_HTIF3 | \
+                                           DMA_LISR_TCIF3)
+
 #define DMA_Stream4_IT_MASK     (uint32_t)(DMA_HISR_FEIF4 | DMA_HISR_DMEIF4 | \
                                            DMA_HISR_TEIF4 | DMA_HISR_HTIF4 | \
                                            DMA_HISR_TCIF4)
@@ -592,7 +596,9 @@ static void adc_dma_clear_flags(DMA_TypeDef* DMAx, uint32_t stream)
   if (stream == LL_DMA_STREAM_4) {
     /* Reset interrupt pending bits for DMA2 Stream4 */
     WRITE_REG(DMAx->HIFCR, DMA_Stream4_IT_MASK);
-
+  } else if (stream == LL_DMA_STREAM_3) {
+    /* Reset interrupt pending bits for DMA2 Stream3 (ADC2 on F4) */
+    WRITE_REG(DMAx->LIFCR, DMA_Stream3_IT_MASK);
   } else if (stream == LL_DMA_STREAM_0) {
     /* Reset interrupt pending bits for DMA2 Stream0 */
     WRITE_REG(DMAx->LIFCR, DMA_Stream0_IT_MASK);