Astran_adder.log

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_verilog /home/flynn/workplace/CEMapping/benchmark/adder/full_adder_16.v; hierarchy -top full_adder_16; flatten; synth -top full_adder_16; aigmap; write_aiger /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_16//full_adder_16.aig;' --

1. Executing Verilog-2005 frontend: /home/flynn/workplace/CEMapping/benchmark/adder/full_adder_16.v
Parsing Verilog input from `/home/flynn/workplace/CEMapping/benchmark/adder/full_adder_16.v' to AST representation.
Generating RTLIL representation for module `\full_adder_16'.
Generating RTLIL representation for module `\fullAdder'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \full_adder_16
Used module:     \fullAdder

2.2. Analyzing design hierarchy..
Top module:  \full_adder_16
Used module:     \fullAdder
Removed 0 unused modules.
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[15].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[14].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[13].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[12].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[11].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[10].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[9].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[8].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[7].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[6].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[5].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[4].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[3].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[2].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[1].f (fullAdder).
Mapping positional arguments of cell full_adder_16.generate_N_bit_Adder[0].f (fullAdder).

3. Executing FLATTEN pass (flatten design).
Using template fullAdder for cells of type fullAdder.
<suppressed ~16 debug messages>
No more expansions possible.
Deleting now unused module fullAdder.

4. Executing SYNTH pass.

4.1. Executing HIERARCHY pass (managing design hierarchy).

4.1.1. Analyzing design hierarchy..
Top module:  \full_adder_16

4.1.2. Analyzing design hierarchy..
Top module:  \full_adder_16
Removed 0 unused modules.

4.2. Executing PROC pass (convert processes to netlists).

4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

4.2.3. Executing PROC_INIT pass (extract init attributes).

4.2.4. Executing PROC_ARST pass (detect async resets in processes).

4.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

4.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).

4.2.7. Executing PROC_DFF pass (convert process syncs to FFs).

4.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..
Removed 0 unused cells and 32 unused wires.
<suppressed ~1 debug messages>

4.5. Executing CHECK pass (checking for obvious problems).
checking module full_adder_16..
found and reported 0 problems.

4.6. Executing OPT pass (performing simple optimizations).

4.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_16'.
Removed a total of 0 cells.

4.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_16..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_16.
Performed a total of 0 changes.

4.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_16'.
Removed a total of 0 cells.

4.6.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.6.9. Finished OPT passes. (There is nothing left to do.)

4.7. Executing WREDUCE pass (reducing word size of cells).

4.8. Executing PEEPOPT pass (run peephole optimizers).

4.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.10. Executing TECHMAP pass (map to technology primitives).

4.10.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

4.10.2. Continuing TECHMAP pass.
No more expansions possible.

4.11. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module full_adder_16:
  created 0 $alu and 0 $macc cells.

4.12. Executing SHARE pass (SAT-based resource sharing).

4.13. Executing OPT pass (performing simple optimizations).

4.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_16'.
Removed a total of 0 cells.

4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_16..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_16.
Performed a total of 0 changes.

4.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_16'.
Removed a total of 0 cells.

4.13.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.13.9. Finished OPT passes. (There is nothing left to do.)

4.14. Executing FSM pass (extract and optimize FSM).

4.14.1. Executing FSM_DETECT pass (finding FSMs in design).

4.14.2. Executing FSM_EXTRACT pass (extracting FSM from design).

4.14.3. Executing FSM_OPT pass (simple optimizations of FSMs).

4.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.14.5. Executing FSM_OPT pass (simple optimizations of FSMs).

4.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

4.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

4.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

4.15. Executing OPT pass (performing simple optimizations).

4.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_16'.
Removed a total of 0 cells.

4.15.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.15.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.15.5. Finished fast OPT passes.

4.16. Executing MEMORY pass.

4.16.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

4.16.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.16.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

4.16.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.16.5. Executing MEMORY_COLLECT pass (generating $mem cells).

4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.18. Executing OPT pass (performing simple optimizations).

4.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_16'.
Removed a total of 0 cells.

4.18.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.18.5. Finished fast OPT passes.

4.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

4.20. Executing OPT pass (performing simple optimizations).

4.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_16'.
Removed a total of 0 cells.

4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_16..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_16.
Performed a total of 0 changes.

4.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_16'.
Removed a total of 0 cells.

4.20.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.20.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.20.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.20.9. Finished OPT passes. (There is nothing left to do.)

4.21. Executing TECHMAP pass (map to technology primitives).

4.21.1. Executing Verilog-2005 frontend: <techmap.v>
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

4.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $xor.
No more expansions possible.
<suppressed ~112 debug messages>

4.22. Executing OPT pass (performing simple optimizations).

4.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_16'.
Removed a total of 0 cells.

4.22.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..

4.22.5. Finished fast OPT passes.

4.23. Executing ABC pass (technology mapping using ABC).

4.23.1. Extracting gate netlist of module `\full_adder_16' to `<abc-temp-dir>/input.blif'..
Extracted 112 gates and 145 wires to a netlist network with 33 inputs and 17 outputs.

4.23.1.1. Executing ABC.
Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 17 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + retime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

4.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        2
ABC RESULTS:            ANDNOT cells:       14
ABC RESULTS:              AOI3 cells:       14
ABC RESULTS:              NAND cells:        1
ABC RESULTS:               NOR cells:       13
ABC RESULTS:               NOT cells:       28
ABC RESULTS:              OAI3 cells:        2
ABC RESULTS:                OR cells:        1
ABC RESULTS:             ORNOT cells:        1
ABC RESULTS:              XNOR cells:       14
ABC RESULTS:               XOR cells:       18
ABC RESULTS:        internal signals:       95
ABC RESULTS:           input signals:       33
ABC RESULTS:          output signals:       17
Removing temp directory.

4.24. Executing OPT pass (performing simple optimizations).

4.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_16.

4.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_16'.
Removed a total of 0 cells.

4.24.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_16..
Removed 0 unused cells and 130 unused wires.
<suppressed ~1 debug messages>

4.24.5. Finished fast OPT passes.

4.25. Executing HIERARCHY pass (managing design hierarchy).

4.25.1. Analyzing design hierarchy..
Top module:  \full_adder_16

4.25.2. Analyzing design hierarchy..
Top module:  \full_adder_16
Removed 0 unused modules.

4.26. Printing statistics.

=== full_adder_16 ===

   Number of wires:                177
   Number of wire bits:            238
   Number of public wires:          86
   Number of public wire bits:     147
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                108
     $_ANDNOT_                      14
     $_AND_                          2
     $_AOI3_                        14
     $_NAND_                         1
     $_NOR_                         13
     $_NOT_                         28
     $_OAI3_                         2
     $_ORNOT_                        1
     $_OR_                           1
     $_XNOR_                        14
     $_XOR_                         18

4.27. Executing CHECK pass (checking for obvious problems).
checking module full_adder_16..
found and reported 0 problems.

5. Executing AIGMAP pass (map logic to AIG).
Module full_adder_16: replaced 78 cells with 382 new cells, skipped 30 cells.
  replaced 9 cell types:
       1 $_NAND_
       1 $_OR_
      13 $_NOR_
      18 $_XOR_
      14 $_XNOR_
      14 $_ANDNOT_
       1 $_ORNOT_
      14 $_AOI3_
       2 $_OAI3_
  not replaced 2 cell types:
      28 $_NOT_
       2 $_AND_

6. Executing AIGER backend.

End of script. Logfile hash: 26e8e72a81
CPU: user 0.18s system 0.01s, MEM: 17.29 MB total, 11.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 23% 13x opt_clean (0 sec), 12% 7x opt (0 sec), ...
>>> aig writing succeed!
[i] processing /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_16//full_adder_16.aig
resyn runtime: 0
[i] area: 297.0668922662735, gates: 96, depth: 25
mapping runtime: 0

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib stdCellLib/gscl45nm/gscl45nm.lib; read_verilog /tmp/N0H3QL2ZKF.v; write_blif -impltf /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_16//full_adder_16_init.blif;' --

1. Executing Liberty frontend.
Imported 32 cell types from liberty file.

2. Executing Verilog-2005 frontend: /tmp/N0H3QL2ZKF.v
Parsing Verilog input from `/tmp/N0H3QL2ZKF.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

3. Executing BLIF backend.

End of script. Logfile hash: 06fe8855bd
CPU: user 0.02s system 0.01s, MEM: 16.34 MB total, 10.00 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 51% 2x read_liberty (0 sec), 41% 2x read_verilog (0 sec), ...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib stdCellLib/gscl45nm/gscl45nm.lib; read_blif /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_16//full_adder_16_init.blif; stat -liberty stdCellLib/gscl45nm/gscl45nm.lib; ltp;' --

1. Executing Liberty frontend.
Imported 32 cell types from liberty file.

2. Executing BLIF frontend.

3. Printing statistics.

=== top ===

   Number of wires:                129
   Number of wire bits:            129
   Number of public wires:         129
   Number of public wire bits:     129
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 96
     AND2X2                          1
     AOI21X1                        12
     INVX1                          16
     NAND2X1                         7
     NAND3X1                         3
     NOR2X1                          6
     NOR3X1                          4
     OAI21X1                        11
     OR2X2                           4
     XNOR2X1                        28
     XOR2X1                          4

   Chip area for module '\top': 297.066900

4. Executing LTP pass (find longest path).

Longest topological path in top (length=25):
    0: \x0
    1: \n51 (via $auto$blifparse.cc:371:parse_blif$9)
    2: \n55 (via $auto$blifparse.cc:371:parse_blif$12)
    3: \n56 (via $auto$blifparse.cc:371:parse_blif$14)
    4: \n57 (via $auto$blifparse.cc:371:parse_blif$15)
    5: \n61 (via $auto$blifparse.cc:371:parse_blif$18)
    6: \n62 (via $auto$blifparse.cc:371:parse_blif$21)
    7: \n63 (via $auto$blifparse.cc:371:parse_blif$22)
    8: \n67 (via $auto$blifparse.cc:371:parse_blif$24)
    9: \n68 (via $auto$blifparse.cc:371:parse_blif$26)
   10: \n69 (via $auto$blifparse.cc:371:parse_blif$27)
   11: \n73 (via $auto$blifparse.cc:371:parse_blif$30)
   12: \n74 (via $auto$blifparse.cc:371:parse_blif$33)
   13: \n75 (via $auto$blifparse.cc:371:parse_blif$34)
   14: \n79 (via $auto$blifparse.cc:371:parse_blif$36)
   15: \n80 (via $auto$blifparse.cc:371:parse_blif$38)
   16: \n81 (via $auto$blifparse.cc:371:parse_blif$39)
   17: \n85 (via $auto$blifparse.cc:371:parse_blif$42)
   18: \n86 (via $auto$blifparse.cc:371:parse_blif$45)
   19: \n87 (via $auto$blifparse.cc:371:parse_blif$46)
   20: \n91 (via $auto$blifparse.cc:371:parse_blif$48)
   21: \n92 (via $auto$blifparse.cc:371:parse_blif$50)
   22: \n94 (via $auto$blifparse.cc:371:parse_blif$51)
   23: \n95 (via $auto$blifparse.cc:371:parse_blif$53)
   24: \n97 (via $auto$blifparse.cc:371:parse_blif$54)
   25: \y0 (via $auto$blifparse.cc:371:parse_blif$57)

End of script. Logfile hash: 1ed15c02b9
CPU: user 0.01s system 0.00s, MEM: 16.46 MB total, 10.00 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 44% 2x read_liberty (0 sec), 41% 1x stat (0 sec), ...
>>> initial mapping succeed with area = 297.0668922662735
[i] processing /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_16//full_adder_16.aig
resyn runtime: 0
[i] area: 209.91920280456543, gates: 37, depth: 17
mapping runtime: 0

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; read_verilog /tmp/RCJK64T2HZ.v; write_blif -impltf /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_16//full_adder_16_temacle.blif;' --

1. Executing Liberty frontend.
Imported 16 cell types from liberty file.

2. Executing Verilog-2005 frontend: /tmp/RCJK64T2HZ.v
Parsing Verilog input from `/tmp/RCJK64T2HZ.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

3. Executing BLIF backend.

End of script. Logfile hash: 5cb6ae94d9
CPU: user 0.01s system 0.00s, MEM: 15.95 MB total, 9.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 50% 2x read_verilog (0 sec), 37% 2x read_liberty (0 sec), ...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; read_blif /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_16//full_adder_16_temacle.blif; stat -liberty outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; ltp;' --

1. Executing Liberty frontend.
Imported 16 cell types from liberty file.

2. Executing BLIF frontend.

3. Printing statistics.

=== top ===

   Number of wires:                 70
   Number of wire bits:             70
   Number of public wires:          70
   Number of public wire bits:      70
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 37
     ADDER_G2_0_605                 16
     ADDER_G3_69_70_420             15
     AOI21X1                         2
     INVX1                           4

   Chip area for module '\top': 209.919200

4. Executing LTP pass (find longest path).

Longest topological path in top (length=17):
    0: \x0
    1: \n35 (via $auto$blifparse.cc:371:parse_blif$3)
    2: \n40 (via $auto$blifparse.cc:371:parse_blif$6)
    3: \n41 (via $auto$blifparse.cc:371:parse_blif$7)
    4: \n42 (via $auto$blifparse.cc:371:parse_blif$8)
    5: \n43 (via $auto$blifparse.cc:371:parse_blif$9)
    6: \n44 (via $auto$blifparse.cc:371:parse_blif$10)
    7: \n45 (via $auto$blifparse.cc:371:parse_blif$11)
    8: \n46 (via $auto$blifparse.cc:371:parse_blif$12)
    9: \n47 (via $auto$blifparse.cc:371:parse_blif$13)
   10: \n48 (via $auto$blifparse.cc:371:parse_blif$14)
   11: \n49 (via $auto$blifparse.cc:371:parse_blif$15)
   12: \n50 (via $auto$blifparse.cc:371:parse_blif$16)
   13: \n51 (via $auto$blifparse.cc:371:parse_blif$17)
   14: \n52 (via $auto$blifparse.cc:371:parse_blif$18)
   15: \n53 (via $auto$blifparse.cc:371:parse_blif$19)
   16: \n54 (via $auto$blifparse.cc:371:parse_blif$20)
   17: \y0 (via $auto$blifparse.cc:371:parse_blif$21)

End of script. Logfile hash: 64eef8a319
CPU: user 0.01s system 0.01s, MEM: 15.82 MB total, 9.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 44% 2x read_liberty (0 sec), 40% 1x stat (0 sec), ...
>>> Temacle mapping succeed with area = 209.91920280456543
full_adder_16 initial mapping area = 297.0668922662735
full_adder_16 Temacle mapping area = 209.91920280456543
full_adder_16 Temacle saveArea = (297.0668922662735 - 209.91920280456543) / 297.0668922662735 = 29.336049129161772 %

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_verilog /home/flynn/workplace/CEMapping/benchmark/adder/full_adder_32.v; hierarchy -top full_adder_32; flatten; synth -top full_adder_32; aigmap; write_aiger /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_32//full_adder_32.aig;' --

1. Executing Verilog-2005 frontend: /home/flynn/workplace/CEMapping/benchmark/adder/full_adder_32.v
Parsing Verilog input from `/home/flynn/workplace/CEMapping/benchmark/adder/full_adder_32.v' to AST representation.
Generating RTLIL representation for module `\full_adder_32'.
Generating RTLIL representation for module `\fullAdder'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \full_adder_32
Used module:     \fullAdder

2.2. Analyzing design hierarchy..
Top module:  \full_adder_32
Used module:     \fullAdder
Removed 0 unused modules.
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[31].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[30].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[29].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[28].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[27].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[26].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[25].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[24].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[23].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[22].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[21].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[20].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[19].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[18].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[17].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[16].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[15].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[14].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[13].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[12].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[11].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[10].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[9].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[8].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[7].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[6].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[5].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[4].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[3].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[2].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[1].f (fullAdder).
Mapping positional arguments of cell full_adder_32.generate_N_bit_Adder[0].f (fullAdder).

3. Executing FLATTEN pass (flatten design).
Using template fullAdder for cells of type fullAdder.
<suppressed ~32 debug messages>
No more expansions possible.
Deleting now unused module fullAdder.

4. Executing SYNTH pass.

4.1. Executing HIERARCHY pass (managing design hierarchy).

4.1.1. Analyzing design hierarchy..
Top module:  \full_adder_32

4.1.2. Analyzing design hierarchy..
Top module:  \full_adder_32
Removed 0 unused modules.

4.2. Executing PROC pass (convert processes to netlists).

4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

4.2.3. Executing PROC_INIT pass (extract init attributes).

4.2.4. Executing PROC_ARST pass (detect async resets in processes).

4.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

4.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).

4.2.7. Executing PROC_DFF pass (convert process syncs to FFs).

4.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..
Removed 0 unused cells and 64 unused wires.
<suppressed ~1 debug messages>

4.5. Executing CHECK pass (checking for obvious problems).
checking module full_adder_32..
found and reported 0 problems.

4.6. Executing OPT pass (performing simple optimizations).

4.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_32'.
Removed a total of 0 cells.

4.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_32..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_32.
Performed a total of 0 changes.

4.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_32'.
Removed a total of 0 cells.

4.6.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.6.9. Finished OPT passes. (There is nothing left to do.)

4.7. Executing WREDUCE pass (reducing word size of cells).

4.8. Executing PEEPOPT pass (run peephole optimizers).

4.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.10. Executing TECHMAP pass (map to technology primitives).

4.10.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

4.10.2. Continuing TECHMAP pass.
No more expansions possible.

4.11. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module full_adder_32:
  created 0 $alu and 0 $macc cells.

4.12. Executing SHARE pass (SAT-based resource sharing).

4.13. Executing OPT pass (performing simple optimizations).

4.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_32'.
Removed a total of 0 cells.

4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_32..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_32.
Performed a total of 0 changes.

4.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_32'.
Removed a total of 0 cells.

4.13.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.13.9. Finished OPT passes. (There is nothing left to do.)

4.14. Executing FSM pass (extract and optimize FSM).

4.14.1. Executing FSM_DETECT pass (finding FSMs in design).

4.14.2. Executing FSM_EXTRACT pass (extracting FSM from design).

4.14.3. Executing FSM_OPT pass (simple optimizations of FSMs).

4.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.14.5. Executing FSM_OPT pass (simple optimizations of FSMs).

4.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

4.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

4.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

4.15. Executing OPT pass (performing simple optimizations).

4.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_32'.
Removed a total of 0 cells.

4.15.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.15.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.15.5. Finished fast OPT passes.

4.16. Executing MEMORY pass.

4.16.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

4.16.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.16.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

4.16.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.16.5. Executing MEMORY_COLLECT pass (generating $mem cells).

4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.18. Executing OPT pass (performing simple optimizations).

4.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_32'.
Removed a total of 0 cells.

4.18.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.18.5. Finished fast OPT passes.

4.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

4.20. Executing OPT pass (performing simple optimizations).

4.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_32'.
Removed a total of 0 cells.

4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_32..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_32.
Performed a total of 0 changes.

4.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_32'.
Removed a total of 0 cells.

4.20.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.20.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.20.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.20.9. Finished OPT passes. (There is nothing left to do.)

4.21. Executing TECHMAP pass (map to technology primitives).

4.21.1. Executing Verilog-2005 frontend: <techmap.v>
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

4.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $xor.
No more expansions possible.
<suppressed ~224 debug messages>

4.22. Executing OPT pass (performing simple optimizations).

4.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_32'.
Removed a total of 0 cells.

4.22.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..

4.22.5. Finished fast OPT passes.

4.23. Executing ABC pass (technology mapping using ABC).

4.23.1. Extracting gate netlist of module `\full_adder_32' to `<abc-temp-dir>/input.blif'..
Extracted 224 gates and 289 wires to a netlist network with 65 inputs and 33 outputs.

4.23.1.1. Executing ABC.
Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 17 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + retime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

4.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        2
ABC RESULTS:            ANDNOT cells:       30
ABC RESULTS:              AOI3 cells:       30
ABC RESULTS:              NAND cells:        1
ABC RESULTS:               NOR cells:       29
ABC RESULTS:               NOT cells:       60
ABC RESULTS:              OAI3 cells:        2
ABC RESULTS:                OR cells:        1
ABC RESULTS:             ORNOT cells:        1
ABC RESULTS:              XNOR cells:       30
ABC RESULTS:               XOR cells:       34
ABC RESULTS:        internal signals:      191
ABC RESULTS:           input signals:       65
ABC RESULTS:          output signals:       33
Removing temp directory.

4.24. Executing OPT pass (performing simple optimizations).

4.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_32.

4.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_32'.
Removed a total of 0 cells.

4.24.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_32..
Removed 0 unused cells and 258 unused wires.
<suppressed ~1 debug messages>

4.24.5. Finished fast OPT passes.

4.25. Executing HIERARCHY pass (managing design hierarchy).

4.25.1. Analyzing design hierarchy..
Top module:  \full_adder_32

4.25.2. Analyzing design hierarchy..
Top module:  \full_adder_32
Removed 0 unused modules.

4.26. Printing statistics.

=== full_adder_32 ===

   Number of wires:                353
   Number of wire bits:            478
   Number of public wires:         166
   Number of public wire bits:     291
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                220
     $_ANDNOT_                      30
     $_AND_                          2
     $_AOI3_                        30
     $_NAND_                         1
     $_NOR_                         29
     $_NOT_                         60
     $_OAI3_                         2
     $_ORNOT_                        1
     $_OR_                           1
     $_XNOR_                        30
     $_XOR_                         34

4.27. Executing CHECK pass (checking for obvious problems).
checking module full_adder_32..
found and reported 0 problems.

5. Executing AIGMAP pass (map logic to AIG).
Module full_adder_32: replaced 158 cells with 766 new cells, skipped 62 cells.
  replaced 9 cell types:
       1 $_NAND_
       1 $_OR_
      29 $_NOR_
      34 $_XOR_
      30 $_XNOR_
      30 $_ANDNOT_
       1 $_ORNOT_
      30 $_AOI3_
       2 $_OAI3_
  not replaced 2 cell types:
      60 $_NOT_
       2 $_AND_

6. Executing AIGER backend.

End of script. Logfile hash: 2b698bdb42
CPU: user 0.33s system 0.02s, MEM: 17.93 MB total, 12.00 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 24% 13x opt_clean (0 sec), 14% 7x opt (0 sec), ...
>>> aig writing succeed!
[i] processing /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_32//full_adder_32.aig
resyn runtime: 0
[i] area: 593.6644846200943, gates: 192, depth: 49
mapping runtime: 0

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib stdCellLib/gscl45nm/gscl45nm.lib; read_verilog /tmp/FSJEIKZOUP.v; write_blif -impltf /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_32//full_adder_32_init.blif;' --

1. Executing Liberty frontend.
Imported 32 cell types from liberty file.

2. Executing Verilog-2005 frontend: /tmp/FSJEIKZOUP.v
Parsing Verilog input from `/tmp/FSJEIKZOUP.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

3. Executing BLIF backend.

End of script. Logfile hash: 8360cc2a97
CPU: user 0.02s system 0.01s, MEM: 17.24 MB total, 10.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 56% 2x read_verilog (0 sec), 36% 2x read_liberty (0 sec), ...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib stdCellLib/gscl45nm/gscl45nm.lib; read_blif /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_32//full_adder_32_init.blif; stat -liberty stdCellLib/gscl45nm/gscl45nm.lib; ltp;' --

1. Executing Liberty frontend.
Imported 32 cell types from liberty file.

2. Executing BLIF frontend.

3. Printing statistics.

=== top ===

   Number of wires:                257
   Number of wire bits:            257
   Number of public wires:         257
   Number of public wire bits:     257
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                192
     AND2X2                          1
     AOI21X1                        24
     INVX1                          32
     NAND2X1                        15
     NAND3X1                         7
     NOR2X1                         10
     NOR3X1                          8
     OAI21X1                        23
     OR2X2                           8
     XNOR2X1                        60
     XOR2X1                          4

   Chip area for module '\top': 593.664500

4. Executing LTP pass (find longest path).

Longest topological path in top (length=49):
    0: \x0
    1: \n99 (via $auto$blifparse.cc:371:parse_blif$17)
    2: \n103 (via $auto$blifparse.cc:371:parse_blif$20)
    3: \n104 (via $auto$blifparse.cc:371:parse_blif$22)
    4: \n105 (via $auto$blifparse.cc:371:parse_blif$23)
    5: \n109 (via $auto$blifparse.cc:371:parse_blif$26)
    6: \n110 (via $auto$blifparse.cc:371:parse_blif$29)
    7: \n111 (via $auto$blifparse.cc:371:parse_blif$30)
    8: \n115 (via $auto$blifparse.cc:371:parse_blif$32)
    9: \n116 (via $auto$blifparse.cc:371:parse_blif$34)
   10: \n117 (via $auto$blifparse.cc:371:parse_blif$35)
   11: \n121 (via $auto$blifparse.cc:371:parse_blif$38)
   12: \n122 (via $auto$blifparse.cc:371:parse_blif$41)
   13: \n123 (via $auto$blifparse.cc:371:parse_blif$42)
   14: \n127 (via $auto$blifparse.cc:371:parse_blif$44)
   15: \n128 (via $auto$blifparse.cc:371:parse_blif$46)
   16: \n129 (via $auto$blifparse.cc:371:parse_blif$47)
   17: \n133 (via $auto$blifparse.cc:371:parse_blif$50)
   18: \n134 (via $auto$blifparse.cc:371:parse_blif$53)
   19: \n135 (via $auto$blifparse.cc:371:parse_blif$54)
   20: \n139 (via $auto$blifparse.cc:371:parse_blif$56)
   21: \n140 (via $auto$blifparse.cc:371:parse_blif$58)
   22: \n141 (via $auto$blifparse.cc:371:parse_blif$59)
   23: \n145 (via $auto$blifparse.cc:371:parse_blif$62)
   24: \n146 (via $auto$blifparse.cc:371:parse_blif$65)
   25: \n147 (via $auto$blifparse.cc:371:parse_blif$66)
   26: \n151 (via $auto$blifparse.cc:371:parse_blif$68)
   27: \n152 (via $auto$blifparse.cc:371:parse_blif$70)
   28: \n153 (via $auto$blifparse.cc:371:parse_blif$71)
   29: \n157 (via $auto$blifparse.cc:371:parse_blif$74)
   30: \n158 (via $auto$blifparse.cc:371:parse_blif$77)
   31: \n159 (via $auto$blifparse.cc:371:parse_blif$78)
   32: \n163 (via $auto$blifparse.cc:371:parse_blif$80)
   33: \n164 (via $auto$blifparse.cc:371:parse_blif$82)
   34: \n165 (via $auto$blifparse.cc:371:parse_blif$83)
   35: \n169 (via $auto$blifparse.cc:371:parse_blif$86)
   36: \n170 (via $auto$blifparse.cc:371:parse_blif$89)
   37: \n171 (via $auto$blifparse.cc:371:parse_blif$90)
   38: \n175 (via $auto$blifparse.cc:371:parse_blif$92)
   39: \n176 (via $auto$blifparse.cc:371:parse_blif$94)
   40: \n177 (via $auto$blifparse.cc:371:parse_blif$95)
   41: \n181 (via $auto$blifparse.cc:371:parse_blif$98)
   42: \n182 (via $auto$blifparse.cc:371:parse_blif$101)
   43: \n183 (via $auto$blifparse.cc:371:parse_blif$102)
   44: \n187 (via $auto$blifparse.cc:371:parse_blif$104)
   45: \n188 (via $auto$blifparse.cc:371:parse_blif$106)
   46: \n190 (via $auto$blifparse.cc:371:parse_blif$107)
   47: \n191 (via $auto$blifparse.cc:371:parse_blif$109)
   48: \n193 (via $auto$blifparse.cc:371:parse_blif$110)
   49: \y0 (via $auto$blifparse.cc:371:parse_blif$113)

End of script. Logfile hash: 59981b241e
CPU: user 0.01s system 0.00s, MEM: 16.59 MB total, 10.00 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 42% 2x read_liberty (0 sec), 39% 1x stat (0 sec), ...
>>> initial mapping succeed with area = 593.6644846200943
[i] processing /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_32//full_adder_32.aig
resyn runtime: 0
[i] area: 414.71920585632324, gates: 69, depth: 33
mapping runtime: 0

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; read_verilog /tmp/72IN78E6GR.v; write_blif -impltf /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_32//full_adder_32_temacle.blif;' --

1. Executing Liberty frontend.
Imported 16 cell types from liberty file.

2. Executing Verilog-2005 frontend: /tmp/72IN78E6GR.v
Parsing Verilog input from `/tmp/72IN78E6GR.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

3. Executing BLIF backend.

End of script. Logfile hash: 628b13a46c
CPU: user 0.02s system 0.00s, MEM: 16.21 MB total, 9.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 61% 2x read_verilog (0 sec), 26% 2x read_liberty (0 sec), ...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; read_blif /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_32//full_adder_32_temacle.blif; stat -liberty outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; ltp;' --

1. Executing Liberty frontend.
Imported 16 cell types from liberty file.

2. Executing BLIF frontend.

3. Printing statistics.

=== top ===

   Number of wires:                134
   Number of wire bits:            134
   Number of public wires:         134
   Number of public wire bits:     134
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 69
     ADDER_G2_0_605                 32
     ADDER_G3_69_70_420             31
     AOI21X1                         2
     INVX1                           4

   Chip area for module '\top': 414.719200

4. Executing LTP pass (find longest path).

Longest topological path in top (length=33):
    0: \x0
    1: \n67 (via $auto$blifparse.cc:371:parse_blif$3)
    2: \n72 (via $auto$blifparse.cc:371:parse_blif$6)
    3: \n73 (via $auto$blifparse.cc:371:parse_blif$7)
    4: \n74 (via $auto$blifparse.cc:371:parse_blif$8)
    5: \n75 (via $auto$blifparse.cc:371:parse_blif$9)
    6: \n76 (via $auto$blifparse.cc:371:parse_blif$10)
    7: \n77 (via $auto$blifparse.cc:371:parse_blif$11)
    8: \n78 (via $auto$blifparse.cc:371:parse_blif$12)
    9: \n79 (via $auto$blifparse.cc:371:parse_blif$13)
   10: \n80 (via $auto$blifparse.cc:371:parse_blif$14)
   11: \n81 (via $auto$blifparse.cc:371:parse_blif$15)
   12: \n82 (via $auto$blifparse.cc:371:parse_blif$16)
   13: \n83 (via $auto$blifparse.cc:371:parse_blif$17)
   14: \n84 (via $auto$blifparse.cc:371:parse_blif$18)
   15: \n85 (via $auto$blifparse.cc:371:parse_blif$19)
   16: \n86 (via $auto$blifparse.cc:371:parse_blif$20)
   17: \n87 (via $auto$blifparse.cc:371:parse_blif$21)
   18: \n88 (via $auto$blifparse.cc:371:parse_blif$22)
   19: \n89 (via $auto$blifparse.cc:371:parse_blif$23)
   20: \n90 (via $auto$blifparse.cc:371:parse_blif$24)
   21: \n91 (via $auto$blifparse.cc:371:parse_blif$25)
   22: \n92 (via $auto$blifparse.cc:371:parse_blif$26)
   23: \n93 (via $auto$blifparse.cc:371:parse_blif$27)
   24: \n94 (via $auto$blifparse.cc:371:parse_blif$28)
   25: \n95 (via $auto$blifparse.cc:371:parse_blif$29)
   26: \n96 (via $auto$blifparse.cc:371:parse_blif$30)
   27: \n97 (via $auto$blifparse.cc:371:parse_blif$31)
   28: \n98 (via $auto$blifparse.cc:371:parse_blif$32)
   29: \n99 (via $auto$blifparse.cc:371:parse_blif$33)
   30: \n100 (via $auto$blifparse.cc:371:parse_blif$34)
   31: \n101 (via $auto$blifparse.cc:371:parse_blif$35)
   32: \n102 (via $auto$blifparse.cc:371:parse_blif$36)
   33: \y0 (via $auto$blifparse.cc:371:parse_blif$37)

End of script. Logfile hash: e2710f8db7
CPU: user 0.00s system 0.01s, MEM: 15.95 MB total, 9.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 42% 2x read_liberty (0 sec), 37% 1x stat (0 sec), ...
>>> Temacle mapping succeed with area = 414.71920585632324
full_adder_32 initial mapping area = 593.6644846200943
full_adder_32 Temacle mapping area = 414.71920585632324
full_adder_32 Temacle saveArea = (593.6644846200943 - 414.71920585632324) / 593.6644846200943 = 30.142493512692457 %

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_verilog /home/flynn/workplace/CEMapping/benchmark/adder/full_adder_64.v; hierarchy -top full_adder_64; flatten; synth -top full_adder_64; aigmap; write_aiger /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_64//full_adder_64.aig;' --

1. Executing Verilog-2005 frontend: /home/flynn/workplace/CEMapping/benchmark/adder/full_adder_64.v
Parsing Verilog input from `/home/flynn/workplace/CEMapping/benchmark/adder/full_adder_64.v' to AST representation.
Generating RTLIL representation for module `\full_adder_64'.
Generating RTLIL representation for module `\fullAdder'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \full_adder_64
Used module:     \fullAdder

2.2. Analyzing design hierarchy..
Top module:  \full_adder_64
Used module:     \fullAdder
Removed 0 unused modules.
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[63].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[62].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[61].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[60].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[59].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[58].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[57].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[56].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[55].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[54].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[53].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[52].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[51].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[50].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[49].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[48].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[47].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[46].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[45].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[44].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[43].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[42].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[41].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[40].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[39].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[38].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[37].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[36].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[35].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[34].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[33].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[32].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[31].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[30].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[29].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[28].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[27].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[26].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[25].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[24].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[23].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[22].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[21].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[20].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[19].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[18].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[17].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[16].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[15].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[14].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[13].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[12].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[11].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[10].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[9].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[8].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[7].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[6].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[5].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[4].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[3].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[2].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[1].f (fullAdder).
Mapping positional arguments of cell full_adder_64.generate_N_bit_Adder[0].f (fullAdder).

3. Executing FLATTEN pass (flatten design).
Using template fullAdder for cells of type fullAdder.
<suppressed ~64 debug messages>
No more expansions possible.
Deleting now unused module fullAdder.

4. Executing SYNTH pass.

4.1. Executing HIERARCHY pass (managing design hierarchy).

4.1.1. Analyzing design hierarchy..
Top module:  \full_adder_64

4.1.2. Analyzing design hierarchy..
Top module:  \full_adder_64
Removed 0 unused modules.

4.2. Executing PROC pass (convert processes to netlists).

4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

4.2.3. Executing PROC_INIT pass (extract init attributes).

4.2.4. Executing PROC_ARST pass (detect async resets in processes).

4.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

4.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).

4.2.7. Executing PROC_DFF pass (convert process syncs to FFs).

4.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..
Removed 0 unused cells and 128 unused wires.
<suppressed ~1 debug messages>

4.5. Executing CHECK pass (checking for obvious problems).
checking module full_adder_64..
found and reported 0 problems.

4.6. Executing OPT pass (performing simple optimizations).

4.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_64'.
Removed a total of 0 cells.

4.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_64..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_64.
Performed a total of 0 changes.

4.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_64'.
Removed a total of 0 cells.

4.6.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.6.9. Finished OPT passes. (There is nothing left to do.)

4.7. Executing WREDUCE pass (reducing word size of cells).

4.8. Executing PEEPOPT pass (run peephole optimizers).

4.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.10. Executing TECHMAP pass (map to technology primitives).

4.10.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

4.10.2. Continuing TECHMAP pass.
No more expansions possible.

4.11. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module full_adder_64:
  created 0 $alu and 0 $macc cells.

4.12. Executing SHARE pass (SAT-based resource sharing).

4.13. Executing OPT pass (performing simple optimizations).

4.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_64'.
Removed a total of 0 cells.

4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_64..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_64.
Performed a total of 0 changes.

4.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_64'.
Removed a total of 0 cells.

4.13.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.13.9. Finished OPT passes. (There is nothing left to do.)

4.14. Executing FSM pass (extract and optimize FSM).

4.14.1. Executing FSM_DETECT pass (finding FSMs in design).

4.14.2. Executing FSM_EXTRACT pass (extracting FSM from design).

4.14.3. Executing FSM_OPT pass (simple optimizations of FSMs).

4.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.14.5. Executing FSM_OPT pass (simple optimizations of FSMs).

4.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

4.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

4.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

4.15. Executing OPT pass (performing simple optimizations).

4.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_64'.
Removed a total of 0 cells.

4.15.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.15.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.15.5. Finished fast OPT passes.

4.16. Executing MEMORY pass.

4.16.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

4.16.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.16.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

4.16.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.16.5. Executing MEMORY_COLLECT pass (generating $mem cells).

4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.18. Executing OPT pass (performing simple optimizations).

4.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_64'.
Removed a total of 0 cells.

4.18.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.18.5. Finished fast OPT passes.

4.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

4.20. Executing OPT pass (performing simple optimizations).

4.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_64'.
Removed a total of 0 cells.

4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_64..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_64.
Performed a total of 0 changes.

4.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_64'.
Removed a total of 0 cells.

4.20.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.20.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.20.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.20.9. Finished OPT passes. (There is nothing left to do.)

4.21. Executing TECHMAP pass (map to technology primitives).

4.21.1. Executing Verilog-2005 frontend: <techmap.v>
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

4.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $xor.
No more expansions possible.
<suppressed ~448 debug messages>

4.22. Executing OPT pass (performing simple optimizations).

4.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_64'.
Removed a total of 0 cells.

4.22.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..

4.22.5. Finished fast OPT passes.

4.23. Executing ABC pass (technology mapping using ABC).

4.23.1. Extracting gate netlist of module `\full_adder_64' to `<abc-temp-dir>/input.blif'..
Extracted 448 gates and 577 wires to a netlist network with 129 inputs and 65 outputs.

4.23.1.1. Executing ABC.
Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 17 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + retime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

4.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        2
ABC RESULTS:            ANDNOT cells:       62
ABC RESULTS:              AOI3 cells:       62
ABC RESULTS:              NAND cells:        1
ABC RESULTS:               NOR cells:       61
ABC RESULTS:               NOT cells:      124
ABC RESULTS:              OAI3 cells:        2
ABC RESULTS:                OR cells:        1
ABC RESULTS:             ORNOT cells:        1
ABC RESULTS:              XNOR cells:       62
ABC RESULTS:               XOR cells:       66
ABC RESULTS:        internal signals:      383
ABC RESULTS:           input signals:      129
ABC RESULTS:          output signals:       65
Removing temp directory.

4.24. Executing OPT pass (performing simple optimizations).

4.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_64.

4.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_64'.
Removed a total of 0 cells.

4.24.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_64..
Removed 0 unused cells and 514 unused wires.
<suppressed ~1 debug messages>

4.24.5. Finished fast OPT passes.

4.25. Executing HIERARCHY pass (managing design hierarchy).

4.25.1. Analyzing design hierarchy..
Top module:  \full_adder_64

4.25.2. Analyzing design hierarchy..
Top module:  \full_adder_64
Removed 0 unused modules.

4.26. Printing statistics.

=== full_adder_64 ===

   Number of wires:                705
   Number of wire bits:            958
   Number of public wires:         326
   Number of public wire bits:     579
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                444
     $_ANDNOT_                      62
     $_AND_                          2
     $_AOI3_                        62
     $_NAND_                         1
     $_NOR_                         61
     $_NOT_                        124
     $_OAI3_                         2
     $_ORNOT_                        1
     $_OR_                           1
     $_XNOR_                        62
     $_XOR_                         66

4.27. Executing CHECK pass (checking for obvious problems).
checking module full_adder_64..
found and reported 0 problems.

5. Executing AIGMAP pass (map logic to AIG).
Module full_adder_64: replaced 318 cells with 1534 new cells, skipped 126 cells.
  replaced 9 cell types:
       1 $_NAND_
       1 $_OR_
      61 $_NOR_
      66 $_XOR_
      62 $_XNOR_
      62 $_ANDNOT_
       1 $_ORNOT_
      62 $_AOI3_
       2 $_OAI3_
  not replaced 2 cell types:
     124 $_NOT_
       2 $_AND_

6. Executing AIGER backend.

End of script. Logfile hash: dabcc4df70
CPU: user 0.65s system 0.00s, MEM: 19.78 MB total, 13.00 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 25% 13x opt_clean (0 sec), 15% 7x opt (0 sec), ...
>>> aig writing succeed!
[i] processing /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_64//full_adder_64.aig
resyn runtime: 0
[i] area: 1186.859669327736, gates: 384, depth: 97
mapping runtime: 0

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib stdCellLib/gscl45nm/gscl45nm.lib; read_verilog /tmp/1LPYCPG47W.v; write_blif -impltf /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_64//full_adder_64_init.blif;' --

1. Executing Liberty frontend.
Imported 32 cell types from liberty file.

2. Executing Verilog-2005 frontend: /tmp/1LPYCPG47W.v
Parsing Verilog input from `/tmp/1LPYCPG47W.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

3. Executing BLIF backend.

End of script. Logfile hash: fbb1110abf
CPU: user 0.04s system 0.01s, MEM: 18.81 MB total, 12.00 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 67% 2x read_verilog (0 sec), 22% 2x read_liberty (0 sec), ...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib stdCellLib/gscl45nm/gscl45nm.lib; read_blif /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_64//full_adder_64_init.blif; stat -liberty stdCellLib/gscl45nm/gscl45nm.lib; ltp;' --

1. Executing Liberty frontend.
Imported 32 cell types from liberty file.

2. Executing BLIF frontend.

3. Printing statistics.

=== top ===

   Number of wires:                513
   Number of wire bits:            513
   Number of public wires:         513
   Number of public wire bits:     513
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                384
     AND2X2                          1
     AOI21X1                        48
     INVX1                          64
     NAND2X1                        31
     NAND3X1                        15
     NOR2X1                         18
     NOR3X1                         16
     OAI21X1                        47
     OR2X2                          16
     XNOR2X1                       124
     XOR2X1                          4

   Chip area for module '\top': 1186.859700

4. Executing LTP pass (find longest path).

Longest topological path in top (length=97):
    0: \x0
    1: \n195 (via $auto$blifparse.cc:371:parse_blif$33)
    2: \n199 (via $auto$blifparse.cc:371:parse_blif$36)
    3: \n200 (via $auto$blifparse.cc:371:parse_blif$38)
    4: \n201 (via $auto$blifparse.cc:371:parse_blif$39)
    5: \n205 (via $auto$blifparse.cc:371:parse_blif$42)
    6: \n206 (via $auto$blifparse.cc:371:parse_blif$45)
    7: \n207 (via $auto$blifparse.cc:371:parse_blif$46)
    8: \n211 (via $auto$blifparse.cc:371:parse_blif$48)
    9: \n212 (via $auto$blifparse.cc:371:parse_blif$50)
   10: \n213 (via $auto$blifparse.cc:371:parse_blif$51)
   11: \n217 (via $auto$blifparse.cc:371:parse_blif$54)
   12: \n218 (via $auto$blifparse.cc:371:parse_blif$57)
   13: \n219 (via $auto$blifparse.cc:371:parse_blif$58)
   14: \n223 (via $auto$blifparse.cc:371:parse_blif$60)
   15: \n224 (via $auto$blifparse.cc:371:parse_blif$62)
   16: \n225 (via $auto$blifparse.cc:371:parse_blif$63)
   17: \n229 (via $auto$blifparse.cc:371:parse_blif$66)
   18: \n230 (via $auto$blifparse.cc:371:parse_blif$69)
   19: \n231 (via $auto$blifparse.cc:371:parse_blif$70)
   20: \n235 (via $auto$blifparse.cc:371:parse_blif$72)
   21: \n236 (via $auto$blifparse.cc:371:parse_blif$74)
   22: \n237 (via $auto$blifparse.cc:371:parse_blif$75)
   23: \n241 (via $auto$blifparse.cc:371:parse_blif$78)
   24: \n242 (via $auto$blifparse.cc:371:parse_blif$81)
   25: \n243 (via $auto$blifparse.cc:371:parse_blif$82)
   26: \n247 (via $auto$blifparse.cc:371:parse_blif$84)
   27: \n248 (via $auto$blifparse.cc:371:parse_blif$86)
   28: \n249 (via $auto$blifparse.cc:371:parse_blif$87)
   29: \n253 (via $auto$blifparse.cc:371:parse_blif$90)
   30: \n254 (via $auto$blifparse.cc:371:parse_blif$93)
   31: \n255 (via $auto$blifparse.cc:371:parse_blif$94)
   32: \n259 (via $auto$blifparse.cc:371:parse_blif$96)
   33: \n260 (via $auto$blifparse.cc:371:parse_blif$98)
   34: \n261 (via $auto$blifparse.cc:371:parse_blif$99)
   35: \n265 (via $auto$blifparse.cc:371:parse_blif$102)
   36: \n266 (via $auto$blifparse.cc:371:parse_blif$105)
   37: \n267 (via $auto$blifparse.cc:371:parse_blif$106)
   38: \n271 (via $auto$blifparse.cc:371:parse_blif$108)
   39: \n272 (via $auto$blifparse.cc:371:parse_blif$110)
   40: \n273 (via $auto$blifparse.cc:371:parse_blif$111)
   41: \n277 (via $auto$blifparse.cc:371:parse_blif$114)
   42: \n278 (via $auto$blifparse.cc:371:parse_blif$117)
   43: \n279 (via $auto$blifparse.cc:371:parse_blif$118)
   44: \n283 (via $auto$blifparse.cc:371:parse_blif$120)
   45: \n284 (via $auto$blifparse.cc:371:parse_blif$122)
   46: \n285 (via $auto$blifparse.cc:371:parse_blif$123)
   47: \n289 (via $auto$blifparse.cc:371:parse_blif$126)
   48: \n290 (via $auto$blifparse.cc:371:parse_blif$129)
   49: \n291 (via $auto$blifparse.cc:371:parse_blif$130)
   50: \n295 (via $auto$blifparse.cc:371:parse_blif$132)
   51: \n296 (via $auto$blifparse.cc:371:parse_blif$134)
   52: \n297 (via $auto$blifparse.cc:371:parse_blif$135)
   53: \n301 (via $auto$blifparse.cc:371:parse_blif$138)
   54: \n302 (via $auto$blifparse.cc:371:parse_blif$141)
   55: \n303 (via $auto$blifparse.cc:371:parse_blif$142)
   56: \n307 (via $auto$blifparse.cc:371:parse_blif$144)
   57: \n308 (via $auto$blifparse.cc:371:parse_blif$146)
   58: \n309 (via $auto$blifparse.cc:371:parse_blif$147)
   59: \n313 (via $auto$blifparse.cc:371:parse_blif$150)
   60: \n314 (via $auto$blifparse.cc:371:parse_blif$153)
   61: \n315 (via $auto$blifparse.cc:371:parse_blif$154)
   62: \n319 (via $auto$blifparse.cc:371:parse_blif$156)
   63: \n320 (via $auto$blifparse.cc:371:parse_blif$158)
   64: \n321 (via $auto$blifparse.cc:371:parse_blif$159)
   65: \n325 (via $auto$blifparse.cc:371:parse_blif$162)
   66: \n326 (via $auto$blifparse.cc:371:parse_blif$165)
   67: \n327 (via $auto$blifparse.cc:371:parse_blif$166)
   68: \n331 (via $auto$blifparse.cc:371:parse_blif$168)
   69: \n332 (via $auto$blifparse.cc:371:parse_blif$170)
   70: \n333 (via $auto$blifparse.cc:371:parse_blif$171)
   71: \n337 (via $auto$blifparse.cc:371:parse_blif$174)
   72: \n338 (via $auto$blifparse.cc:371:parse_blif$177)
   73: \n339 (via $auto$blifparse.cc:371:parse_blif$178)
   74: \n343 (via $auto$blifparse.cc:371:parse_blif$180)
   75: \n344 (via $auto$blifparse.cc:371:parse_blif$182)
   76: \n345 (via $auto$blifparse.cc:371:parse_blif$183)
   77: \n349 (via $auto$blifparse.cc:371:parse_blif$186)
   78: \n350 (via $auto$blifparse.cc:371:parse_blif$189)
   79: \n351 (via $auto$blifparse.cc:371:parse_blif$190)
   80: \n355 (via $auto$blifparse.cc:371:parse_blif$192)
   81: \n356 (via $auto$blifparse.cc:371:parse_blif$194)
   82: \n357 (via $auto$blifparse.cc:371:parse_blif$195)
   83: \n361 (via $auto$blifparse.cc:371:parse_blif$198)
   84: \n362 (via $auto$blifparse.cc:371:parse_blif$201)
   85: \n363 (via $auto$blifparse.cc:371:parse_blif$202)
   86: \n367 (via $auto$blifparse.cc:371:parse_blif$204)
   87: \n368 (via $auto$blifparse.cc:371:parse_blif$206)
   88: \n369 (via $auto$blifparse.cc:371:parse_blif$207)
   89: \n373 (via $auto$blifparse.cc:371:parse_blif$210)
   90: \n374 (via $auto$blifparse.cc:371:parse_blif$213)
   91: \n375 (via $auto$blifparse.cc:371:parse_blif$214)
   92: \n379 (via $auto$blifparse.cc:371:parse_blif$216)
   93: \n380 (via $auto$blifparse.cc:371:parse_blif$218)
   94: \n382 (via $auto$blifparse.cc:371:parse_blif$219)
   95: \n383 (via $auto$blifparse.cc:371:parse_blif$221)
   96: \n385 (via $auto$blifparse.cc:371:parse_blif$222)
   97: \y0 (via $auto$blifparse.cc:371:parse_blif$225)

End of script. Logfile hash: 0097b85f7d
CPU: user 0.01s system 0.00s, MEM: 16.85 MB total, 10.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 36% 1x stat (0 sec), 35% 2x read_liberty (0 sec), ...
>>> initial mapping succeed with area = 1186.859669327736
[i] processing /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_64//full_adder_64.aig
resyn runtime: 0
[i] area: 824.3192119598389, gates: 133, depth: 65
mapping runtime: 0

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; read_verilog /tmp/DFW0TT1KUE.v; write_blif -impltf /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_64//full_adder_64_temacle.blif;' --

1. Executing Liberty frontend.
Imported 16 cell types from liberty file.

2. Executing Verilog-2005 frontend: /tmp/DFW0TT1KUE.v
Parsing Verilog input from `/tmp/DFW0TT1KUE.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

3. Executing BLIF backend.

End of script. Logfile hash: d8bfb9aac8
CPU: user 0.02s system 0.00s, MEM: 16.98 MB total, 10.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 73% 2x read_verilog (0 sec), 13% 2x read_liberty (0 sec), ...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; read_blif /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_64//full_adder_64_temacle.blif; stat -liberty outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; ltp;' --

1. Executing Liberty frontend.
Imported 16 cell types from liberty file.

2. Executing BLIF frontend.

3. Printing statistics.

=== top ===

   Number of wires:                262
   Number of wire bits:            262
   Number of public wires:         262
   Number of public wire bits:     262
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                133
     ADDER_G2_0_605                 64
     ADDER_G3_69_70_420             63
     AOI21X1                         2
     INVX1                           4

   Chip area for module '\top': 824.319200

4. Executing LTP pass (find longest path).

Longest topological path in top (length=65):
    0: \x0
    1: \n131 (via $auto$blifparse.cc:371:parse_blif$3)
    2: \n136 (via $auto$blifparse.cc:371:parse_blif$6)
    3: \n137 (via $auto$blifparse.cc:371:parse_blif$7)
    4: \n138 (via $auto$blifparse.cc:371:parse_blif$8)
    5: \n139 (via $auto$blifparse.cc:371:parse_blif$9)
    6: \n140 (via $auto$blifparse.cc:371:parse_blif$10)
    7: \n141 (via $auto$blifparse.cc:371:parse_blif$11)
    8: \n142 (via $auto$blifparse.cc:371:parse_blif$12)
    9: \n143 (via $auto$blifparse.cc:371:parse_blif$13)
   10: \n144 (via $auto$blifparse.cc:371:parse_blif$14)
   11: \n145 (via $auto$blifparse.cc:371:parse_blif$15)
   12: \n146 (via $auto$blifparse.cc:371:parse_blif$16)
   13: \n147 (via $auto$blifparse.cc:371:parse_blif$17)
   14: \n148 (via $auto$blifparse.cc:371:parse_blif$18)
   15: \n149 (via $auto$blifparse.cc:371:parse_blif$19)
   16: \n150 (via $auto$blifparse.cc:371:parse_blif$20)
   17: \n151 (via $auto$blifparse.cc:371:parse_blif$21)
   18: \n152 (via $auto$blifparse.cc:371:parse_blif$22)
   19: \n153 (via $auto$blifparse.cc:371:parse_blif$23)
   20: \n154 (via $auto$blifparse.cc:371:parse_blif$24)
   21: \n155 (via $auto$blifparse.cc:371:parse_blif$25)
   22: \n156 (via $auto$blifparse.cc:371:parse_blif$26)
   23: \n157 (via $auto$blifparse.cc:371:parse_blif$27)
   24: \n158 (via $auto$blifparse.cc:371:parse_blif$28)
   25: \n159 (via $auto$blifparse.cc:371:parse_blif$29)
   26: \n160 (via $auto$blifparse.cc:371:parse_blif$30)
   27: \n161 (via $auto$blifparse.cc:371:parse_blif$31)
   28: \n162 (via $auto$blifparse.cc:371:parse_blif$32)
   29: \n163 (via $auto$blifparse.cc:371:parse_blif$33)
   30: \n164 (via $auto$blifparse.cc:371:parse_blif$34)
   31: \n165 (via $auto$blifparse.cc:371:parse_blif$35)
   32: \n166 (via $auto$blifparse.cc:371:parse_blif$36)
   33: \n167 (via $auto$blifparse.cc:371:parse_blif$37)
   34: \n168 (via $auto$blifparse.cc:371:parse_blif$38)
   35: \n169 (via $auto$blifparse.cc:371:parse_blif$39)
   36: \n170 (via $auto$blifparse.cc:371:parse_blif$40)
   37: \n171 (via $auto$blifparse.cc:371:parse_blif$41)
   38: \n172 (via $auto$blifparse.cc:371:parse_blif$42)
   39: \n173 (via $auto$blifparse.cc:371:parse_blif$43)
   40: \n174 (via $auto$blifparse.cc:371:parse_blif$44)
   41: \n175 (via $auto$blifparse.cc:371:parse_blif$45)
   42: \n176 (via $auto$blifparse.cc:371:parse_blif$46)
   43: \n177 (via $auto$blifparse.cc:371:parse_blif$47)
   44: \n178 (via $auto$blifparse.cc:371:parse_blif$48)
   45: \n179 (via $auto$blifparse.cc:371:parse_blif$49)
   46: \n180 (via $auto$blifparse.cc:371:parse_blif$50)
   47: \n181 (via $auto$blifparse.cc:371:parse_blif$51)
   48: \n182 (via $auto$blifparse.cc:371:parse_blif$52)
   49: \n183 (via $auto$blifparse.cc:371:parse_blif$53)
   50: \n184 (via $auto$blifparse.cc:371:parse_blif$54)
   51: \n185 (via $auto$blifparse.cc:371:parse_blif$55)
   52: \n186 (via $auto$blifparse.cc:371:parse_blif$56)
   53: \n187 (via $auto$blifparse.cc:371:parse_blif$57)
   54: \n188 (via $auto$blifparse.cc:371:parse_blif$58)
   55: \n189 (via $auto$blifparse.cc:371:parse_blif$59)
   56: \n190 (via $auto$blifparse.cc:371:parse_blif$60)
   57: \n191 (via $auto$blifparse.cc:371:parse_blif$61)
   58: \n192 (via $auto$blifparse.cc:371:parse_blif$62)
   59: \n193 (via $auto$blifparse.cc:371:parse_blif$63)
   60: \n194 (via $auto$blifparse.cc:371:parse_blif$64)
   61: \n195 (via $auto$blifparse.cc:371:parse_blif$65)
   62: \n196 (via $auto$blifparse.cc:371:parse_blif$66)
   63: \n197 (via $auto$blifparse.cc:371:parse_blif$67)
   64: \n198 (via $auto$blifparse.cc:371:parse_blif$68)
   65: \y0 (via $auto$blifparse.cc:371:parse_blif$69)

End of script. Logfile hash: 7551142600
CPU: user 0.01s system 0.00s, MEM: 15.95 MB total, 9.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 35% 2x read_liberty (0 sec), 34% 1x stat (0 sec), ...
>>> Temacle mapping succeed with area = 824.3192119598389
full_adder_64 initial mapping area = 1186.859669327736
full_adder_64 Temacle mapping area = 824.3192119598389
full_adder_64 Temacle saveArea = (1186.859669327736 - 824.3192119598389) / 1186.859669327736 = 30.546194022520634 %

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_verilog /home/flynn/workplace/CEMapping/benchmark/adder/full_adder_128.v; hierarchy -top full_adder_128; flatten; synth -top full_adder_128; aigmap; write_aiger /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_128//full_adder_128.aig;' --

1. Executing Verilog-2005 frontend: /home/flynn/workplace/CEMapping/benchmark/adder/full_adder_128.v
Parsing Verilog input from `/home/flynn/workplace/CEMapping/benchmark/adder/full_adder_128.v' to AST representation.
Generating RTLIL representation for module `\full_adder_128'.
Generating RTLIL representation for module `\fullAdder'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \full_adder_128
Used module:     \fullAdder

2.2. Analyzing design hierarchy..
Top module:  \full_adder_128
Used module:     \fullAdder
Removed 0 unused modules.
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[127].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[126].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[125].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[124].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[123].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[122].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[121].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[120].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[119].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[118].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[117].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[116].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[115].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[114].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[113].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[112].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[111].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[110].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[109].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[108].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[107].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[106].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[105].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[104].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[103].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[102].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[101].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[100].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[99].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[98].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[97].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[96].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[95].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[94].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[93].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[92].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[91].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[90].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[89].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[88].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[87].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[86].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[85].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[84].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[83].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[82].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[81].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[80].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[79].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[78].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[77].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[76].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[75].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[74].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[73].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[72].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[71].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[70].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[69].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[68].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[67].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[66].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[65].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[64].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[63].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[62].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[61].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[60].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[59].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[58].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[57].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[56].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[55].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[54].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[53].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[52].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[51].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[50].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[49].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[48].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[47].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[46].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[45].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[44].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[43].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[42].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[41].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[40].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[39].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[38].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[37].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[36].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[35].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[34].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[33].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[32].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[31].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[30].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[29].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[28].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[27].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[26].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[25].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[24].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[23].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[22].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[21].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[20].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[19].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[18].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[17].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[16].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[15].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[14].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[13].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[12].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[11].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[10].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[9].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[8].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[7].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[6].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[5].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[4].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[3].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[2].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[1].f (fullAdder).
Mapping positional arguments of cell full_adder_128.generate_N_bit_Adder[0].f (fullAdder).

3. Executing FLATTEN pass (flatten design).
Using template fullAdder for cells of type fullAdder.
<suppressed ~128 debug messages>
No more expansions possible.
Deleting now unused module fullAdder.

4. Executing SYNTH pass.

4.1. Executing HIERARCHY pass (managing design hierarchy).

4.1.1. Analyzing design hierarchy..
Top module:  \full_adder_128

4.1.2. Analyzing design hierarchy..
Top module:  \full_adder_128
Removed 0 unused modules.

4.2. Executing PROC pass (convert processes to netlists).

4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

4.2.3. Executing PROC_INIT pass (extract init attributes).

4.2.4. Executing PROC_ARST pass (detect async resets in processes).

4.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

4.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).

4.2.7. Executing PROC_DFF pass (convert process syncs to FFs).

4.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..
Removed 0 unused cells and 256 unused wires.
<suppressed ~1 debug messages>

4.5. Executing CHECK pass (checking for obvious problems).
checking module full_adder_128..
found and reported 0 problems.

4.6. Executing OPT pass (performing simple optimizations).

4.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_128'.
Removed a total of 0 cells.

4.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_128..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_128.
Performed a total of 0 changes.

4.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_128'.
Removed a total of 0 cells.

4.6.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.6.9. Finished OPT passes. (There is nothing left to do.)

4.7. Executing WREDUCE pass (reducing word size of cells).

4.8. Executing PEEPOPT pass (run peephole optimizers).

4.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.10. Executing TECHMAP pass (map to technology primitives).

4.10.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

4.10.2. Continuing TECHMAP pass.
No more expansions possible.

4.11. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module full_adder_128:
  created 0 $alu and 0 $macc cells.

4.12. Executing SHARE pass (SAT-based resource sharing).

4.13. Executing OPT pass (performing simple optimizations).

4.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_128'.
Removed a total of 0 cells.

4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_128..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_128.
Performed a total of 0 changes.

4.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_128'.
Removed a total of 0 cells.

4.13.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.13.9. Finished OPT passes. (There is nothing left to do.)

4.14. Executing FSM pass (extract and optimize FSM).

4.14.1. Executing FSM_DETECT pass (finding FSMs in design).

4.14.2. Executing FSM_EXTRACT pass (extracting FSM from design).

4.14.3. Executing FSM_OPT pass (simple optimizations of FSMs).

4.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.14.5. Executing FSM_OPT pass (simple optimizations of FSMs).

4.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

4.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

4.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

4.15. Executing OPT pass (performing simple optimizations).

4.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_128'.
Removed a total of 0 cells.

4.15.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.15.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.15.5. Finished fast OPT passes.

4.16. Executing MEMORY pass.

4.16.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

4.16.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.16.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

4.16.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.16.5. Executing MEMORY_COLLECT pass (generating $mem cells).

4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.18. Executing OPT pass (performing simple optimizations).

4.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_128'.
Removed a total of 0 cells.

4.18.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.18.5. Finished fast OPT passes.

4.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

4.20. Executing OPT pass (performing simple optimizations).

4.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_128'.
Removed a total of 0 cells.

4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_128..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_128.
Performed a total of 0 changes.

4.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_128'.
Removed a total of 0 cells.

4.20.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.20.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.20.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.20.9. Finished OPT passes. (There is nothing left to do.)

4.21. Executing TECHMAP pass (map to technology primitives).

4.21.1. Executing Verilog-2005 frontend: <techmap.v>
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

4.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $xor.
No more expansions possible.
<suppressed ~896 debug messages>

4.22. Executing OPT pass (performing simple optimizations).

4.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_128'.
Removed a total of 0 cells.

4.22.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..

4.22.5. Finished fast OPT passes.

4.23. Executing ABC pass (technology mapping using ABC).

4.23.1. Extracting gate netlist of module `\full_adder_128' to `<abc-temp-dir>/input.blif'..
Extracted 896 gates and 1153 wires to a netlist network with 257 inputs and 129 outputs.

4.23.1.1. Executing ABC.
Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 17 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + retime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

4.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        2
ABC RESULTS:            ANDNOT cells:      126
ABC RESULTS:              AOI3 cells:      126
ABC RESULTS:              NAND cells:        1
ABC RESULTS:               NOR cells:      125
ABC RESULTS:               NOT cells:      252
ABC RESULTS:              OAI3 cells:        2
ABC RESULTS:                OR cells:        1
ABC RESULTS:             ORNOT cells:        1
ABC RESULTS:              XNOR cells:      126
ABC RESULTS:               XOR cells:      130
ABC RESULTS:        internal signals:      767
ABC RESULTS:           input signals:      257
ABC RESULTS:          output signals:      129
Removing temp directory.

4.24. Executing OPT pass (performing simple optimizations).

4.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_128.

4.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_128'.
Removed a total of 0 cells.

4.24.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_128..
Removed 0 unused cells and 1026 unused wires.
<suppressed ~1 debug messages>

4.24.5. Finished fast OPT passes.

4.25. Executing HIERARCHY pass (managing design hierarchy).

4.25.1. Analyzing design hierarchy..
Top module:  \full_adder_128

4.25.2. Analyzing design hierarchy..
Top module:  \full_adder_128
Removed 0 unused modules.

4.26. Printing statistics.

=== full_adder_128 ===

   Number of wires:               1409
   Number of wire bits:           1918
   Number of public wires:         646
   Number of public wire bits:    1155
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                892
     $_ANDNOT_                     126
     $_AND_                          2
     $_AOI3_                       126
     $_NAND_                         1
     $_NOR_                        125
     $_NOT_                        252
     $_OAI3_                         2
     $_ORNOT_                        1
     $_OR_                           1
     $_XNOR_                       126
     $_XOR_                        130

4.27. Executing CHECK pass (checking for obvious problems).
checking module full_adder_128..
found and reported 0 problems.

5. Executing AIGMAP pass (map logic to AIG).
Module full_adder_128: replaced 638 cells with 3070 new cells, skipped 254 cells.
  replaced 9 cell types:
       1 $_NAND_
       1 $_OR_
     125 $_NOR_
     130 $_XOR_
     126 $_XNOR_
     126 $_ANDNOT_
       1 $_ORNOT_
     126 $_AOI3_
       2 $_OAI3_
  not replaced 2 cell types:
     252 $_NOT_
       2 $_AND_

6. Executing AIGER backend.

End of script. Logfile hash: e91cc6a92a
CPU: user 1.44s system 0.01s, MEM: 23.38 MB total, 17.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 27% 13x opt_clean (0 sec), 15% 7x opt (0 sec), ...
>>> aig writing succeed!
[i] processing /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_128//full_adder_128.aig
resyn runtime: 0
[i] area: 2373.250038743019, gates: 768, depth: 193
mapping runtime: 0

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib stdCellLib/gscl45nm/gscl45nm.lib; read_verilog /tmp/FZYKLPBX77.v; write_blif -impltf /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_128//full_adder_128_init.blif;' --

1. Executing Liberty frontend.
Imported 32 cell types from liberty file.

2. Executing Verilog-2005 frontend: /tmp/FZYKLPBX77.v
Parsing Verilog input from `/tmp/FZYKLPBX77.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

3. Executing BLIF backend.

End of script. Logfile hash: 0f6f4d5b9c
CPU: user 0.07s system 0.00s, MEM: 22.02 MB total, 15.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 83% 2x read_verilog (0 sec), 9% 2x write_blif (0 sec), ...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib stdCellLib/gscl45nm/gscl45nm.lib; read_blif /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_128//full_adder_128_init.blif; stat -liberty stdCellLib/gscl45nm/gscl45nm.lib; ltp;' --

1. Executing Liberty frontend.
Imported 32 cell types from liberty file.

2. Executing BLIF frontend.

3. Printing statistics.

=== top ===

   Number of wires:               1025
   Number of wire bits:           1025
   Number of public wires:        1025
   Number of public wire bits:    1025
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                768
     AND2X2                          1
     AOI21X1                        96
     INVX1                         128
     NAND2X1                        63
     NAND3X1                        31
     NOR2X1                         34
     NOR3X1                         32
     OAI21X1                        95
     OR2X2                          32
     XNOR2X1                       252
     XOR2X1                          4

   Chip area for module '\top': 2373.250100

4. Executing LTP pass (find longest path).

Longest topological path in top (length=193):
    0: \x0
    1: \n387 (via $auto$blifparse.cc:371:parse_blif$65)
    2: \n391 (via $auto$blifparse.cc:371:parse_blif$68)
    3: \n392 (via $auto$blifparse.cc:371:parse_blif$70)
    4: \n393 (via $auto$blifparse.cc:371:parse_blif$71)
    5: \n397 (via $auto$blifparse.cc:371:parse_blif$74)
    6: \n398 (via $auto$blifparse.cc:371:parse_blif$77)
    7: \n399 (via $auto$blifparse.cc:371:parse_blif$78)
    8: \n403 (via $auto$blifparse.cc:371:parse_blif$80)
    9: \n404 (via $auto$blifparse.cc:371:parse_blif$82)
   10: \n405 (via $auto$blifparse.cc:371:parse_blif$83)
   11: \n409 (via $auto$blifparse.cc:371:parse_blif$86)
   12: \n410 (via $auto$blifparse.cc:371:parse_blif$89)
   13: \n411 (via $auto$blifparse.cc:371:parse_blif$90)
   14: \n415 (via $auto$blifparse.cc:371:parse_blif$92)
   15: \n416 (via $auto$blifparse.cc:371:parse_blif$94)
   16: \n417 (via $auto$blifparse.cc:371:parse_blif$95)
   17: \n421 (via $auto$blifparse.cc:371:parse_blif$98)
   18: \n422 (via $auto$blifparse.cc:371:parse_blif$101)
   19: \n423 (via $auto$blifparse.cc:371:parse_blif$102)
   20: \n427 (via $auto$blifparse.cc:371:parse_blif$104)
   21: \n428 (via $auto$blifparse.cc:371:parse_blif$106)
   22: \n429 (via $auto$blifparse.cc:371:parse_blif$107)
   23: \n433 (via $auto$blifparse.cc:371:parse_blif$110)
   24: \n434 (via $auto$blifparse.cc:371:parse_blif$113)
   25: \n435 (via $auto$blifparse.cc:371:parse_blif$114)
   26: \n439 (via $auto$blifparse.cc:371:parse_blif$116)
   27: \n440 (via $auto$blifparse.cc:371:parse_blif$118)
   28: \n441 (via $auto$blifparse.cc:371:parse_blif$119)
   29: \n445 (via $auto$blifparse.cc:371:parse_blif$122)
   30: \n446 (via $auto$blifparse.cc:371:parse_blif$125)
   31: \n447 (via $auto$blifparse.cc:371:parse_blif$126)
   32: \n451 (via $auto$blifparse.cc:371:parse_blif$128)
   33: \n452 (via $auto$blifparse.cc:371:parse_blif$130)
   34: \n453 (via $auto$blifparse.cc:371:parse_blif$131)
   35: \n457 (via $auto$blifparse.cc:371:parse_blif$134)
   36: \n458 (via $auto$blifparse.cc:371:parse_blif$137)
   37: \n459 (via $auto$blifparse.cc:371:parse_blif$138)
   38: \n463 (via $auto$blifparse.cc:371:parse_blif$140)
   39: \n464 (via $auto$blifparse.cc:371:parse_blif$142)
   40: \n465 (via $auto$blifparse.cc:371:parse_blif$143)
   41: \n469 (via $auto$blifparse.cc:371:parse_blif$146)
   42: \n470 (via $auto$blifparse.cc:371:parse_blif$149)
   43: \n471 (via $auto$blifparse.cc:371:parse_blif$150)
   44: \n475 (via $auto$blifparse.cc:371:parse_blif$152)
   45: \n476 (via $auto$blifparse.cc:371:parse_blif$154)
   46: \n477 (via $auto$blifparse.cc:371:parse_blif$155)
   47: \n481 (via $auto$blifparse.cc:371:parse_blif$158)
   48: \n482 (via $auto$blifparse.cc:371:parse_blif$161)
   49: \n483 (via $auto$blifparse.cc:371:parse_blif$162)
   50: \n487 (via $auto$blifparse.cc:371:parse_blif$164)
   51: \n488 (via $auto$blifparse.cc:371:parse_blif$166)
   52: \n489 (via $auto$blifparse.cc:371:parse_blif$167)
   53: \n493 (via $auto$blifparse.cc:371:parse_blif$170)
   54: \n494 (via $auto$blifparse.cc:371:parse_blif$173)
   55: \n495 (via $auto$blifparse.cc:371:parse_blif$174)
   56: \n499 (via $auto$blifparse.cc:371:parse_blif$176)
   57: \n500 (via $auto$blifparse.cc:371:parse_blif$178)
   58: \n501 (via $auto$blifparse.cc:371:parse_blif$179)
   59: \n505 (via $auto$blifparse.cc:371:parse_blif$182)
   60: \n506 (via $auto$blifparse.cc:371:parse_blif$185)
   61: \n507 (via $auto$blifparse.cc:371:parse_blif$186)
   62: \n511 (via $auto$blifparse.cc:371:parse_blif$188)
   63: \n512 (via $auto$blifparse.cc:371:parse_blif$190)
   64: \n513 (via $auto$blifparse.cc:371:parse_blif$191)
   65: \n517 (via $auto$blifparse.cc:371:parse_blif$194)
   66: \n518 (via $auto$blifparse.cc:371:parse_blif$197)
   67: \n519 (via $auto$blifparse.cc:371:parse_blif$198)
   68: \n523 (via $auto$blifparse.cc:371:parse_blif$200)
   69: \n524 (via $auto$blifparse.cc:371:parse_blif$202)
   70: \n525 (via $auto$blifparse.cc:371:parse_blif$203)
   71: \n529 (via $auto$blifparse.cc:371:parse_blif$206)
   72: \n530 (via $auto$blifparse.cc:371:parse_blif$209)
   73: \n531 (via $auto$blifparse.cc:371:parse_blif$210)
   74: \n535 (via $auto$blifparse.cc:371:parse_blif$212)
   75: \n536 (via $auto$blifparse.cc:371:parse_blif$214)
   76: \n537 (via $auto$blifparse.cc:371:parse_blif$215)
   77: \n541 (via $auto$blifparse.cc:371:parse_blif$218)
   78: \n542 (via $auto$blifparse.cc:371:parse_blif$221)
   79: \n543 (via $auto$blifparse.cc:371:parse_blif$222)
   80: \n547 (via $auto$blifparse.cc:371:parse_blif$224)
   81: \n548 (via $auto$blifparse.cc:371:parse_blif$226)
   82: \n549 (via $auto$blifparse.cc:371:parse_blif$227)
   83: \n553 (via $auto$blifparse.cc:371:parse_blif$230)
   84: \n554 (via $auto$blifparse.cc:371:parse_blif$233)
   85: \n555 (via $auto$blifparse.cc:371:parse_blif$234)
   86: \n559 (via $auto$blifparse.cc:371:parse_blif$236)
   87: \n560 (via $auto$blifparse.cc:371:parse_blif$238)
   88: \n561 (via $auto$blifparse.cc:371:parse_blif$239)
   89: \n565 (via $auto$blifparse.cc:371:parse_blif$242)
   90: \n566 (via $auto$blifparse.cc:371:parse_blif$245)
   91: \n567 (via $auto$blifparse.cc:371:parse_blif$246)
   92: \n571 (via $auto$blifparse.cc:371:parse_blif$248)
   93: \n572 (via $auto$blifparse.cc:371:parse_blif$250)
   94: \n573 (via $auto$blifparse.cc:371:parse_blif$251)
   95: \n577 (via $auto$blifparse.cc:371:parse_blif$254)
   96: \n578 (via $auto$blifparse.cc:371:parse_blif$257)
   97: \n579 (via $auto$blifparse.cc:371:parse_blif$258)
   98: \n583 (via $auto$blifparse.cc:371:parse_blif$260)
   99: \n584 (via $auto$blifparse.cc:371:parse_blif$262)
  100: \n585 (via $auto$blifparse.cc:371:parse_blif$263)
  101: \n589 (via $auto$blifparse.cc:371:parse_blif$266)
  102: \n590 (via $auto$blifparse.cc:371:parse_blif$269)
  103: \n591 (via $auto$blifparse.cc:371:parse_blif$270)
  104: \n595 (via $auto$blifparse.cc:371:parse_blif$272)
  105: \n596 (via $auto$blifparse.cc:371:parse_blif$274)
  106: \n597 (via $auto$blifparse.cc:371:parse_blif$275)
  107: \n601 (via $auto$blifparse.cc:371:parse_blif$278)
  108: \n602 (via $auto$blifparse.cc:371:parse_blif$281)
  109: \n603 (via $auto$blifparse.cc:371:parse_blif$282)
  110: \n607 (via $auto$blifparse.cc:371:parse_blif$284)
  111: \n608 (via $auto$blifparse.cc:371:parse_blif$286)
  112: \n609 (via $auto$blifparse.cc:371:parse_blif$287)
  113: \n613 (via $auto$blifparse.cc:371:parse_blif$290)
  114: \n614 (via $auto$blifparse.cc:371:parse_blif$293)
  115: \n615 (via $auto$blifparse.cc:371:parse_blif$294)
  116: \n619 (via $auto$blifparse.cc:371:parse_blif$296)
  117: \n620 (via $auto$blifparse.cc:371:parse_blif$298)
  118: \n621 (via $auto$blifparse.cc:371:parse_blif$299)
  119: \n625 (via $auto$blifparse.cc:371:parse_blif$302)
  120: \n626 (via $auto$blifparse.cc:371:parse_blif$305)
  121: \n627 (via $auto$blifparse.cc:371:parse_blif$306)
  122: \n631 (via $auto$blifparse.cc:371:parse_blif$308)
  123: \n632 (via $auto$blifparse.cc:371:parse_blif$310)
  124: \n633 (via $auto$blifparse.cc:371:parse_blif$311)
  125: \n637 (via $auto$blifparse.cc:371:parse_blif$314)
  126: \n638 (via $auto$blifparse.cc:371:parse_blif$317)
  127: \n639 (via $auto$blifparse.cc:371:parse_blif$318)
  128: \n643 (via $auto$blifparse.cc:371:parse_blif$320)
  129: \n644 (via $auto$blifparse.cc:371:parse_blif$322)
  130: \n645 (via $auto$blifparse.cc:371:parse_blif$323)
  131: \n649 (via $auto$blifparse.cc:371:parse_blif$326)
  132: \n650 (via $auto$blifparse.cc:371:parse_blif$329)
  133: \n651 (via $auto$blifparse.cc:371:parse_blif$330)
  134: \n655 (via $auto$blifparse.cc:371:parse_blif$332)
  135: \n656 (via $auto$blifparse.cc:371:parse_blif$334)
  136: \n657 (via $auto$blifparse.cc:371:parse_blif$335)
  137: \n661 (via $auto$blifparse.cc:371:parse_blif$338)
  138: \n662 (via $auto$blifparse.cc:371:parse_blif$341)
  139: \n663 (via $auto$blifparse.cc:371:parse_blif$342)
  140: \n667 (via $auto$blifparse.cc:371:parse_blif$344)
  141: \n668 (via $auto$blifparse.cc:371:parse_blif$346)
  142: \n669 (via $auto$blifparse.cc:371:parse_blif$347)
  143: \n673 (via $auto$blifparse.cc:371:parse_blif$350)
  144: \n674 (via $auto$blifparse.cc:371:parse_blif$353)
  145: \n675 (via $auto$blifparse.cc:371:parse_blif$354)
  146: \n679 (via $auto$blifparse.cc:371:parse_blif$356)
  147: \n680 (via $auto$blifparse.cc:371:parse_blif$358)
  148: \n681 (via $auto$blifparse.cc:371:parse_blif$359)
  149: \n685 (via $auto$blifparse.cc:371:parse_blif$362)
  150: \n686 (via $auto$blifparse.cc:371:parse_blif$365)
  151: \n687 (via $auto$blifparse.cc:371:parse_blif$366)
  152: \n691 (via $auto$blifparse.cc:371:parse_blif$368)
  153: \n692 (via $auto$blifparse.cc:371:parse_blif$370)
  154: \n693 (via $auto$blifparse.cc:371:parse_blif$371)
  155: \n697 (via $auto$blifparse.cc:371:parse_blif$374)
  156: \n698 (via $auto$blifparse.cc:371:parse_blif$377)
  157: \n699 (via $auto$blifparse.cc:371:parse_blif$378)
  158: \n703 (via $auto$blifparse.cc:371:parse_blif$380)
  159: \n704 (via $auto$blifparse.cc:371:parse_blif$382)
  160: \n705 (via $auto$blifparse.cc:371:parse_blif$383)
  161: \n709 (via $auto$blifparse.cc:371:parse_blif$386)
  162: \n710 (via $auto$blifparse.cc:371:parse_blif$389)
  163: \n711 (via $auto$blifparse.cc:371:parse_blif$390)
  164: \n715 (via $auto$blifparse.cc:371:parse_blif$392)
  165: \n716 (via $auto$blifparse.cc:371:parse_blif$394)
  166: \n717 (via $auto$blifparse.cc:371:parse_blif$395)
  167: \n721 (via $auto$blifparse.cc:371:parse_blif$398)
  168: \n722 (via $auto$blifparse.cc:371:parse_blif$401)
  169: \n723 (via $auto$blifparse.cc:371:parse_blif$402)
  170: \n727 (via $auto$blifparse.cc:371:parse_blif$404)
  171: \n728 (via $auto$blifparse.cc:371:parse_blif$406)
  172: \n729 (via $auto$blifparse.cc:371:parse_blif$407)
  173: \n733 (via $auto$blifparse.cc:371:parse_blif$410)
  174: \n734 (via $auto$blifparse.cc:371:parse_blif$413)
  175: \n735 (via $auto$blifparse.cc:371:parse_blif$414)
  176: \n739 (via $auto$blifparse.cc:371:parse_blif$416)
  177: \n740 (via $auto$blifparse.cc:371:parse_blif$418)
  178: \n741 (via $auto$blifparse.cc:371:parse_blif$419)
  179: \n745 (via $auto$blifparse.cc:371:parse_blif$422)
  180: \n746 (via $auto$blifparse.cc:371:parse_blif$425)
  181: \n747 (via $auto$blifparse.cc:371:parse_blif$426)
  182: \n751 (via $auto$blifparse.cc:371:parse_blif$428)
  183: \n752 (via $auto$blifparse.cc:371:parse_blif$430)
  184: \n753 (via $auto$blifparse.cc:371:parse_blif$431)
  185: \n757 (via $auto$blifparse.cc:371:parse_blif$434)
  186: \n758 (via $auto$blifparse.cc:371:parse_blif$437)
  187: \n759 (via $auto$blifparse.cc:371:parse_blif$438)
  188: \n763 (via $auto$blifparse.cc:371:parse_blif$440)
  189: \n764 (via $auto$blifparse.cc:371:parse_blif$442)
  190: \n766 (via $auto$blifparse.cc:371:parse_blif$443)
  191: \n767 (via $auto$blifparse.cc:371:parse_blif$445)
  192: \n769 (via $auto$blifparse.cc:371:parse_blif$446)
  193: \y0 (via $auto$blifparse.cc:371:parse_blif$449)

End of script. Logfile hash: 26a3258638
CPU: user 0.01s system 0.01s, MEM: 17.24 MB total, 10.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 30% 1x stat (0 sec), 27% 2x read_liberty (0 sec), ...
>>> initial mapping succeed with area = 2373.250038743019
[i] processing /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_128//full_adder_128.aig
resyn runtime: 0
[i] area: 1643.5192241668701, gates: 261, depth: 129
mapping runtime: 0

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; read_verilog /tmp/Y92O6GL8F1.v; write_blif -impltf /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_128//full_adder_128_temacle.blif;' --

1. Executing Liberty frontend.
Imported 16 cell types from liberty file.

2. Executing Verilog-2005 frontend: /tmp/Y92O6GL8F1.v
Parsing Verilog input from `/tmp/Y92O6GL8F1.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

3. Executing BLIF backend.

End of script. Logfile hash: dda5569177
CPU: user 0.03s system 0.00s, MEM: 18.27 MB total, 11.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 82% 2x read_verilog (0 sec), 10% 2x write_blif (0 sec), ...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; read_blif /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_128//full_adder_128_temacle.blif; stat -liberty outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; ltp;' --

1. Executing Liberty frontend.
Imported 16 cell types from liberty file.

2. Executing BLIF frontend.

3. Printing statistics.

=== top ===

   Number of wires:                518
   Number of wire bits:            518
   Number of public wires:         518
   Number of public wire bits:     518
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                261
     ADDER_G2_0_605                128
     ADDER_G3_69_70_420            127
     AOI21X1                         2
     INVX1                           4

   Chip area for module '\top': 1643.519200

4. Executing LTP pass (find longest path).

Longest topological path in top (length=129):
    0: \x0
    1: \n259 (via $auto$blifparse.cc:371:parse_blif$3)
    2: \n264 (via $auto$blifparse.cc:371:parse_blif$6)
    3: \n265 (via $auto$blifparse.cc:371:parse_blif$7)
    4: \n266 (via $auto$blifparse.cc:371:parse_blif$8)
    5: \n267 (via $auto$blifparse.cc:371:parse_blif$9)
    6: \n268 (via $auto$blifparse.cc:371:parse_blif$10)
    7: \n269 (via $auto$blifparse.cc:371:parse_blif$11)
    8: \n270 (via $auto$blifparse.cc:371:parse_blif$12)
    9: \n271 (via $auto$blifparse.cc:371:parse_blif$13)
   10: \n272 (via $auto$blifparse.cc:371:parse_blif$14)
   11: \n273 (via $auto$blifparse.cc:371:parse_blif$15)
   12: \n274 (via $auto$blifparse.cc:371:parse_blif$16)
   13: \n275 (via $auto$blifparse.cc:371:parse_blif$17)
   14: \n276 (via $auto$blifparse.cc:371:parse_blif$18)
   15: \n277 (via $auto$blifparse.cc:371:parse_blif$19)
   16: \n278 (via $auto$blifparse.cc:371:parse_blif$20)
   17: \n279 (via $auto$blifparse.cc:371:parse_blif$21)
   18: \n280 (via $auto$blifparse.cc:371:parse_blif$22)
   19: \n281 (via $auto$blifparse.cc:371:parse_blif$23)
   20: \n282 (via $auto$blifparse.cc:371:parse_blif$24)
   21: \n283 (via $auto$blifparse.cc:371:parse_blif$25)
   22: \n284 (via $auto$blifparse.cc:371:parse_blif$26)
   23: \n285 (via $auto$blifparse.cc:371:parse_blif$27)
   24: \n286 (via $auto$blifparse.cc:371:parse_blif$28)
   25: \n287 (via $auto$blifparse.cc:371:parse_blif$29)
   26: \n288 (via $auto$blifparse.cc:371:parse_blif$30)
   27: \n289 (via $auto$blifparse.cc:371:parse_blif$31)
   28: \n290 (via $auto$blifparse.cc:371:parse_blif$32)
   29: \n291 (via $auto$blifparse.cc:371:parse_blif$33)
   30: \n292 (via $auto$blifparse.cc:371:parse_blif$34)
   31: \n293 (via $auto$blifparse.cc:371:parse_blif$35)
   32: \n294 (via $auto$blifparse.cc:371:parse_blif$36)
   33: \n295 (via $auto$blifparse.cc:371:parse_blif$37)
   34: \n296 (via $auto$blifparse.cc:371:parse_blif$38)
   35: \n297 (via $auto$blifparse.cc:371:parse_blif$39)
   36: \n298 (via $auto$blifparse.cc:371:parse_blif$40)
   37: \n299 (via $auto$blifparse.cc:371:parse_blif$41)
   38: \n300 (via $auto$blifparse.cc:371:parse_blif$42)
   39: \n301 (via $auto$blifparse.cc:371:parse_blif$43)
   40: \n302 (via $auto$blifparse.cc:371:parse_blif$44)
   41: \n303 (via $auto$blifparse.cc:371:parse_blif$45)
   42: \n304 (via $auto$blifparse.cc:371:parse_blif$46)
   43: \n305 (via $auto$blifparse.cc:371:parse_blif$47)
   44: \n306 (via $auto$blifparse.cc:371:parse_blif$48)
   45: \n307 (via $auto$blifparse.cc:371:parse_blif$49)
   46: \n308 (via $auto$blifparse.cc:371:parse_blif$50)
   47: \n309 (via $auto$blifparse.cc:371:parse_blif$51)
   48: \n310 (via $auto$blifparse.cc:371:parse_blif$52)
   49: \n311 (via $auto$blifparse.cc:371:parse_blif$53)
   50: \n312 (via $auto$blifparse.cc:371:parse_blif$54)
   51: \n313 (via $auto$blifparse.cc:371:parse_blif$55)
   52: \n314 (via $auto$blifparse.cc:371:parse_blif$56)
   53: \n315 (via $auto$blifparse.cc:371:parse_blif$57)
   54: \n316 (via $auto$blifparse.cc:371:parse_blif$58)
   55: \n317 (via $auto$blifparse.cc:371:parse_blif$59)
   56: \n318 (via $auto$blifparse.cc:371:parse_blif$60)
   57: \n319 (via $auto$blifparse.cc:371:parse_blif$61)
   58: \n320 (via $auto$blifparse.cc:371:parse_blif$62)
   59: \n321 (via $auto$blifparse.cc:371:parse_blif$63)
   60: \n322 (via $auto$blifparse.cc:371:parse_blif$64)
   61: \n323 (via $auto$blifparse.cc:371:parse_blif$65)
   62: \n324 (via $auto$blifparse.cc:371:parse_blif$66)
   63: \n325 (via $auto$blifparse.cc:371:parse_blif$67)
   64: \n326 (via $auto$blifparse.cc:371:parse_blif$68)
   65: \n327 (via $auto$blifparse.cc:371:parse_blif$69)
   66: \n328 (via $auto$blifparse.cc:371:parse_blif$70)
   67: \n329 (via $auto$blifparse.cc:371:parse_blif$71)
   68: \n330 (via $auto$blifparse.cc:371:parse_blif$72)
   69: \n331 (via $auto$blifparse.cc:371:parse_blif$73)
   70: \n332 (via $auto$blifparse.cc:371:parse_blif$74)
   71: \n333 (via $auto$blifparse.cc:371:parse_blif$75)
   72: \n334 (via $auto$blifparse.cc:371:parse_blif$76)
   73: \n335 (via $auto$blifparse.cc:371:parse_blif$77)
   74: \n336 (via $auto$blifparse.cc:371:parse_blif$78)
   75: \n337 (via $auto$blifparse.cc:371:parse_blif$79)
   76: \n338 (via $auto$blifparse.cc:371:parse_blif$80)
   77: \n339 (via $auto$blifparse.cc:371:parse_blif$81)
   78: \n340 (via $auto$blifparse.cc:371:parse_blif$82)
   79: \n341 (via $auto$blifparse.cc:371:parse_blif$83)
   80: \n342 (via $auto$blifparse.cc:371:parse_blif$84)
   81: \n343 (via $auto$blifparse.cc:371:parse_blif$85)
   82: \n344 (via $auto$blifparse.cc:371:parse_blif$86)
   83: \n345 (via $auto$blifparse.cc:371:parse_blif$87)
   84: \n346 (via $auto$blifparse.cc:371:parse_blif$88)
   85: \n347 (via $auto$blifparse.cc:371:parse_blif$89)
   86: \n348 (via $auto$blifparse.cc:371:parse_blif$90)
   87: \n349 (via $auto$blifparse.cc:371:parse_blif$91)
   88: \n350 (via $auto$blifparse.cc:371:parse_blif$92)
   89: \n351 (via $auto$blifparse.cc:371:parse_blif$93)
   90: \n352 (via $auto$blifparse.cc:371:parse_blif$94)
   91: \n353 (via $auto$blifparse.cc:371:parse_blif$95)
   92: \n354 (via $auto$blifparse.cc:371:parse_blif$96)
   93: \n355 (via $auto$blifparse.cc:371:parse_blif$97)
   94: \n356 (via $auto$blifparse.cc:371:parse_blif$98)
   95: \n357 (via $auto$blifparse.cc:371:parse_blif$99)
   96: \n358 (via $auto$blifparse.cc:371:parse_blif$100)
   97: \n359 (via $auto$blifparse.cc:371:parse_blif$101)
   98: \n360 (via $auto$blifparse.cc:371:parse_blif$102)
   99: \n361 (via $auto$blifparse.cc:371:parse_blif$103)
  100: \n362 (via $auto$blifparse.cc:371:parse_blif$104)
  101: \n363 (via $auto$blifparse.cc:371:parse_blif$105)
  102: \n364 (via $auto$blifparse.cc:371:parse_blif$106)
  103: \n365 (via $auto$blifparse.cc:371:parse_blif$107)
  104: \n366 (via $auto$blifparse.cc:371:parse_blif$108)
  105: \n367 (via $auto$blifparse.cc:371:parse_blif$109)
  106: \n368 (via $auto$blifparse.cc:371:parse_blif$110)
  107: \n369 (via $auto$blifparse.cc:371:parse_blif$111)
  108: \n370 (via $auto$blifparse.cc:371:parse_blif$112)
  109: \n371 (via $auto$blifparse.cc:371:parse_blif$113)
  110: \n372 (via $auto$blifparse.cc:371:parse_blif$114)
  111: \n373 (via $auto$blifparse.cc:371:parse_blif$115)
  112: \n374 (via $auto$blifparse.cc:371:parse_blif$116)
  113: \n375 (via $auto$blifparse.cc:371:parse_blif$117)
  114: \n376 (via $auto$blifparse.cc:371:parse_blif$118)
  115: \n377 (via $auto$blifparse.cc:371:parse_blif$119)
  116: \n378 (via $auto$blifparse.cc:371:parse_blif$120)
  117: \n379 (via $auto$blifparse.cc:371:parse_blif$121)
  118: \n380 (via $auto$blifparse.cc:371:parse_blif$122)
  119: \n381 (via $auto$blifparse.cc:371:parse_blif$123)
  120: \n382 (via $auto$blifparse.cc:371:parse_blif$124)
  121: \n383 (via $auto$blifparse.cc:371:parse_blif$125)
  122: \n384 (via $auto$blifparse.cc:371:parse_blif$126)
  123: \n385 (via $auto$blifparse.cc:371:parse_blif$127)
  124: \n386 (via $auto$blifparse.cc:371:parse_blif$128)
  125: \n387 (via $auto$blifparse.cc:371:parse_blif$129)
  126: \n388 (via $auto$blifparse.cc:371:parse_blif$130)
  127: \n389 (via $auto$blifparse.cc:371:parse_blif$131)
  128: \n390 (via $auto$blifparse.cc:371:parse_blif$132)
  129: \y0 (via $auto$blifparse.cc:371:parse_blif$133)

End of script. Logfile hash: f6e4b52ff4
CPU: user 0.01s system 0.00s, MEM: 16.21 MB total, 9.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 28% 1x stat (0 sec), 27% 2x read_liberty (0 sec), ...
>>> Temacle mapping succeed with area = 1643.5192241668701
full_adder_128 initial mapping area = 2373.250038743019
full_adder_128 Temacle mapping area = 1643.5192241668701
full_adder_128 Temacle saveArea = (2373.250038743019 - 1643.5192241668701) / 2373.250038743019 = 30.748164022474743 %

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_verilog /home/flynn/workplace/CEMapping/benchmark/adder/full_adder_256.v; hierarchy -top full_adder_256; flatten; synth -top full_adder_256; aigmap; write_aiger /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_256//full_adder_256.aig;' --

1. Executing Verilog-2005 frontend: /home/flynn/workplace/CEMapping/benchmark/adder/full_adder_256.v
Parsing Verilog input from `/home/flynn/workplace/CEMapping/benchmark/adder/full_adder_256.v' to AST representation.
Generating RTLIL representation for module `\full_adder_256'.
Generating RTLIL representation for module `\fullAdder'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \full_adder_256
Used module:     \fullAdder

2.2. Analyzing design hierarchy..
Top module:  \full_adder_256
Used module:     \fullAdder
Removed 0 unused modules.
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[255].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[254].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[253].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[252].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[251].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[250].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[249].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[248].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[247].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[246].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[245].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[244].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[243].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[242].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[241].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[240].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[239].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[238].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[237].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[236].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[235].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[234].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[233].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[232].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[231].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[230].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[229].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[228].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[227].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[226].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[225].f (fullAdder).
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Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[223].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[222].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[221].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[220].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[219].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[218].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[217].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[216].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[215].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[214].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[213].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[212].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[211].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[210].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[209].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[208].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[207].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[206].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[205].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[204].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[203].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[202].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[201].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[200].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[199].f (fullAdder).
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Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[197].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[196].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[195].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[194].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[193].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[192].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[191].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[190].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[189].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[188].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[187].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[186].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[185].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[184].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[183].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[182].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[181].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[180].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[179].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[178].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[177].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[176].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[175].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[174].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[173].f (fullAdder).
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Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[171].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[170].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[169].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[168].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[167].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[166].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[165].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[164].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[163].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[162].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[161].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[160].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[159].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[158].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[157].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[156].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[155].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[154].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[153].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[152].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[151].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[150].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[149].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[148].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[147].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[146].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[145].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[144].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[143].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[142].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[141].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[140].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[139].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[138].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[137].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[136].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[135].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[134].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[133].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[132].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[131].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[130].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[129].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[128].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[127].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[126].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[125].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[124].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[123].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[122].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[121].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[120].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[119].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[118].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[117].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[116].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[115].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[114].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[113].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[112].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[111].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[110].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[109].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[108].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[107].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[106].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[105].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[104].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[103].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[102].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[101].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[100].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[99].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[98].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[97].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[96].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[95].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[94].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[93].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[92].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[91].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[90].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[89].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[88].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[87].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[86].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[85].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[84].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[83].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[82].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[81].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[80].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[79].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[78].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[77].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[76].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[75].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[74].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[73].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[72].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[71].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[70].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[69].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[68].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[67].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[66].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[65].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[64].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[63].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[62].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[61].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[60].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[59].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[58].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[57].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[56].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[55].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[54].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[53].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[52].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[51].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[50].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[49].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[48].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[47].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[46].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[45].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[44].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[43].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[42].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[41].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[40].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[39].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[38].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[37].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[36].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[35].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[34].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[33].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[32].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[31].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[30].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[29].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[28].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[27].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[26].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[25].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[24].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[23].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[22].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[21].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[20].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[19].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[18].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[17].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[16].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[15].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[14].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[13].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[12].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[11].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[10].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[9].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[8].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[7].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[6].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[5].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[4].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[3].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[2].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[1].f (fullAdder).
Mapping positional arguments of cell full_adder_256.generate_N_bit_Adder[0].f (fullAdder).

3. Executing FLATTEN pass (flatten design).
Using template fullAdder for cells of type fullAdder.
<suppressed ~256 debug messages>
No more expansions possible.
Deleting now unused module fullAdder.

4. Executing SYNTH pass.

4.1. Executing HIERARCHY pass (managing design hierarchy).

4.1.1. Analyzing design hierarchy..
Top module:  \full_adder_256

4.1.2. Analyzing design hierarchy..
Top module:  \full_adder_256
Removed 0 unused modules.

4.2. Executing PROC pass (convert processes to netlists).

4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

4.2.3. Executing PROC_INIT pass (extract init attributes).

4.2.4. Executing PROC_ARST pass (detect async resets in processes).

4.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

4.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).

4.2.7. Executing PROC_DFF pass (convert process syncs to FFs).

4.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..
Removed 0 unused cells and 512 unused wires.
<suppressed ~1 debug messages>

4.5. Executing CHECK pass (checking for obvious problems).
checking module full_adder_256..
found and reported 0 problems.

4.6. Executing OPT pass (performing simple optimizations).

4.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_256'.
Removed a total of 0 cells.

4.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_256..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_256.
Performed a total of 0 changes.

4.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_256'.
Removed a total of 0 cells.

4.6.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.6.9. Finished OPT passes. (There is nothing left to do.)

4.7. Executing WREDUCE pass (reducing word size of cells).

4.8. Executing PEEPOPT pass (run peephole optimizers).

4.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.10. Executing TECHMAP pass (map to technology primitives).

4.10.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

4.10.2. Continuing TECHMAP pass.
No more expansions possible.

4.11. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module full_adder_256:
  created 0 $alu and 0 $macc cells.

4.12. Executing SHARE pass (SAT-based resource sharing).

4.13. Executing OPT pass (performing simple optimizations).

4.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_256'.
Removed a total of 0 cells.

4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_256..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_256.
Performed a total of 0 changes.

4.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_256'.
Removed a total of 0 cells.

4.13.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.13.9. Finished OPT passes. (There is nothing left to do.)

4.14. Executing FSM pass (extract and optimize FSM).

4.14.1. Executing FSM_DETECT pass (finding FSMs in design).

4.14.2. Executing FSM_EXTRACT pass (extracting FSM from design).

4.14.3. Executing FSM_OPT pass (simple optimizations of FSMs).

4.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.14.5. Executing FSM_OPT pass (simple optimizations of FSMs).

4.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

4.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

4.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

4.15. Executing OPT pass (performing simple optimizations).

4.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_256'.
Removed a total of 0 cells.

4.15.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.15.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.15.5. Finished fast OPT passes.

4.16. Executing MEMORY pass.

4.16.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

4.16.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.16.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

4.16.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.16.5. Executing MEMORY_COLLECT pass (generating $mem cells).

4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.18. Executing OPT pass (performing simple optimizations).

4.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_256'.
Removed a total of 0 cells.

4.18.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.18.5. Finished fast OPT passes.

4.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

4.20. Executing OPT pass (performing simple optimizations).

4.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_256'.
Removed a total of 0 cells.

4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \full_adder_256..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \full_adder_256.
Performed a total of 0 changes.

4.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_256'.
Removed a total of 0 cells.

4.20.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.20.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.20.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.20.9. Finished OPT passes. (There is nothing left to do.)

4.21. Executing TECHMAP pass (map to technology primitives).

4.21.1. Executing Verilog-2005 frontend: <techmap.v>
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

4.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $xor.
No more expansions possible.
<suppressed ~1792 debug messages>

4.22. Executing OPT pass (performing simple optimizations).

4.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_256'.
Removed a total of 0 cells.

4.22.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..

4.22.5. Finished fast OPT passes.

4.23. Executing ABC pass (technology mapping using ABC).

4.23.1. Extracting gate netlist of module `\full_adder_256' to `<abc-temp-dir>/input.blif'..
Extracted 1792 gates and 2305 wires to a netlist network with 513 inputs and 257 outputs.

4.23.1.1. Executing ABC.
Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 17 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + retime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

4.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        2
ABC RESULTS:            ANDNOT cells:      254
ABC RESULTS:              AOI3 cells:      254
ABC RESULTS:              NAND cells:        1
ABC RESULTS:               NOR cells:      253
ABC RESULTS:               NOT cells:      508
ABC RESULTS:              OAI3 cells:        2
ABC RESULTS:                OR cells:        1
ABC RESULTS:             ORNOT cells:        1
ABC RESULTS:              XNOR cells:      254
ABC RESULTS:               XOR cells:      258
ABC RESULTS:        internal signals:     1535
ABC RESULTS:           input signals:      513
ABC RESULTS:          output signals:      257
Removing temp directory.

4.24. Executing OPT pass (performing simple optimizations).

4.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module full_adder_256.

4.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\full_adder_256'.
Removed a total of 0 cells.

4.24.3. Executing OPT_RMDFF pass (remove dff with constant values).

4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \full_adder_256..
Removed 0 unused cells and 2050 unused wires.
<suppressed ~1 debug messages>

4.24.5. Finished fast OPT passes.

4.25. Executing HIERARCHY pass (managing design hierarchy).

4.25.1. Analyzing design hierarchy..
Top module:  \full_adder_256

4.25.2. Analyzing design hierarchy..
Top module:  \full_adder_256
Removed 0 unused modules.

4.26. Printing statistics.

=== full_adder_256 ===

   Number of wires:               2817
   Number of wire bits:           3838
   Number of public wires:        1286
   Number of public wire bits:    2307
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               1788
     $_ANDNOT_                     254
     $_AND_                          2
     $_AOI3_                       254
     $_NAND_                         1
     $_NOR_                        253
     $_NOT_                        508
     $_OAI3_                         2
     $_ORNOT_                        1
     $_OR_                           1
     $_XNOR_                       254
     $_XOR_                        258

4.27. Executing CHECK pass (checking for obvious problems).
checking module full_adder_256..
found and reported 0 problems.

5. Executing AIGMAP pass (map logic to AIG).
Module full_adder_256: replaced 1278 cells with 6142 new cells, skipped 510 cells.
  replaced 9 cell types:
       1 $_NAND_
       1 $_OR_
     253 $_NOR_
     258 $_XOR_
     254 $_XNOR_
     254 $_ANDNOT_
       1 $_ORNOT_
     254 $_AOI3_
       2 $_OAI3_
  not replaced 2 cell types:
     508 $_NOT_
       2 $_AND_

6. Executing AIGER backend.

End of script. Logfile hash: c7c43e4eed
CPU: user 3.15s system 0.04s, MEM: 30.72 MB total, 24.36 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 28% 13x opt_clean (0 sec), 14% 7x opt (0 sec), ...
>>> aig writing succeed!
[i] processing /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_256//full_adder_256.aig
resyn runtime: 0
[i] area: 4746.0307775735855, gates: 1536, depth: 385
mapping runtime: 0

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib stdCellLib/gscl45nm/gscl45nm.lib; read_verilog /tmp/5IP1MW05L9.v; write_blif -impltf /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_256//full_adder_256_init.blif;' --

1. Executing Liberty frontend.
Imported 32 cell types from liberty file.

2. Executing Verilog-2005 frontend: /tmp/5IP1MW05L9.v
Parsing Verilog input from `/tmp/5IP1MW05L9.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

3. Executing BLIF backend.

End of script. Logfile hash: f86b2f98bc
CPU: user 0.13s system 0.02s, MEM: 28.58 MB total, 22.00 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 87% 2x read_verilog (0 sec), 8% 2x write_blif (0 sec), ...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib stdCellLib/gscl45nm/gscl45nm.lib; read_blif /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_256//full_adder_256_init.blif; stat -liberty stdCellLib/gscl45nm/gscl45nm.lib; ltp;' --

1. Executing Liberty frontend.
Imported 32 cell types from liberty file.

2. Executing BLIF frontend.

3. Printing statistics.

=== top ===

   Number of wires:               2049
   Number of wire bits:           2049
   Number of public wires:        2049
   Number of public wire bits:    2049
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               1536
     AND2X2                          1
     AOI21X1                       192
     INVX1                         256
     NAND2X1                       127
     NAND3X1                        63
     NOR2X1                         66
     NOR3X1                         64
     OAI21X1                       191
     OR2X2                          64
     XNOR2X1                       508
     XOR2X1                          4

   Chip area for module '\top': 4746.030900

4. Executing LTP pass (find longest path).

Longest topological path in top (length=385):
    0: \x0
    1: \n771 (via $auto$blifparse.cc:371:parse_blif$129)
    2: \n775 (via $auto$blifparse.cc:371:parse_blif$132)
    3: \n776 (via $auto$blifparse.cc:371:parse_blif$134)
    4: \n777 (via $auto$blifparse.cc:371:parse_blif$135)
    5: \n781 (via $auto$blifparse.cc:371:parse_blif$138)
    6: \n782 (via $auto$blifparse.cc:371:parse_blif$141)
    7: \n783 (via $auto$blifparse.cc:371:parse_blif$142)
    8: \n787 (via $auto$blifparse.cc:371:parse_blif$144)
    9: \n788 (via $auto$blifparse.cc:371:parse_blif$146)
   10: \n789 (via $auto$blifparse.cc:371:parse_blif$147)
   11: \n793 (via $auto$blifparse.cc:371:parse_blif$150)
   12: \n794 (via $auto$blifparse.cc:371:parse_blif$153)
   13: \n795 (via $auto$blifparse.cc:371:parse_blif$154)
   14: \n799 (via $auto$blifparse.cc:371:parse_blif$156)
   15: \n800 (via $auto$blifparse.cc:371:parse_blif$158)
   16: \n801 (via $auto$blifparse.cc:371:parse_blif$159)
   17: \n805 (via $auto$blifparse.cc:371:parse_blif$162)
   18: \n806 (via $auto$blifparse.cc:371:parse_blif$165)
   19: \n807 (via $auto$blifparse.cc:371:parse_blif$166)
   20: \n811 (via $auto$blifparse.cc:371:parse_blif$168)
   21: \n812 (via $auto$blifparse.cc:371:parse_blif$170)
   22: \n813 (via $auto$blifparse.cc:371:parse_blif$171)
   23: \n817 (via $auto$blifparse.cc:371:parse_blif$174)
   24: \n818 (via $auto$blifparse.cc:371:parse_blif$177)
   25: \n819 (via $auto$blifparse.cc:371:parse_blif$178)
   26: \n823 (via $auto$blifparse.cc:371:parse_blif$180)
   27: \n824 (via $auto$blifparse.cc:371:parse_blif$182)
   28: \n825 (via $auto$blifparse.cc:371:parse_blif$183)
   29: \n829 (via $auto$blifparse.cc:371:parse_blif$186)
   30: \n830 (via $auto$blifparse.cc:371:parse_blif$189)
   31: \n831 (via $auto$blifparse.cc:371:parse_blif$190)
   32: \n835 (via $auto$blifparse.cc:371:parse_blif$192)
   33: \n836 (via $auto$blifparse.cc:371:parse_blif$194)
   34: \n837 (via $auto$blifparse.cc:371:parse_blif$195)
   35: \n841 (via $auto$blifparse.cc:371:parse_blif$198)
   36: \n842 (via $auto$blifparse.cc:371:parse_blif$201)
   37: \n843 (via $auto$blifparse.cc:371:parse_blif$202)
   38: \n847 (via $auto$blifparse.cc:371:parse_blif$204)
   39: \n848 (via $auto$blifparse.cc:371:parse_blif$206)
   40: \n849 (via $auto$blifparse.cc:371:parse_blif$207)
   41: \n853 (via $auto$blifparse.cc:371:parse_blif$210)
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  317: \n1405 (via $auto$blifparse.cc:371:parse_blif$762)
  318: \n1406 (via $auto$blifparse.cc:371:parse_blif$765)
  319: \n1407 (via $auto$blifparse.cc:371:parse_blif$766)
  320: \n1411 (via $auto$blifparse.cc:371:parse_blif$768)
  321: \n1412 (via $auto$blifparse.cc:371:parse_blif$770)
  322: \n1413 (via $auto$blifparse.cc:371:parse_blif$771)
  323: \n1417 (via $auto$blifparse.cc:371:parse_blif$774)
  324: \n1418 (via $auto$blifparse.cc:371:parse_blif$777)
  325: \n1419 (via $auto$blifparse.cc:371:parse_blif$778)
  326: \n1423 (via $auto$blifparse.cc:371:parse_blif$780)
  327: \n1424 (via $auto$blifparse.cc:371:parse_blif$782)
  328: \n1425 (via $auto$blifparse.cc:371:parse_blif$783)
  329: \n1429 (via $auto$blifparse.cc:371:parse_blif$786)
  330: \n1430 (via $auto$blifparse.cc:371:parse_blif$789)
  331: \n1431 (via $auto$blifparse.cc:371:parse_blif$790)
  332: \n1435 (via $auto$blifparse.cc:371:parse_blif$792)
  333: \n1436 (via $auto$blifparse.cc:371:parse_blif$794)
  334: \n1437 (via $auto$blifparse.cc:371:parse_blif$795)
  335: \n1441 (via $auto$blifparse.cc:371:parse_blif$798)
  336: \n1442 (via $auto$blifparse.cc:371:parse_blif$801)
  337: \n1443 (via $auto$blifparse.cc:371:parse_blif$802)
  338: \n1447 (via $auto$blifparse.cc:371:parse_blif$804)
  339: \n1448 (via $auto$blifparse.cc:371:parse_blif$806)
  340: \n1449 (via $auto$blifparse.cc:371:parse_blif$807)
  341: \n1453 (via $auto$blifparse.cc:371:parse_blif$810)
  342: \n1454 (via $auto$blifparse.cc:371:parse_blif$813)
  343: \n1455 (via $auto$blifparse.cc:371:parse_blif$814)
  344: \n1459 (via $auto$blifparse.cc:371:parse_blif$816)
  345: \n1460 (via $auto$blifparse.cc:371:parse_blif$818)
  346: \n1461 (via $auto$blifparse.cc:371:parse_blif$819)
  347: \n1465 (via $auto$blifparse.cc:371:parse_blif$822)
  348: \n1466 (via $auto$blifparse.cc:371:parse_blif$825)
  349: \n1467 (via $auto$blifparse.cc:371:parse_blif$826)
  350: \n1471 (via $auto$blifparse.cc:371:parse_blif$828)
  351: \n1472 (via $auto$blifparse.cc:371:parse_blif$830)
  352: \n1473 (via $auto$blifparse.cc:371:parse_blif$831)
  353: \n1477 (via $auto$blifparse.cc:371:parse_blif$834)
  354: \n1478 (via $auto$blifparse.cc:371:parse_blif$837)
  355: \n1479 (via $auto$blifparse.cc:371:parse_blif$838)
  356: \n1483 (via $auto$blifparse.cc:371:parse_blif$840)
  357: \n1484 (via $auto$blifparse.cc:371:parse_blif$842)
  358: \n1485 (via $auto$blifparse.cc:371:parse_blif$843)
  359: \n1489 (via $auto$blifparse.cc:371:parse_blif$846)
  360: \n1490 (via $auto$blifparse.cc:371:parse_blif$849)
  361: \n1491 (via $auto$blifparse.cc:371:parse_blif$850)
  362: \n1495 (via $auto$blifparse.cc:371:parse_blif$852)
  363: \n1496 (via $auto$blifparse.cc:371:parse_blif$854)
  364: \n1497 (via $auto$blifparse.cc:371:parse_blif$855)
  365: \n1501 (via $auto$blifparse.cc:371:parse_blif$858)
  366: \n1502 (via $auto$blifparse.cc:371:parse_blif$861)
  367: \n1503 (via $auto$blifparse.cc:371:parse_blif$862)
  368: \n1507 (via $auto$blifparse.cc:371:parse_blif$864)
  369: \n1508 (via $auto$blifparse.cc:371:parse_blif$866)
  370: \n1509 (via $auto$blifparse.cc:371:parse_blif$867)
  371: \n1513 (via $auto$blifparse.cc:371:parse_blif$870)
  372: \n1514 (via $auto$blifparse.cc:371:parse_blif$873)
  373: \n1515 (via $auto$blifparse.cc:371:parse_blif$874)
  374: \n1519 (via $auto$blifparse.cc:371:parse_blif$876)
  375: \n1520 (via $auto$blifparse.cc:371:parse_blif$878)
  376: \n1521 (via $auto$blifparse.cc:371:parse_blif$879)
  377: \n1525 (via $auto$blifparse.cc:371:parse_blif$882)
  378: \n1526 (via $auto$blifparse.cc:371:parse_blif$885)
  379: \n1527 (via $auto$blifparse.cc:371:parse_blif$886)
  380: \n1531 (via $auto$blifparse.cc:371:parse_blif$888)
  381: \n1532 (via $auto$blifparse.cc:371:parse_blif$890)
  382: \n1534 (via $auto$blifparse.cc:371:parse_blif$891)
  383: \n1535 (via $auto$blifparse.cc:371:parse_blif$893)
  384: \n1537 (via $auto$blifparse.cc:371:parse_blif$894)
  385: \y0 (via $auto$blifparse.cc:371:parse_blif$897)

End of script. Logfile hash: 4a17d20ff9
CPU: user 0.03s system 0.00s, MEM: 18.18 MB total, 11.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 30% 2x read_blif (0 sec), 28% 1x ltp (0 sec), ...
>>> initial mapping succeed with area = 4746.0307775735855
[i] processing /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_256//full_adder_256.aig
resyn runtime: 0
[i] area: 3281.9192485809326, gates: 517, depth: 257
mapping runtime: 0

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; read_verilog /tmp/IBVKZLD2HM.v; write_blif -impltf /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_256//full_adder_256_temacle.blif;' --

1. Executing Liberty frontend.
Imported 16 cell types from liberty file.

2. Executing Verilog-2005 frontend: /tmp/IBVKZLD2HM.v
Parsing Verilog input from `/tmp/IBVKZLD2HM.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

3. Executing BLIF backend.

End of script. Logfile hash: fbd8234590
CPU: user 0.06s system 0.00s, MEM: 21.02 MB total, 14.50 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 86% 2x read_verilog (0 sec), 9% 2x write_blif (0 sec), ...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Running command `read_liberty -lib outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; read_blif /home/flynn/workplace/CEMapping/outputs/Astran/adder/full_adder_256//full_adder_256_temacle.blif; stat -liberty outputs/Astran/K3/adder/ADDER_G3_69_70_420.lib; ltp;' --

1. Executing Liberty frontend.
Imported 16 cell types from liberty file.

2. Executing BLIF frontend.

3. Printing statistics.

=== top ===

   Number of wires:               1030
   Number of wire bits:           1030
   Number of public wires:        1030
   Number of public wire bits:    1030
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                517
     ADDER_G2_0_605                256
     ADDER_G3_69_70_420            255
     AOI21X1                         2
     INVX1                           4

   Chip area for module '\top': 3281.919200

4. Executing LTP pass (find longest path).

Longest topological path in top (length=257):
    0: \x0
    1: \n515 (via $auto$blifparse.cc:371:parse_blif$3)
    2: \n520 (via $auto$blifparse.cc:371:parse_blif$6)
    3: \n521 (via $auto$blifparse.cc:371:parse_blif$7)
    4: \n522 (via $auto$blifparse.cc:371:parse_blif$8)
    5: \n523 (via $auto$blifparse.cc:371:parse_blif$9)
    6: \n524 (via $auto$blifparse.cc:371:parse_blif$10)
    7: \n525 (via $auto$blifparse.cc:371:parse_blif$11)
    8: \n526 (via $auto$blifparse.cc:371:parse_blif$12)
    9: \n527 (via $auto$blifparse.cc:371:parse_blif$13)
   10: \n528 (via $auto$blifparse.cc:371:parse_blif$14)
   11: \n529 (via $auto$blifparse.cc:371:parse_blif$15)
   12: \n530 (via $auto$blifparse.cc:371:parse_blif$16)
   13: \n531 (via $auto$blifparse.cc:371:parse_blif$17)
   14: \n532 (via $auto$blifparse.cc:371:parse_blif$18)
   15: \n533 (via $auto$blifparse.cc:371:parse_blif$19)
   16: \n534 (via $auto$blifparse.cc:371:parse_blif$20)
   17: \n535 (via $auto$blifparse.cc:371:parse_blif$21)
   18: \n536 (via $auto$blifparse.cc:371:parse_blif$22)
   19: \n537 (via $auto$blifparse.cc:371:parse_blif$23)
   20: \n538 (via $auto$blifparse.cc:371:parse_blif$24)
   21: \n539 (via $auto$blifparse.cc:371:parse_blif$25)
   22: \n540 (via $auto$blifparse.cc:371:parse_blif$26)
   23: \n541 (via $auto$blifparse.cc:371:parse_blif$27)
   24: \n542 (via $auto$blifparse.cc:371:parse_blif$28)
   25: \n543 (via $auto$blifparse.cc:371:parse_blif$29)
   26: \n544 (via $auto$blifparse.cc:371:parse_blif$30)
   27: \n545 (via $auto$blifparse.cc:371:parse_blif$31)
   28: \n546 (via $auto$blifparse.cc:371:parse_blif$32)
   29: \n547 (via $auto$blifparse.cc:371:parse_blif$33)
   30: \n548 (via $auto$blifparse.cc:371:parse_blif$34)
   31: \n549 (via $auto$blifparse.cc:371:parse_blif$35)
   32: \n550 (via $auto$blifparse.cc:371:parse_blif$36)
   33: \n551 (via $auto$blifparse.cc:371:parse_blif$37)
   34: \n552 (via $auto$blifparse.cc:371:parse_blif$38)
   35: \n553 (via $auto$blifparse.cc:371:parse_blif$39)
   36: \n554 (via $auto$blifparse.cc:371:parse_blif$40)
   37: \n555 (via $auto$blifparse.cc:371:parse_blif$41)
   38: \n556 (via $auto$blifparse.cc:371:parse_blif$42)
   39: \n557 (via $auto$blifparse.cc:371:parse_blif$43)
   40: \n558 (via $auto$blifparse.cc:371:parse_blif$44)
   41: \n559 (via $auto$blifparse.cc:371:parse_blif$45)
   42: \n560 (via $auto$blifparse.cc:371:parse_blif$46)
   43: \n561 (via $auto$blifparse.cc:371:parse_blif$47)
   44: \n562 (via $auto$blifparse.cc:371:parse_blif$48)
   45: \n563 (via $auto$blifparse.cc:371:parse_blif$49)
   46: \n564 (via $auto$blifparse.cc:371:parse_blif$50)
   47: \n565 (via $auto$blifparse.cc:371:parse_blif$51)
   48: \n566 (via $auto$blifparse.cc:371:parse_blif$52)
   49: \n567 (via $auto$blifparse.cc:371:parse_blif$53)
   50: \n568 (via $auto$blifparse.cc:371:parse_blif$54)
   51: \n569 (via $auto$blifparse.cc:371:parse_blif$55)
   52: \n570 (via $auto$blifparse.cc:371:parse_blif$56)
   53: \n571 (via $auto$blifparse.cc:371:parse_blif$57)
   54: \n572 (via $auto$blifparse.cc:371:parse_blif$58)
   55: \n573 (via $auto$blifparse.cc:371:parse_blif$59)
   56: \n574 (via $auto$blifparse.cc:371:parse_blif$60)
   57: \n575 (via $auto$blifparse.cc:371:parse_blif$61)
   58: \n576 (via $auto$blifparse.cc:371:parse_blif$62)
   59: \n577 (via $auto$blifparse.cc:371:parse_blif$63)
   60: \n578 (via $auto$blifparse.cc:371:parse_blif$64)
   61: \n579 (via $auto$blifparse.cc:371:parse_blif$65)
   62: \n580 (via $auto$blifparse.cc:371:parse_blif$66)
   63: \n581 (via $auto$blifparse.cc:371:parse_blif$67)
   64: \n582 (via $auto$blifparse.cc:371:parse_blif$68)
   65: \n583 (via $auto$blifparse.cc:371:parse_blif$69)
   66: \n584 (via $auto$blifparse.cc:371:parse_blif$70)
   67: \n585 (via $auto$blifparse.cc:371:parse_blif$71)
   68: \n586 (via $auto$blifparse.cc:371:parse_blif$72)
   69: \n587 (via $auto$blifparse.cc:371:parse_blif$73)
   70: \n588 (via $auto$blifparse.cc:371:parse_blif$74)
   71: \n589 (via $auto$blifparse.cc:371:parse_blif$75)
   72: \n590 (via $auto$blifparse.cc:371:parse_blif$76)
   73: \n591 (via $auto$blifparse.cc:371:parse_blif$77)
   74: \n592 (via $auto$blifparse.cc:371:parse_blif$78)
   75: \n593 (via $auto$blifparse.cc:371:parse_blif$79)
   76: \n594 (via $auto$blifparse.cc:371:parse_blif$80)
   77: \n595 (via $auto$blifparse.cc:371:parse_blif$81)
   78: \n596 (via $auto$blifparse.cc:371:parse_blif$82)
   79: \n597 (via $auto$blifparse.cc:371:parse_blif$83)
   80: \n598 (via $auto$blifparse.cc:371:parse_blif$84)
   81: \n599 (via $auto$blifparse.cc:371:parse_blif$85)
   82: \n600 (via $auto$blifparse.cc:371:parse_blif$86)
   83: \n601 (via $auto$blifparse.cc:371:parse_blif$87)
   84: \n602 (via $auto$blifparse.cc:371:parse_blif$88)
   85: \n603 (via $auto$blifparse.cc:371:parse_blif$89)
   86: \n604 (via $auto$blifparse.cc:371:parse_blif$90)
   87: \n605 (via $auto$blifparse.cc:371:parse_blif$91)
   88: \n606 (via $auto$blifparse.cc:371:parse_blif$92)
   89: \n607 (via $auto$blifparse.cc:371:parse_blif$93)
   90: \n608 (via $auto$blifparse.cc:371:parse_blif$94)
   91: \n609 (via $auto$blifparse.cc:371:parse_blif$95)
   92: \n610 (via $auto$blifparse.cc:371:parse_blif$96)
   93: \n611 (via $auto$blifparse.cc:371:parse_blif$97)
   94: \n612 (via $auto$blifparse.cc:371:parse_blif$98)
   95: \n613 (via $auto$blifparse.cc:371:parse_blif$99)
   96: \n614 (via $auto$blifparse.cc:371:parse_blif$100)
   97: \n615 (via $auto$blifparse.cc:371:parse_blif$101)
   98: \n616 (via $auto$blifparse.cc:371:parse_blif$102)
   99: \n617 (via $auto$blifparse.cc:371:parse_blif$103)
  100: \n618 (via $auto$blifparse.cc:371:parse_blif$104)
  101: \n619 (via $auto$blifparse.cc:371:parse_blif$105)
  102: \n620 (via $auto$blifparse.cc:371:parse_blif$106)
  103: \n621 (via $auto$blifparse.cc:371:parse_blif$107)
  104: \n622 (via $auto$blifparse.cc:371:parse_blif$108)
  105: \n623 (via $auto$blifparse.cc:371:parse_blif$109)
  106: \n624 (via $auto$blifparse.cc:371:parse_blif$110)
  107: \n625 (via $auto$blifparse.cc:371:parse_blif$111)
  108: \n626 (via $auto$blifparse.cc:371:parse_blif$112)
  109: \n627 (via $auto$blifparse.cc:371:parse_blif$113)
  110: \n628 (via $auto$blifparse.cc:371:parse_blif$114)
  111: \n629 (via $auto$blifparse.cc:371:parse_blif$115)
  112: \n630 (via $auto$blifparse.cc:371:parse_blif$116)
  113: \n631 (via $auto$blifparse.cc:371:parse_blif$117)
  114: \n632 (via $auto$blifparse.cc:371:parse_blif$118)
  115: \n633 (via $auto$blifparse.cc:371:parse_blif$119)
  116: \n634 (via $auto$blifparse.cc:371:parse_blif$120)
  117: \n635 (via $auto$blifparse.cc:371:parse_blif$121)
  118: \n636 (via $auto$blifparse.cc:371:parse_blif$122)
  119: \n637 (via $auto$blifparse.cc:371:parse_blif$123)
  120: \n638 (via $auto$blifparse.cc:371:parse_blif$124)
  121: \n639 (via $auto$blifparse.cc:371:parse_blif$125)
  122: \n640 (via $auto$blifparse.cc:371:parse_blif$126)
  123: \n641 (via $auto$blifparse.cc:371:parse_blif$127)
  124: \n642 (via $auto$blifparse.cc:371:parse_blif$128)
  125: \n643 (via $auto$blifparse.cc:371:parse_blif$129)
  126: \n644 (via $auto$blifparse.cc:371:parse_blif$130)
  127: \n645 (via $auto$blifparse.cc:371:parse_blif$131)
  128: \n646 (via $auto$blifparse.cc:371:parse_blif$132)
  129: \n647 (via $auto$blifparse.cc:371:parse_blif$133)
  130: \n648 (via $auto$blifparse.cc:371:parse_blif$134)
  131: \n649 (via $auto$blifparse.cc:371:parse_blif$135)
  132: \n650 (via $auto$blifparse.cc:371:parse_blif$136)
  133: \n651 (via $auto$blifparse.cc:371:parse_blif$137)
  134: \n652 (via $auto$blifparse.cc:371:parse_blif$138)
  135: \n653 (via $auto$blifparse.cc:371:parse_blif$139)
  136: \n654 (via $auto$blifparse.cc:371:parse_blif$140)
  137: \n655 (via $auto$blifparse.cc:371:parse_blif$141)
  138: \n656 (via $auto$blifparse.cc:371:parse_blif$142)
  139: \n657 (via $auto$blifparse.cc:371:parse_blif$143)
  140: \n658 (via $auto$blifparse.cc:371:parse_blif$144)
  141: \n659 (via $auto$blifparse.cc:371:parse_blif$145)
  142: \n660 (via $auto$blifparse.cc:371:parse_blif$146)
  143: \n661 (via $auto$blifparse.cc:371:parse_blif$147)
  144: \n662 (via $auto$blifparse.cc:371:parse_blif$148)
  145: \n663 (via $auto$blifparse.cc:371:parse_blif$149)
  146: \n664 (via $auto$blifparse.cc:371:parse_blif$150)
  147: \n665 (via $auto$blifparse.cc:371:parse_blif$151)
  148: \n666 (via $auto$blifparse.cc:371:parse_blif$152)
  149: \n667 (via $auto$blifparse.cc:371:parse_blif$153)
  150: \n668 (via $auto$blifparse.cc:371:parse_blif$154)
  151: \n669 (via $auto$blifparse.cc:371:parse_blif$155)
  152: \n670 (via $auto$blifparse.cc:371:parse_blif$156)
  153: \n671 (via $auto$blifparse.cc:371:parse_blif$157)
  154: \n672 (via $auto$blifparse.cc:371:parse_blif$158)
  155: \n673 (via $auto$blifparse.cc:371:parse_blif$159)
  156: \n674 (via $auto$blifparse.cc:371:parse_blif$160)
  157: \n675 (via $auto$blifparse.cc:371:parse_blif$161)
  158: \n676 (via $auto$blifparse.cc:371:parse_blif$162)
  159: \n677 (via $auto$blifparse.cc:371:parse_blif$163)
  160: \n678 (via $auto$blifparse.cc:371:parse_blif$164)
  161: \n679 (via $auto$blifparse.cc:371:parse_blif$165)
  162: \n680 (via $auto$blifparse.cc:371:parse_blif$166)
  163: \n681 (via $auto$blifparse.cc:371:parse_blif$167)
  164: \n682 (via $auto$blifparse.cc:371:parse_blif$168)
  165: \n683 (via $auto$blifparse.cc:371:parse_blif$169)
  166: \n684 (via $auto$blifparse.cc:371:parse_blif$170)
  167: \n685 (via $auto$blifparse.cc:371:parse_blif$171)
  168: \n686 (via $auto$blifparse.cc:371:parse_blif$172)
  169: \n687 (via $auto$blifparse.cc:371:parse_blif$173)
  170: \n688 (via $auto$blifparse.cc:371:parse_blif$174)
  171: \n689 (via $auto$blifparse.cc:371:parse_blif$175)
  172: \n690 (via $auto$blifparse.cc:371:parse_blif$176)
  173: \n691 (via $auto$blifparse.cc:371:parse_blif$177)
  174: \n692 (via $auto$blifparse.cc:371:parse_blif$178)
  175: \n693 (via $auto$blifparse.cc:371:parse_blif$179)
  176: \n694 (via $auto$blifparse.cc:371:parse_blif$180)
  177: \n695 (via $auto$blifparse.cc:371:parse_blif$181)
  178: \n696 (via $auto$blifparse.cc:371:parse_blif$182)
  179: \n697 (via $auto$blifparse.cc:371:parse_blif$183)
  180: \n698 (via $auto$blifparse.cc:371:parse_blif$184)
  181: \n699 (via $auto$blifparse.cc:371:parse_blif$185)
  182: \n700 (via $auto$blifparse.cc:371:parse_blif$186)
  183: \n701 (via $auto$blifparse.cc:371:parse_blif$187)
  184: \n702 (via $auto$blifparse.cc:371:parse_blif$188)
  185: \n703 (via $auto$blifparse.cc:371:parse_blif$189)
  186: \n704 (via $auto$blifparse.cc:371:parse_blif$190)
  187: \n705 (via $auto$blifparse.cc:371:parse_blif$191)
  188: \n706 (via $auto$blifparse.cc:371:parse_blif$192)
  189: \n707 (via $auto$blifparse.cc:371:parse_blif$193)
  190: \n708 (via $auto$blifparse.cc:371:parse_blif$194)
  191: \n709 (via $auto$blifparse.cc:371:parse_blif$195)
  192: \n710 (via $auto$blifparse.cc:371:parse_blif$196)
  193: \n711 (via $auto$blifparse.cc:371:parse_blif$197)
  194: \n712 (via $auto$blifparse.cc:371:parse_blif$198)
  195: \n713 (via $auto$blifparse.cc:371:parse_blif$199)
  196: \n714 (via $auto$blifparse.cc:371:parse_blif$200)
  197: \n715 (via $auto$blifparse.cc:371:parse_blif$201)
  198: \n716 (via $auto$blifparse.cc:371:parse_blif$202)
  199: \n717 (via $auto$blifparse.cc:371:parse_blif$203)
  200: \n718 (via $auto$blifparse.cc:371:parse_blif$204)
  201: \n719 (via $auto$blifparse.cc:371:parse_blif$205)
  202: \n720 (via $auto$blifparse.cc:371:parse_blif$206)
  203: \n721 (via $auto$blifparse.cc:371:parse_blif$207)
  204: \n722 (via $auto$blifparse.cc:371:parse_blif$208)
  205: \n723 (via $auto$blifparse.cc:371:parse_blif$209)
  206: \n724 (via $auto$blifparse.cc:371:parse_blif$210)
  207: \n725 (via $auto$blifparse.cc:371:parse_blif$211)
  208: \n726 (via $auto$blifparse.cc:371:parse_blif$212)
  209: \n727 (via $auto$blifparse.cc:371:parse_blif$213)
  210: \n728 (via $auto$blifparse.cc:371:parse_blif$214)
  211: \n729 (via $auto$blifparse.cc:371:parse_blif$215)
  212: \n730 (via $auto$blifparse.cc:371:parse_blif$216)
  213: \n731 (via $auto$blifparse.cc:371:parse_blif$217)
  214: \n732 (via $auto$blifparse.cc:371:parse_blif$218)
  215: \n733 (via $auto$blifparse.cc:371:parse_blif$219)
  216: \n734 (via $auto$blifparse.cc:371:parse_blif$220)
  217: \n735 (via $auto$blifparse.cc:371:parse_blif$221)
  218: \n736 (via $auto$blifparse.cc:371:parse_blif$222)
  219: \n737 (via $auto$blifparse.cc:371:parse_blif$223)
  220: \n738 (via $auto$blifparse.cc:371:parse_blif$224)
  221: \n739 (via $auto$blifparse.cc:371:parse_blif$225)
  222: \n740 (via $auto$blifparse.cc:371:parse_blif$226)
  223: \n741 (via $auto$blifparse.cc:371:parse_blif$227)
  224: \n742 (via $auto$blifparse.cc:371:parse_blif$228)
  225: \n743 (via $auto$blifparse.cc:371:parse_blif$229)
  226: \n744 (via $auto$blifparse.cc:371:parse_blif$230)
  227: \n745 (via $auto$blifparse.cc:371:parse_blif$231)
  228: \n746 (via $auto$blifparse.cc:371:parse_blif$232)
  229: \n747 (via $auto$blifparse.cc:371:parse_blif$233)
  230: \n748 (via $auto$blifparse.cc:371:parse_blif$234)
  231: \n749 (via $auto$blifparse.cc:371:parse_blif$235)
  232: \n750 (via $auto$blifparse.cc:371:parse_blif$236)
  233: \n751 (via $auto$blifparse.cc:371:parse_blif$237)
  234: \n752 (via $auto$blifparse.cc:371:parse_blif$238)
  235: \n753 (via $auto$blifparse.cc:371:parse_blif$239)
  236: \n754 (via $auto$blifparse.cc:371:parse_blif$240)
  237: \n755 (via $auto$blifparse.cc:371:parse_blif$241)
  238: \n756 (via $auto$blifparse.cc:371:parse_blif$242)
  239: \n757 (via $auto$blifparse.cc:371:parse_blif$243)
  240: \n758 (via $auto$blifparse.cc:371:parse_blif$244)
  241: \n759 (via $auto$blifparse.cc:371:parse_blif$245)
  242: \n760 (via $auto$blifparse.cc:371:parse_blif$246)
  243: \n761 (via $auto$blifparse.cc:371:parse_blif$247)
  244: \n762 (via $auto$blifparse.cc:371:parse_blif$248)
  245: \n763 (via $auto$blifparse.cc:371:parse_blif$249)
  246: \n764 (via $auto$blifparse.cc:371:parse_blif$250)
  247: \n765 (via $auto$blifparse.cc:371:parse_blif$251)
  248: \n766 (via $auto$blifparse.cc:371:parse_blif$252)
  249: \n767 (via $auto$blifparse.cc:371:parse_blif$253)
  250: \n768 (via $auto$blifparse.cc:371:parse_blif$254)
  251: \n769 (via $auto$blifparse.cc:371:parse_blif$255)
  252: \n770 (via $auto$blifparse.cc:371:parse_blif$256)
  253: \n771 (via $auto$blifparse.cc:371:parse_blif$257)
  254: \n772 (via $auto$blifparse.cc:371:parse_blif$258)
  255: \n773 (via $auto$blifparse.cc:371:parse_blif$259)
  256: \n774 (via $auto$blifparse.cc:371:parse_blif$260)
  257: \y0 (via $auto$blifparse.cc:371:parse_blif$261)

End of script. Logfile hash: e7b5d76830
CPU: user 0.01s system 0.01s, MEM: 16.62 MB total, 10.00 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 31% 1x ltp (0 sec), 27% 2x read_blif (0 sec), ...
>>> Temacle mapping succeed with area = 3281.9192485809326
full_adder_256 initial mapping area = 4746.0307775735855
full_adder_256 Temacle mapping area = 3281.9192485809326
full_adder_256 Temacle saveArea = (4746.0307775735855 - 3281.9192485809326) / 4746.0307775735855 = 30.849178979433038 %