Hello,
Thank you for the great work. Its very well written,however there are some compilation errors, namely:
Error (10822): HDL error at Rx.vhd(58): couldn't implement registers for assignments on this clock edge
Error (12152): Can't elaborate user hierarchy "Rx_top:RxTOP|Rx:Reciever"
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 12 warnings
Error: Peak virtual memory: 4774 megabytes
Error: Processing ended: Tue Jul 13 15:28:40 2021
Error: Elapsed time: 00:00:07
Error: Total CPU time (on all processors): 00:00:16
Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 12 warnings
Do you know how to fix this?
Also, there are some other erros (but one error at a time). Did you make this code work on a FPGA?
Thank you.
Hello,
Thank you for the great work. Its very well written,however there are some compilation errors, namely:
Error (10822): HDL error at Rx.vhd(58): couldn't implement registers for assignments on this clock edge
Error (12152): Can't elaborate user hierarchy "Rx_top:RxTOP|Rx:Reciever"
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 12 warnings
Error: Peak virtual memory: 4774 megabytes
Error: Processing ended: Tue Jul 13 15:28:40 2021
Error: Elapsed time: 00:00:07
Error: Total CPU time (on all processors): 00:00:16
Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 12 warnings
Do you know how to fix this?
Also, there are some other erros (but one error at a time). Did you make this code work on a FPGA?
Thank you.