Component: Design AXI Bus

[Meowcaroni]

Purpose: Central AXI4 interconnect between masters and slaves. Performs address decode, per-slave channel arbitration, and ID-based routing so multiple transactions can be outstanding concurrently. Common widths/IDs are defined in rtl/bus/interconnect_pkg.sv.

Main File(s)

• AXI Top
• AXI Crossbar

Sub-File(s)

• AXI Instruction Cache Port
• AXI Data Cache Port
• AXI DMA
• MMU
• MIG AXI Wrap
• AXI-to-AXI Lite
• Peripheral AXI Shell
• AXI Async FIFO

Related Sub-Issues (Dependencies)