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sourav-ignsourav-ign
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implement socfpga configurator changes
 * configurator changes are implemented for portable layers and other dependant files. Signed-off-by: Sourav Raj K K <sourav.raj@ignitarium.com>
1 parent c09d5b6 commit c306a6f

3 files changed

Lines changed: 84 additions & 8 deletions

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‎apps/msc_app.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727
#include "tusb.h"
2828
#include "osal_log.h"
2929
#include "socfpga_cache.h"
30-
#include "hcd_dwc3.h"
30+
#include "host/hcd.h"
3131

3232
#define MSC_BLOCK_SIZE (512)
3333

@@ -97,7 +97,7 @@ void tuh_msc_umount_cb(uint8_t dev_addr)
9797
tuh_bus_info_get(dev_addr, &dev_info);
9898
if( dev_info.rhport != SOCFPGA_USB2_OTG_PORT )
9999
{
100-
hcd_dwc3_device_close(dev_info.rhport);
100+
hcd_device_close(dev_info.rhport, dev_addr);
101101
}
102102
PRINT("A MassStorage device is unmounted, address - %d\r\n", dev_addr);
103103
}

‎hw/bsp/socfpga/family.cmake‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,16 @@ add_subdirectory(${FREERTOS_TOP_DIR}/tinyusb/src ${CMAKE_CURRENT_BINARY_DIR}/tin
1616

1717
add_library(agilex5-tinyusb STATIC)
1818

19+
set(DWC2_SRCS
20+
${FREERTOS_TOP_DIR}/tinyusb/src/portable/socfpga/dwc2/hcd_dwc2.c
21+
${FREERTOS_TOP_DIR}/tinyusb/src/portable/socfpga/dwc2/dwc2_common.c
22+
)
23+
24+
set(DWC3_SRCS
25+
${FREERTOS_TOP_DIR}/tinyusb/src/portable/socfpga/dwc3/hcd_dwc3.c
26+
${FREERTOS_TOP_DIR}/tinyusb/src/portable/socfpga/dwc3/dwc3_common.c
27+
)
28+
1929
target_compile_definitions(agilex5-tinyusb PUBLIC CFG_TUSB_MCU=OPT_MCU_SOCFPGA CFG_TUSB_OS=OPT_OS_FREERTOS BOARD_TUH_MAX_SPEED=${RHPORT_DEVICE_SPEED})
2030

2131
target_include_directories(agilex5-tinyusb PUBLIC
@@ -33,11 +43,9 @@ target_include_directories(agilex5-tinyusb PUBLIC
3343
${FREERTOS_TOP_DIR}/tinyusb/src/portable/socfpga/hcd_socfpga.c
3444

3545
# Synopsys dwc2 controller
36-
${FREERTOS_TOP_DIR}/tinyusb/src/portable/socfpga/dwc2/hcd_dwc2.c
37-
${FREERTOS_TOP_DIR}/tinyusb/src/portable/socfpga/dwc2/dwc2_common.c
46+
$<$<STREQUAL:${CONFIG_USB_OTG_ISENABLE},y>:${DWC2_SRCS}>
3847

3948
# Synopsys dwc3 controller
40-
${FREERTOS_TOP_DIR}/tinyusb/src/portable/socfpga/dwc3/hcd_dwc3.c
41-
${FREERTOS_TOP_DIR}/tinyusb/src/portable/socfpga/dwc3/dwc3_common.c
49+
$<$<STREQUAL:${CONFIG_USB3_ISENABLE},y>:${DWC3_SRCS}>
4250
)
4351
target_link_libraries(agilex5-tinyusb PRIVATE socfpga_drivers m)

‎src/portable/socfpga/hcd_socfpga.c‎

Lines changed: 70 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,22 @@
2525
* This file is part of the TinyUSB stack.
2626
*/
2727

28+
#include "gen_config.h"
29+
30+
#if (CONFIG_USB3_ISENABLE == 0) && (CONFIG_USB_OTG_ISENABLE == 0)
31+
#error "Either usb3 or usb_otg driver should be enabled"
32+
#endif
33+
2834
#include "tusb_option.h"
29-
#include "hcd_dwc2.h"
30-
#include "hcd_dwc3.h"
35+
36+
#if (CONFIG_USB_OTG_ISENABLE == 1)
37+
#include "hcd_dwc2.h"
38+
#endif
39+
40+
#if (CONFIG_USB3_ISENABLE == 1)
41+
#include "hcd_dwc3.h"
42+
#endif
43+
3144

3245
//--------------------------------------------------------------------+
3346
// Controller API
@@ -49,13 +62,17 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
4962
bool ret;
5063
if( rhport == SOCFPGA_USB2_OTG_PORT )
5164
{
65+
#if (CONFIG_USB_OTG_ISENABLE == 1)
5266
//USB2.0 dwc2 controller initialization
5367
return hcd_dwc2_init(rhport, rh_init);
68+
#endif
5469
}
5570
else
5671
{
72+
#if (CONFIG_USB3_ISENABLE == 1)
5773
//USB3.1 controller initialization
5874
ret = hcd_dwc3_init(rhport, rh_init);
75+
#endif
5976

6077
}
6178

@@ -66,31 +83,41 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
6683
void hcd_int_enable (uint8_t rhport) {
6784
if( rhport == SOCFPGA_USB2_OTG_PORT )
6885
{
86+
#if (CONFIG_USB_OTG_ISENABLE == 1)
6987
hcd_dwc2_int_enable(rhport);
88+
#endif
7089
}
7190
else
7291
{
92+
#if (CONFIG_USB3_ISENABLE == 1)
7393
hcd_dwc3_int_enable(rhport);
94+
#endif
7495
}
7596
}
7697

7798
// Disable USB interrupt
7899
void hcd_int_disable(uint8_t rhport) {
79100
if( rhport == SOCFPGA_USB2_OTG_PORT )
80101
{
102+
#if (CONFIG_USB_OTG_ISENABLE == 1)
81103
hcd_dwc2_int_disable(rhport);
104+
#endif
82105
}
83106
else
84107
{
108+
#if (CONFIG_USB3_ISENABLE == 1)
85109
hcd_dwc3_int_disable(rhport);
110+
#endif
86111
}
87112
}
88113

89114
// Get frame number (1ms)
90115
uint32_t hcd_frame_number(uint8_t rhport) {
91116
if( rhport == SOCFPGA_USB2_OTG_PORT )
92117
{
118+
#if (CONFIG_USB_OTG_ISENABLE == 1)
93119
return hcd_dwc2_frame_number(rhport);
120+
#endif
94121
}
95122
else
96123
{
@@ -106,11 +133,15 @@ uint32_t hcd_frame_number(uint8_t rhport) {
106133
bool hcd_port_connect_status(uint8_t rhport) {
107134
if( rhport == SOCFPGA_USB2_OTG_PORT )
108135
{
136+
#if (CONFIG_USB_OTG_ISENABLE == 1)
109137
return hcd_dwc2_port_connect_status(rhport);
138+
#endif
110139
}
111140
else
112141
{
142+
#if (CONFIG_USB3_ISENABLE == 1)
113143
return hcd_dwc3_port_connect_status(rhport);
144+
#endif
114145
}
115146

116147
return true;
@@ -121,35 +152,47 @@ bool hcd_port_connect_status(uint8_t rhport) {
121152
void hcd_port_reset(uint8_t rhport) {
122153
if( rhport == SOCFPGA_USB2_OTG_PORT )
123154
{
155+
#if (CONFIG_USB_OTG_ISENABLE == 1)
124156
hcd_dwc2_port_reset(rhport);
157+
#endif
125158
}
126159
else
127160
{
161+
#if (CONFIG_USB3_ISENABLE == 1)
128162
hcd_dwc3_port_reset(rhport);
163+
#endif
129164
}
130165
}
131166

132167
// Complete bus reset sequence, may be required by some controllers
133168
void hcd_port_reset_end(uint8_t rhport) {
134169
if( rhport == SOCFPGA_USB2_OTG_PORT )
135170
{
171+
#if (CONFIG_USB_OTG_ISENABLE == 1)
136172
hcd_dwc2_port_reset_end(rhport);
173+
#endif
137174
}
138175
else
139176
{
177+
#if (CONFIG_USB3_ISENABLE == 1)
140178
hcd_dwc3_port_reset_end(rhport);
179+
#endif
141180
}
142181
}
143182

144183
// Get port link speed
145184
tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
146185
if( rhport == SOCFPGA_USB2_OTG_PORT )
147186
{
187+
#if (CONFIG_USB_OTG_ISENABLE == 1)
148188
return hcd_dwc2_port_speed_get(rhport);
189+
#endif
149190
}
150191
else
151192
{
193+
#if (CONFIG_USB3_ISENABLE == 1)
152194
return hcd_dwc3_port_speed_get(rhport);
195+
#endif
153196
}
154197
return 0;
155198
}
@@ -158,10 +201,15 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
158201
void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
159202
if( rhport == SOCFPGA_USB2_OTG_PORT )
160203
{
204+
#if (CONFIG_USB_OTG_ISENABLE == 1)
161205
hcd_dwc2_device_close(rhport, dev_addr);
206+
#endif
162207
}
163208
else
164209
{
210+
#if (CONFIG_USB3_ISENABLE == 1)
211+
hcd_dwc3_device_close(rhport);
212+
#endif
165213
}
166214
}
167215

@@ -173,7 +221,9 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
173221
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* desc_ep) {
174222
if( rhport == SOCFPGA_USB2_OTG_PORT )
175223
{
224+
#if (CONFIG_USB_OTG_ISENABLE == 1)
176225
return hcd_dwc2_edpt_open(rhport, dev_addr, desc_ep);
226+
#endif
177227
}
178228
else
179229
{
@@ -193,11 +243,15 @@ bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
193243
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint32_t buflen) {
194244
if( rhport == SOCFPGA_USB2_OTG_PORT )
195245
{
246+
#if (CONFIG_USB_OTG_ISENABLE == 1)
196247
return hcd_dwc2_edpt_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
248+
#endif
197249
}
198250
else
199251
{
252+
#if (CONFIG_USB3_ISENABLE == 1)
200253
return hcd_dwc3_edpt_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
254+
#endif
201255
}
202256
return true;
203257
}
@@ -207,7 +261,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
207261
bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
208262
if( rhport == SOCFPGA_USB2_OTG_PORT )
209263
{
264+
#if (CONFIG_USB_OTG_ISENABLE == 1)
210265
return hcd_dwc2_edpt_abort_xfer(rhport, dev_addr, ep_addr);
266+
#endif
211267
}
212268
else
213269
{
@@ -219,11 +275,15 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
219275
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet[8]) {
220276
if( rhport == SOCFPGA_USB2_OTG_PORT )
221277
{
278+
#if (CONFIG_USB_OTG_ISENABLE == 1)
222279
return hcd_dwc2_setup_send(rhport, dev_addr, setup_packet);
280+
#endif
223281
}
224282
else
225283
{
284+
#if (CONFIG_USB3_ISENABLE == 1)
226285
return hcd_dwc3_setup_send(rhport, dev_addr, setup_packet);
286+
#endif
227287
}
228288
return true;
229289
}
@@ -233,7 +293,9 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
233293
(void) rhport;
234294
if( rhport == SOCFPGA_USB2_OTG_PORT )
235295
{
296+
#if (CONFIG_USB_OTG_ISENABLE == 1)
236297
return hcd_dwc2_edpt_clear_stall(rhport, dev_addr, ep_addr);
298+
#endif
237299
}
238300
else
239301
{
@@ -250,7 +312,9 @@ bool hcd_parse_full_conf_descriptor( tusb_desc_configuration_t *desc_cfg, uint8_
250312
}
251313
else
252314
{
315+
#if (CONFIG_USB3_ISENABLE == 1)
253316
return hcd_dwc3_parse_full_conf_descriptor(desc_cfg);
317+
#endif
254318
}
255319

256320
return true;
@@ -259,11 +323,15 @@ bool hcd_parse_full_conf_descriptor( tusb_desc_configuration_t *desc_cfg, uint8_
259323
void hcd_int_handler(uint8_t rhport, bool in_isr) {
260324
if( rhport == SOCFPGA_USB2_OTG_PORT )
261325
{
326+
#if (CONFIG_USB_OTG_ISENABLE == 1)
262327
hcd_dwc2_int_handler(rhport, in_isr);
328+
#endif
263329
}
264330
else
265331
{
332+
#if (CONFIG_USB3_ISENABLE == 1)
266333
hcd_dwc3_int_handler(rhport, in_isr);
334+
#endif
267335
}
268336

269337
}

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