Preliminary workshop date is 29 November 2025.
Language: Russian.
Overall time of the event is 3-4 hours plus lunch break at the canteen in the middle.
- Foreword. Couple of words about the University, about room setup, about plan.
- Introduction.
- Discussion about Chip Design School in general, supported by Yadro.
- Historical reference about Yuri Panchul and MIET.
- Demonstration of the School lecture topics, practical exercises on FPGA boards and homeworks.
- Mention of the MIET's APS course for students interested specifically in RISC-V processors.
- Discussion about the SoC Challenge by Yadro. Presentation of the tracks: RTL, Topology, System Programming. Team formation for '26. Maybe example of the previous year task for RTL Junior track and Sys Programming.
- Presentation to the ALU Task. Explanation of the class planning.
- Theoretical part.
- Practical part.
- Discuss about microelectronics and digital circuit design.
- Basics on combinational and sequential logic.
- Basics on HDL in general and SystemVerilog in particular. Three ways to execute Verilog: sim, fpga, asic.
- Theory on binary numbers, two's bit complement, adder/subtractor.
- Theory on equality.
- Theory on binary multiplicator.
- Introduction to the setup. Configuration of the TM1638 board connection.
- Implementation of the 8-bit adder.
- Checking of the implementation correctness with adder Testbench using terminal.
- Implementation of the 8-bit adder/subtractor with mux for two's complement.
- Checking of the implementation correctness with adder/subtractor Testbench using terminal.
- Implementation of the equality with generate.
- Checking correctness with testbench.
- Implementation of the multiplicator.
- Checking correctness with testbench.
- Implementation of the ALU.
- Final full check with final testbench.
- Talk about Yosis and OpenROAD (LibreLane), show GDSII file with ALU using Tiny Tapeout with SKY130 cells.
- Talk about opportunities of the MPW MIET shuttle service.