Parse Altium Multi-Channel designs

[WLaney]

Problem

If you have an Altium Multi-Channel design the MCP server only picks up one on channel. This leads to it giving incorrect responses to questions like how many time a component appears in a design.

Proposed Solution

Parse the .SchDoc files to understand if they're calling into other .SchDocs multiple times

Alternatives Considered

NA

Use Case

Multi channel design is extremely common in non-trival Altium designs.

[valentinozegna]

PR #52 implements multi-channel expansion and cross-sheet PORT connectivity.

What changed:

• PORT records (RECORD=18) are now treated as globally-named connectable devices, fixing cross-sheet signal connectivity (same mechanism as NET_LABEL and POWER_PORT)
• PrjPCBStructure is parsed to identify repeated sheets and their channel designators
• Repeated sheets are expanded into N channel instances with components renamed per ChannelDesignatorFormatString (e.g., DD12 becomes DD12_AY1, DD12_AY2, DD12_AY3)
• Nets are classified using SHEET_ENTRY records on the parent schematic:
  • Power nets (POWER_PORT): global, unchanged
  • Shared SHEET_ENTRY signals (including bus notation like AD[0..7]): global, unchanged
  • Repeat() SHEET_ENTRY signals: per-channel suffix (e.g., CS becomes CS_AY1)
  • Local nets: per-channel suffix
• SHEET_ENTRY is deliberately excluded from within-sheet connectivity (it uses relative coordinates, not absolute), with cross-sheet connection handled at the project level instead

Verified on the aberrant-sound-module fixture:

• 3x AY-3-8912 instances (DD12_AY1, DD12_AY2, DD12_AY3) with surrounding passives also expanded
• Shared bus signals (AD0-AD7, BDIR) connect all 3 channels to the system bus
• Per-channel signals (CS_AY1/2/3, L_AY1/2/3, R_AY1/2/3) correctly isolated
• XNET tracing works through the resistor mixing network in the audio output stage
• Total: 103 components, 107 nets

Also verified zero regressions on pca10056, LimeSDR, and STM32 fixtures (53/53 MCP spot-checks passed).

Known limitations (not addressed in this PR):

• Hidden power pins (ELECTRICAL=7 with hidden flag in PinConglomerate) are not auto-connected. DD12's Vcc/Vss and control pins like CLK, RST, BC1, BC2 show as NC when they lack explicit wiring on the schematic. This is a separate concern (Phase 3 in the plan).
• Only HierarchyMode=0 (flat) is supported. Hierarchical mode designs where PORTs scope to their hierarchy level would need additional work.