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### What this PR does / why we need it?
port vllm-project#12351 to main branch.
### Does this PR introduce _any_ user-facing change?
### How was this patch tested?
- vLLM version: v0.25.1
- vLLM main:
vllm-project/vllm@fe784ff
---------
Signed-off-by: ZYang6263 <50876451+ZYang6263@users.noreply.github.com>
Signed-off-by: Angazenn <supperccell@163.com>
Co-authored-by: ZYang6263 <50876451+ZYang6263@users.noreply.github.com>
Copy file name to clipboardExpand all lines: docs/source/user_guide/configuration/additional_config.md
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@@ -78,8 +78,9 @@ The following table lists additional configuration options available in vLLM Asc
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|`enable_sleep_mode_extra_cleanup`| bool |`False`| Enables extra sleep-mode cleanup for RL workloads, including HCCL process-group release and ACL graph workspace cleanup. Disabled by default because wakeup may need to restore HCCL and recapture ACL graphs. |
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|`pa_shape_list`| list |`[]`| The custom shape list of page attention ops. |
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|`enable_kv_nz`| bool |`False`| Whether to enable KV cache NZ layout. This option only takes effects on models using MLA (e.g., DeepSeek). |
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|`enable_sparse_c8`| bool |`False`| Whether to enable KV cache C8 in DSA models (e.g., DeepSeek V3.2 and GLM5). Not supported on Ascend 950 devices now |
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|`c8_enable_reshape_optim`| bool |`False`| Whether to enable StoreKVBlock operator achieves acceleration under the C8 feature (this means that enable_sparse_c8 needs to be enabled). In the PD separation scenario, only the P node is enabled. |
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|`enable_sparse_sfa_c8`| bool |`False`| Whether to enable the packed C8 KV cache for Sparse Flash Attention in DSA models (e.g., DeepSeek V3.2 and GLM5). This option is independent of `enable_sparse_li_c8`. SFA prefill context parallelism and Ascend 950 DCP are not supported. |
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|`enable_sparse_li_c8`| bool |`False`| Whether to enable the C8 key and scale caches for LightningIndexer in DSA models. This option is independent of `enable_sparse_sfa_c8` and only applies to eligible indexer layers from the model quantization config. SFA prefill context parallelism and Ascend 950 DCP are not supported. |
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|`c8_enable_reshape_optim`| bool |`False`| Whether to use the StoreKVBlock operator to accelerate LightningIndexer C8 cache writes. `enable_sparse_li_c8` must also be enabled. In the PD separation scenario, only the P node is enabled. |
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|`enable_mc2_hierarchy_comm`| bool |`False`| Enable dispatch/combine op inter-node communication by ROCE. |
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|`enable_prefill_mc2`| bool |`False`| Whether to reserve mc2_token_capacity for prefill batches. When enabled, `max_num_batched_tokens` is used to calculate the mc2_token_capacity instead of the decode-only capacity. In this scenario, the recommended maximum value of `max_num_batched_tokens` is `tp_size * 512`. This is a temporary switch; once MC2 operators are complete for all scenarios, this switch will be removed and MC2 will be enabled by default. |
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|`mega_moe_max_tokens`| int |`65536`| Per-rank token capacity after dispatch in the mega moe (dispatch_ffn_combine) fused operator. When load imbalance causes a rank to receive more tokens than this limit, the excess tokens are dropped and skipped from computation, degrading accuracy. Do not set this too large: workspace memory scales linearly with this value. |
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