Commit b417b95
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[Feature][Test] Enable "c8_enable_reshape_optim" for A5 and add ut coverage (vllm-project#11451)
### What this PR does / why we need it?
This PR addresses two items:
1. **Add unit test for the `c8_enable_reshape_optim = True` code path**
When `c8_enable_reshape_optim` is `True`,
`AscendSFAMetadataBuilder._build()` reads `slot_mapping_cpu`, invokes
`torch.ops._C_ascend.store_kv_block_pre`, and populates the returned
`group_len`, `group_key_idx`, and `group_key_cache_idx` into the
metadata. This branch previously had no UT coverage. The new test
verifies:
- `slot_mapping_cpu` is correctly sliced and forwarded to the op
- The op is called with the expected arguments (`slot_mapping`,
`slot_mapping_cpu.tolist()`, `block_size`)
- The return values are correctly propagated to `metadata.group_len` /
`group_key_idx` / `group_key_cache_idx`
- `block_size=128` behavior is as expected
The test runs under a pure TP setup without DCP/PCP group dependencies.
2. **Enable `store_kv_block` custom operator compilation for A5**
Adds `store_kv_block` to the Ascend950 (A5) `CUSTOM_OPS_ARRAY` in
`csrc/build_aclnn.sh` so the operator compiles correctly on A5 hardware,
supporting downstream E2E testing and inference.
### Does this PR introduce _any_ user-facing change?
No. Test and build configuration changes only.
### How was this patch tested?
- UT: `pytest -sv
tests/ut/attention/a2/test_sfa_v1.py::TestAscendSFAMetadataBuilder::test_ascend_sfa_metadata_builder_build_with_c8_reshape_optim`
- vLLM version: v0.23.0
- vLLM main:
vllm-project/vllm@1f486d9
Signed-off-by: Li Jiahang <216526138+lijiahang226@users.noreply.github.com>1 parent ee2a613 commit b417b95
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