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top_processor.qsf
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110 lines (108 loc) · 5.3 KB
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 10.1 Build 153 11/29/2010 SJ Web Edition
# Date created = 03:02:47 May 05, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# top_processor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY top_processor
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "03:02:47 MAY 05, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_G12 -to rx
set_location_assignment PIN_G9 -to tx
set_location_assignment PIN_Y2 -to clock
set_location_assignment PIN_M23 -to rd_clr
set_location_assignment PIN_AB28 -to start_process
set_location_assignment PIN_AC28 -to start_transmit
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name QIP_FILE dram.qip
set_global_assignment -name VERILOG_FILE top_processor.v
set_global_assignment -name VERILOG_FILE sor.v
set_global_assignment -name VERILOG_FILE reg3.v
set_global_assignment -name VERILOG_FILE reg2.v
set_global_assignment -name VERILOG_FILE reg1.v
set_global_assignment -name VERILOG_FILE ReadBus.v
set_global_assignment -name VERILOG_FILE Processor.v
set_global_assignment -name VERILOG_FILE pc.v
set_global_assignment -name VERILOG_FILE mar.v
set_global_assignment -name VERILOG_FILE main_controller.v
set_global_assignment -name VERILOG_FILE iram.v
set_global_assignment -name VERILOG_FILE ir.v
set_global_assignment -name VERILOG_FILE dstr.v
set_global_assignment -name VERILOG_FILE decoder.v
set_global_assignment -name VERILOG_FILE cram.v
set_global_assignment -name VERILOG_FILE coun.v
set_global_assignment -name VERILOG_FILE controller.v
set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name VERILOG_FILE ac.v
set_global_assignment -name VERILOG_FILE tb.v
set_global_assignment -name VERILOG_FILE slowclock.v
set_location_assignment PIN_G18 -to clk
set_location_assignment PIN_H15 -to mar_ac_disp[17]
set_location_assignment PIN_G16 -to mar_ac_disp[16]
set_location_assignment PIN_G15 -to mar_ac_disp[15]
set_location_assignment PIN_F15 -to mar_ac_disp[14]
set_location_assignment PIN_H17 -to mar_ac_disp[13]
set_location_assignment PIN_J16 -to mar_ac_disp[12]
set_location_assignment PIN_H16 -to mar_ac_disp[11]
set_location_assignment PIN_J15 -to mar_ac_disp[10]
set_location_assignment PIN_G17 -to mar_ac_disp[9]
set_location_assignment PIN_J17 -to mar_ac_disp[8]
set_location_assignment PIN_H19 -to mar_ac_disp[7]
set_location_assignment PIN_J19 -to mar_ac_disp[6]
set_location_assignment PIN_E18 -to mar_ac_disp[5]
set_location_assignment PIN_G19 -to mar_ac_disp[0]
set_location_assignment PIN_F19 -to mar_ac_disp[1]
set_location_assignment PIN_E19 -to mar_ac_disp[2]
set_location_assignment PIN_F18 -to mar_ac_disp[4]
set_location_assignment PIN_F21 -to mar_ac_disp[3]
set_location_assignment PIN_E21 -to pc_disp[0]
set_location_assignment PIN_E22 -to pc_disp[1]
set_location_assignment PIN_E25 -to pc_disp[2]
set_location_assignment PIN_E24 -to pc_disp[3]
set_location_assignment PIN_H21 -to pc_disp[4]
set_location_assignment PIN_G20 -to pc_disp[5]
set_location_assignment PIN_G22 -to pc_disp[6]
set_location_assignment PIN_F17 -to pc_disp[7]
set_global_assignment -name QIP_FILE C_ram.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top