Add gf180 scratch RAM

Author: MichaelBell

cpu/config.vlt

@@ -0,0 +1,5 @@
+`verilator_config
+lint_off -file "*/gf180mcu_fd_ip_sram__sram512x8m8wm1.v"
+lint_off -rule MINTYPMAXDLY -file "*/gf180mcu_fd_ip_sram__sram512x8m8wm1.v"
+lint_off -rule SPECIFYIGN -file "*/gf180mcu_fd_ip_sram__sram512x8m8wm1.v"
+

cpu/cpu.v

@@ -145,6 +145,11 @@ module tinyqv_cpu #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
     wire [3:0] timer_data;
     wire is_timer_addr;
 
+    wire [3:0] scratch_data;
+    wire is_scratch_addr;
+    
+    wire is_internal_addr = is_timer_addr || is_scratch_addr;
+
     reg no_write_in_progress;
     reg load_started;
     wire stall_core = !instr_valid || ((is_store || is_load) && !no_write_in_progress);
@@ -244,7 +249,7 @@ module tinyqv_cpu #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
 
             if (counter_hi == 3'd0) begin
                 data_ready_latch <= 0;
-                if (data_ready_ext || data_ready_latch || is_timer_addr) begin
+                if (data_ready_ext || data_ready_latch || is_internal_addr) begin
                     data_ready_sync <= 1;
                 end else begin
                     data_ready_sync <= 0;
@@ -257,7 +262,7 @@ module tinyqv_cpu #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
         end
     end
 
-    assign data_ready_core = (counter_hi == 3'd0) ? (data_ready_ext || data_ready_latch || is_timer_addr) : data_ready_sync;
+    assign data_ready_core = (counter_hi == 3'd0) ? (data_ready_ext || data_ready_latch || is_internal_addr) : data_ready_sync;
 
     always @(posedge clk) begin
         if (!rstn) begin
@@ -351,7 +356,8 @@ module tinyqv_cpu #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
         .counter(counter[4:2]),
         .pc(pc[counter+:4]),
         .next_pc(next_pc_for_core[counter+:4]),
-        .data_in(is_timer_addr ? timer_data : data_in[counter+:4]),
+        .data_in(is_timer_addr ? timer_data : 
+                 is_scratch_addr ? scratch_data : data_in[counter+:4]),
         .load_data_ready(data_ready_core),
 
         .data_out(data_out_slice),
@@ -462,6 +468,24 @@ module tinyqv_cpu #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
         .timer_interrupt(timer_interrupt)
     );
 
+`ifdef NO_SCRATCH
+    assign is_scratch_addr = 0;
+    assign scratch_data = 0;
+`else
+    // Scratch
+    assign is_scratch_addr = data_addr[27:12] == 16'hffff && data_addr[11:9] == 3'b110;
+    wire [1:0] scratch_write_n = data_write_n | {2{!is_scratch_addr}};
+    tinyqv_scratch i_scratch (
+        .clk(clk),
+        .rstn(rstn),
+        .data_addr(address_ready ? addr_out[8:0] : data_addr[8:0]),
+        .data_write_n(scratch_write_n),
+        .counter(counter_hi),
+        .data_in(data_out_slice),
+        .data_out(scratch_data)
+    );
+`endif
+
     // Debugging
     assign debug_instr_complete = instr_complete;
     assign debug_instr_valid = instr_valid;

cpu/internal_ram.v

@@ -0,0 +1,57 @@
+/* TinyQV: A RISC-V core designed to use minimal area.
+  
+   This module wraps an SRAM primitive to provide scratch RAM.
+
+   This version wraps the gf180 primitive.
+ */
+
+`default_nettype none
+
+module tinyqv_scratch #(parameter ADDR_BITS=9) (
+    input         clk,
+    input         rstn,
+
+    input [ADDR_BITS-1:0] data_addr,
+    input [1:0]   data_write_n,
+    input [2:0]   counter,
+
+    input [3:0]   data_in,
+    output [3:0]  data_out
+);
+
+    wire write_enable_n;
+    wire [7:0] write_bit_enable_n;
+    wire [7:0] data_from_read;
+    wire [1:0] byte_in_word;
+
+    /* verilator lint_off PINMISSING */
+    gf180mcu_fd_ip_sram__sram512x8m8wm1 i_sram (
+        .CLK(clk),
+        .CEN(!rstn),
+        .GWEN(write_enable_n),
+        .WEN(write_bit_enable_n),
+        .A({data_addr[ADDR_BITS-1:2], byte_in_word}),
+        .D({data_in, data_in}),
+        .Q(data_from_read)
+    );
+    /* verilator lint_on PINMISSING */
+
+    assign data_out = counter[0] ? data_from_read[7:4] : data_from_read[3:0];
+
+    assign write_enable_n = 
+        !((data_write_n == 2'b00 && counter[2:1] == 2'b00) ||
+          (data_write_n == 2'b01 && !counter[2]) ||
+          (data_write_n == 2'b10));
+
+    assign write_bit_enable_n = {{4{!counter[0]}}, {4{counter[0]}}};
+
+    // Byte address:
+    // - For writes this should be the data address + the counter/2 (as the counter counts in nibbles)
+    // - For reads this needs to give the correct address to read the nibble on the next cycle.
+    //   Therefore, increment by 1 on the second half of each byte.
+    //   Note the first byte is read on the last count of the previous cycle (this is OK because the 
+    //   address is already complete by then).
+    // Can use XOR instead of ADD because we assume the address is aligned for the width of the transaction.
+    assign byte_in_word = (counter[2:1] + {1'b0, counter[0] && (data_write_n == 2'b11)}) ^ data_addr[1:0];
+
+endmodule

cpu/lint.sh

@@ -1,3 +1,3 @@
 #!/bin/bash
 
-verilator --lint-only -DSIM --timing -Wall -Wno-DECLFILENAME -Wno-MULTITOP *.v
+verilator --lint-only -DSIM --timing -Wall -Wno-DECLFILENAME -Wno-MULTITOP -Wno-TIMESCALEMOD config.vlt *.v $PDK_ROOT/gf180mcuD/libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram512x8m8wm1.v

test/test_cpu.mk

@@ -8,6 +8,7 @@ TOPLEVEL_LANG ?= verilog
 CPUD = $(PWD)/../cpu
 VERILOG_SOURCES += $(CPUD)/cpu.v $(CPUD)/decode.v $(CPUD)/core.v $(CPUD)/alu.v $(CPUD)/register.v $(CPUD)/counter.v $(CPUD)/time.v $(CPUD)/buffer.v  $(PWD)/tb_cpu.v
 COMPILE_ARGS    += -DSIM
+COMPILE_ARGS    += -DNO_SCRATCH
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
 TOPLEVEL = tb_cpu