You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Currently, constraints on operands/fields in the encoding are evaluated in the behavior block by explicitly raising an Illegal Instruction. It would be great if we could find a way to define those conditions somewhere else.
Examples:
RV32E: Hardwire the MSB of register operands to zero. (See #?)
Zpfsoperand: 64bit register pair operands made up of an even and odd register (rd & rd+1 where rd%2==0 and (optionally )non-overlapping constraints between source and dest registers)
RVV: implement Vector Load/Stores in a more compact fashion (See Add Mnemonic field to CoreDSL Syntax #80, Allowing us to cut down >150 instruction blocks to less than 20)
Currently, constraints on operands/fields in the encoding are evaluated in the behavior block by explicitly raising an Illegal Instruction. It would be great if we could find a way to define those conditions somewhere else.
Examples:
rd & rd+1whererd%2==0and (optionally )non-overlapping constraints between source and dest registers)SUNPKD810,SUNPKD820,SUNPKD830,SUNPKD831,SUNPKD832in a single instruction block (see Add Mnemonic field to CoreDSL Syntax #80)