fixes interrupt configurability of platform wrapper

Author: eyck

CMakeLists.txt

@@ -19,7 +19,7 @@ if(NOT TARGET dbt-rise-core)
     FetchContent_Declare(
         dbt_rise_core_git
         GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git"
-        GIT_TAG f50d2d185adf8bb9f073018631d7be2a53500224
+        GIT_TAG 8f181e19e14e3fe5cfba340b47795c7b48b7844a
         GIT_SHALLOW OFF
         UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped.
     )

src/iss/arch/riscv_hart_common.h

@@ -514,7 +514,7 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
         if(enable)
             this->disass_func = util::delegate<void(uint64_t, std::string const&, bool)>::from<this_class, &this_class::print_disass_output>(this);
         else
-            this->disass_func = util::delegate<void(uint64_t, std::string const&, bool)>::from<this_class, &this_class::print_disass_output>(nullptr);
+            this->disass_func = util::delegate<void(uint64_t, std::string const&, bool)>(nullptr);
     }
 
     void set_semihosting_callback(semihosting_cb_t<reg_t> cb) { semihosting_cb = cb; };
@@ -1011,7 +1011,12 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
 
     void set_next(mem::memory_if mem_if) override { memory = mem_if; };
 
-    void set_irq_num(unsigned i) { mcause_max_irq = std::max(1u << util::ilog2(i), 16u); }
+    void set_max_irq_num(unsigned i) { mcause_max_irq = std::max(1u << util::ilog2(i), 16u); }
+
+    void set_clint_custom_irq_num(unsigned num) {
+        assert(num<=traits<BASE>::XLEN);
+        clint_custom_irq_mask=std::numeric_limits<reg_t>::max()>>(traits<BASE>::XLEN-num);
+    }
 
 protected:
     util::InstanceLogger<logging::dbt_rise_iss> isslogger;
@@ -1060,7 +1065,7 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
     instrumentation_if* get_instrumentation_if() override { return &instr_if; };
 
     using csr_type = std::array<typename traits<BASE>::reg_t, 1ULL << 12>;
-    csr_type csr;
+    csr_type csr{0};
 
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
     std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
@@ -1074,6 +1079,7 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
     int64_t instret_offset{0};
     semihosting_cb_t<reg_t> semihosting_cb;
     unsigned mcause_max_irq{traits<BASE>::XLEN};
+    reg_t clint_custom_irq_mask{0xffff};
 };
 
 } // namespace arch

src/iss/arch/riscv_hart_m_p.h

@@ -316,7 +316,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
-    auto mask = riscv_hart_common<BASE>::get_irq_mask(3);
+    // generate mask from allowed writable bits, the number of custom interrupts and the available ie bits
+    auto mask = riscv_hart_common<BASE>::get_irq_mask(3) & this->clint_custom_irq_mask & 0x0888;
     this->csr[mie] = (this->csr[mie] & ~mask) | (val & mask);
     check_interrupt();
     return iss::Ok;

src/iss/arch/riscv_hart_msu_vp.h

@@ -416,7 +416,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FE
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
-    auto mask = riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3);
+    // generate mask from allowed writable bits, the number of custom interrupts and the available ie bits
+    auto mask = riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3) & this->clint_custom_irq_mask & (FEAT & FEAT_EXT_N?0xbbb:0xaaa);
     this->csr[mie] = (this->csr[mie] & ~mask) | (val & mask);
     check_interrupt();
     return iss::Ok;

src/iss/arch/riscv_hart_mu_p.h

@@ -345,7 +345,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
-    auto mask = riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3);
+    // generate mask from allowed writable bits, the number of custom interrupts and the available ie bits
+    auto mask = riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3) & this->clint_custom_irq_mask & (FEAT & FEAT_EXT_N?0x999:0x888);
     this->csr[mie] = (this->csr[mie] & ~mask) | (val & mask);
     check_interrupt();
     return iss::Ok;

src/sysc/core_complex.h

@@ -86,7 +86,7 @@ using irq_signal_t = sc_core::sc_in<bool>;
 
 enum { SW_IRQ = 3, TIMER_IRQ = 7, EXT_IRQ = 11, LOCAL_IRQ_START = 16 };
 
-template <unsigned int BUSWIDTH = scc::LT, typename QK = tlm::scc::quantumkeeper>
+template <unsigned int BUSWIDTH = scc::LT, typename QK = tlm::scc::quantumkeeper_st>
 class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
 public:
     using this_class = core_complex<BUSWIDTH, QK>;