Support for random number generation in Verilog-A missing

[rjordans]

I have a few Verilog-A modules that use functions like $rdist_normal but these are currently not implemented in OpenVAF.

I had a look at the code to see if this can be worked around but it seems that none of the random number generating functions is implemented.

Are there any plans to include this in the future?

[Kreijstal]

Right now this is just a port of arpad's version, so that it compiles on llvm18, let us see if we can upstream this change there if not, we can consider implementing it just here

[KrzysztofHerman]

@arpadbuermen @Kreijstal is there any plan for implementation of this function ? Our ReRAM Verilog-A model uses this function and in fact it is a show stopper to release it to open-source.

[arpadbuermen]

Will do it. In the meantime I am working on a workaround in pure Verilog-A. Will send it in a day or two. The implementation itself requires two things:

1. fixing the crash in $bound_step
2. adding random distributions (tricky, because it requires a change in the simulator; OpenVAF currently does not know when one iteration ends and the next iteration starts)

[arpadbuermen]

I don't know what the Verilog-A board was thinking when they wrote the spec, but storing the random generator state in an integer (be it i32 or i64) is impossible for any serious random number generator. The state is much longer than 32/64 bits.

[KrzysztofHerman]

Will do it. In the meantime I am working on a workaround in pure Verilog-A. Will send it in a day or two. The implementation itself requires two things:

1. fixing the crash in $bound_step

2. adding random distributions (tricky, because it requires a change in the simulator; OpenVAF currently does not know when one iteration ends and the next iteration starts)

Thank you @arpadbuermen we will follow the development and give you feedback while testing.

[arpadbuermen]

$bound_step is fixed. I sent a model with a $rdist_normal workaround to Sergei today.