diff --git a/src/main/scala/Bundles.scala b/src/main/scala/Bundles.scala
index cd8d3de..b0ef8ed 100644
--- a/src/main/scala/Bundles.scala
+++ b/src/main/scala/Bundles.scala
@@ -79,11 +79,11 @@ object Bundles {
   }
 
   class AmuMmaIO extends Bundle {
-    // rounding mode (xmfrm/xmxrm)
+    // rounding mode (mfrm/mxrm)
     val rm       = UInt(3.W) // 52 : 50
     // dest matrix register index
     val md       = UInt(4.W) // 49 : 46
-    // whether saturate (xmsaten)
+    // whether saturate (msaten)
     val sat      = Bool()    // 45
     // src matrix register indices
     val ms1      = UInt(4.W) // 44 : 41
@@ -152,7 +152,7 @@ object Bundles {
   }
 
   class AmuReleaseIO extends Bundle {
-    val tokenRd = UInt(5.W)
+    val msyncRd = UInt(5.W)
   }
 
   object AmuReleaseIO {
@@ -162,7 +162,7 @@ object Bundles {
   }
 
   class AmuArithIO extends Bundle {
-    // Only support mzero1r currently
+    // Only support mzero currently
     
     // dest matrix register index
     val md     = UInt(4.W) // 12 : 9
diff --git a/src/main/scala/TaskController.scala b/src/main/scala/TaskController.scala
index 11eb992..331a558 100644
--- a/src/main/scala/TaskController.scala
+++ b/src/main/scala/TaskController.scala
@@ -243,7 +243,7 @@ class TaskController(implicit p: Parameters) extends BaseTaskController {
 
   class ReleaseEventEntry extends Bundle {
     val eventType = UInt(2.W)
-    val token = UInt(5.W)
+    val msync = UInt(5.W)
     val slotId = UInt(SlotIdxWidth.W)
     val seqId = UInt(SeqIdWidth.W)
   }
@@ -949,10 +949,10 @@ class TaskController(implicit p: Parameters) extends BaseTaskController {
       is(TaskCtrlOpKind.Release) {
         val issueRelease = issueCtrl.data.asTypeOf(new AmuReleaseIO)
         io.ygjkctrl.mrelease.valid := true.B
-        io.ygjkctrl.mrelease.bits.tokenRd(issueRelease.tokenRd) := true.B
+        io.ygjkctrl.mrelease.bits.msyncRd(issueRelease.msyncRd) := true.B
 
         releaseIssueEvent.eventType := 0.U
-        releaseIssueEvent.token := issueRelease.tokenRd
+        releaseIssueEvent.msync := issueRelease.msyncRd
         releaseIssueEvent.slotId := issueSlotIdx
         releaseIssueEvent.seqId := issueSlot.seqId
         releaseIssueEventEn := true.B
diff --git a/src/main/scala/config_ygjk.scala b/src/main/scala/config_ygjk.scala
index 6f30da5..14304d0 100644
--- a/src/main/scala/config_ygjk.scala
+++ b/src/main/scala/config_ygjk.scala
@@ -37,7 +37,7 @@ class YGJKBuffer extends Bundle with YGJKParameters{
 }
 
 class MreleaseIO extends Bundle{
-    val tokenRd = Vec(32, Bool())
+    val msyncRd = Vec(32, Bool())
 }
 
 class YGJKControl(implicit p: Parameters) extends CuteBundle{