USI/transcript at main · Purdue-SoCET/USI · GitHub

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# //  Questa Sim-64
# //  Version 2021.4 linux_x86_64 Oct 13 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# vsim -voptargs="+acc" top_tb
# Start time: 17:20:56 on Apr 16,2026
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading sv_std.std
# Loading work.top_tb(fast)
# Loading work.bus_protocol_if(fast__1)
# Loading work.top(fast)
# Loading work.reg_map(fast)
# Loading work.data_buffer(fast)
# Loading work.datapath(fast)
# Loading work.control_unit(fast)
add wave -position insertpoint  \
sim:/top_tb/CLK \
sim:/top_tb/nRST \
sim:/top_tb/serial_in \
sim:/top_tb/serial_out \
sim:/top_tb/serial_clk \
sim:/top_tb/spi_cs_n \
sim:/top_tb/rdata \
sim:/top_tb/pass \
sim:/top_tb/fail
run -all
# PASS: mode_sel UART exp=00000000 act=00000000
# PASS: clkdiv exp=00000002 act=00000002
# PASS: config exp=00000000 act=00000000
# PASS: tx_data reg exp=aabbccdd act=aabbccdd
# ----- RX TEST -----
# Sent UART byte = a5
# Forced TX byte = dd
# Before serial shift: serial_out = 0
# bit[0] serial_out = 0 time=525000
# bit[1] serial_out = 1 time=555000
# bit[2] serial_out = 1 time=585000
# bit[3] serial_out = 1 time=615000
# bit[4] serial_out = 0 time=645000
# bit[5] serial_out = 1 time=675000
# bit[6] serial_out = 1 time=705000
# bit[7] serial_out = 1 time=735000
# Observed serial bits (LSB->MSB packed) = 11101110
# ----------------------------------
# PASS = 4
# FAIL = 0
# ----------------------------------
# ** Note: $finish    : testbench/top_tb.sv(203)
#    Time: 805 ns  Iteration: 0  Instance: /top_tb
# 1
# Break in Module top_tb at testbench/top_tb.sv line 203
# End time: 17:36:31 on Apr 16,2026, Elapsed time: 0:15:35
# Errors: 0, Warnings: 0