Add bitprog examples

Author: rodrigomelo9

examples/helpers/diamond.sh

@@ -16,3 +16,5 @@ python3 $HDIR/hdl2bit.py -t diamond -o results/diamond-vhdl -p lfxp2-5e-5tn144c
     --param FREQ 125000000 --param SECS 1 --last cfg Top
 
 python3 $HDIR/prj2bit.py results/diamond-vhdl/example.ldf
+
+# Diamond programming is not yet supported

examples/helpers/ise.sh

@@ -16,3 +16,5 @@ python3 $HDIR/hdl2bit.py -t ise -o results/ise-vhdl -p xc6slx16-3-csg32 --projec
     --param FREQ 125000000 --param SECS 1 --last cfg Top
 
 python3 $HDIR/prj2bit.py results/ise-vhdl/example.xise
+
+python3 $HDIR/bitprog.py -t ise results/ise-vhdl/example.bit

examples/helpers/libero.sh

@@ -16,3 +16,5 @@ python3 $HDIR/hdl2bit.py -t libero -o results/libero-vhdl -p m2s010-1-tq144 --pr
     --param FREQ 125000000 --param SECS 1 --last cfg Top
 
 python3 $HDIR/prj2bit.py results/libero-vhdl/libero/example.prjx
+
+python3 $HDIR/bitprog.py -t libero results/libero-vhdl/example.ppd

examples/helpers/openflow.sh

@@ -13,6 +13,8 @@ python3 $HDIR/hdl2bit.py -t openflow -o results/openflow-vlog -p hx1k-tq144 \
 python3 $HDIR/hdl2bit.py -t openflow -o results/openflow-vhdl -p hx1k-tq144 --project example \
     -f ../sources/vhdl/blink.vhdl,blink_lib -f ../sources/vhdl/blink_pkg.vhdl,blink_lib -f ../sources/vhdl/top.vhdl \
     -f ../sources/cons/icestick/clk.pcf -f ../sources/cons/icestick/led.pcf \
-    --param FREQ 125000000 --param SECS 1 --last cfg Top
+    --param FREQ 125000000 --param SECS 1 --last syn Top
 
 # OpenFlow doesn't have a project file, so it is not supported by prj2bit
+
+python3 $HDIR/bitprog.py -t openflow results/openflow-vhdl/openflow.bit

examples/helpers/quartus.sh

@@ -16,3 +16,5 @@ python3 $HDIR/hdl2bit.py -t quartus -o results/quartus-vhdl -p 5CSEBA6U23I7 --pr
     --param FREQ 125000000 --param SECS 1 --last cfg Top
 
 python3 $HDIR/prj2bit.py results/quartus-vhdl/example.qpf
+
+python3 $HDIR/bitprog.py -t quartus results/quartus-vhdl/example.sof

examples/helpers/vivado.sh

@@ -16,3 +16,5 @@ python3 $HDIR/hdl2bit.py -t vivado -o results/vivado-vhdl -p xc7z010-1-clg400 --
     --param FREQ 125000000 --param SECS 1 --last cfg Top
 
 python3 $HDIR/prj2bit.py results/vivado-vhdl/example.xpr
+
+python3 $HDIR/bitprog.py -t vivado results/vivado-vhdl/example.bit

tests/regress.sh

@@ -69,3 +69,7 @@ for TOOL in "${!TOOLS[@]}"; do
 done
 
 cd $SDIR
+
+echo "##################################################################################"
+echo "# Test successfully finished                                                     #"
+echo "##################################################################################"