Port Vantage to new Device/Driver/CapabilityBackend architecture #6236
rickwierengaAnnotations
16 errors
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Tests (all, py3.13)
Process completed with exit code 2.
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Tests (all, py3.9)
Process completed with exit code 2.
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Tests (all, py3.12)
Process completed with exit code 2.
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Tests (sila, py3.12)
Process completed with exit code 2.
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Tests (all, py3.14)
Process completed with exit code 2.
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Tests (modbus, py3.12)
Process completed with exit code 2.
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Tests (all, py3.10)
Process completed with exit code 2.
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Tests (<none>, py3.12)
Process completed with exit code 2.
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Tests (pico, py3.12)
Process completed with exit code 2.
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Tests (opentrons, py3.12)
Process completed with exit code 2.
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Tests (all, py3.11)
Process completed with exit code 2.
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Tests (serial, py3.12)
Process completed with exit code 2.
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Tests (usb, py3.12)
Process completed with exit code 2.
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Tests (cytation-microscopy, py3.12)
Process completed with exit code 2.
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Tests (ftdi, py3.12)
Process completed with exit code 2.
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Tests (hid, py3.12)
Process completed with exit code 2.
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