diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript index 456327087b2..218154598e7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript @@ -6,6 +6,7 @@ import os cwd = GetCurrentDir() group = [] src = [] +src += ['drv_dma.c'] path = [cwd] if GetDepend(['RT_USING_PIN']): @@ -35,7 +36,7 @@ if GetDepend('RT_USING_SOFT_SPI'): if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): src += ['drv_soft_i2c.c'] - + if GetDepend(['RT_USING_I2C']): if GetDepend('BSP_USING_HARD_I2C1') or GetDepend('BSP_USING_HARD_I2C2') or GetDepend('BSP_USING_HARD_I2C3') or GetDepend('BSP_USING_HARD_I2C4'): src += ['drv_hard_i2c.c'] diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/spi_config.h index 9e71f4e6341..8be4b43ef5f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/spi_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version * 2019-01-05 SummerGift modify DMA support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -30,24 +31,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + 0U, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + 0U, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -63,24 +94,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + 0U, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + 0U, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/uart_config.h index 392cf70306c..8c5b6efaf73 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/uart_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-10-30 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -29,13 +30,29 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ @@ -51,13 +68,29 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h index fc1f1aa2c90..ab9027cf3b1 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2024-02-06 Dyyt587 first version * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __I2C_HARD_CONFIG_H__ #define __I2C_HARD_CONFIG_H__ @@ -32,24 +33,54 @@ extern "C" { #endif /* BSP_USING_HARD_I2C1 */ #ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_PRIORITY +#define I2C1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C1_TX_DMA_PRIORITY */ + +#ifndef I2C1_TX_DMA_PREEMPT_PRIORITY +#define I2C1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C1_TX_DMA_SUB_PRIORITY +#define I2C1_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C1_TX_DMA_SUB_PRIORITY */ #ifndef I2C1_TX_DMA_CONFIG #define I2C1_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C1_TX_DMA_RCC, \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .dma_irq = I2C1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C1_TX_DMA_INSTANCE, \ + I2C1_TX_DMA_RCC, \ + I2C1_TX_DMA_IRQ, \ + I2C1_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C1_TX, \ + I2C1_TX_DMA_PRIORITY, \ + I2C1_TX_DMA_PREEMPT_PRIORITY, \ + I2C1_TX_DMA_SUB_PRIORITY) #endif /* I2C1_TX_DMA_CONFIG */ #endif /* BSP_I2C1_TX_USING_DMA */ #ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_PRIORITY +#define I2C1_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C1_RX_DMA_PRIORITY */ + +#ifndef I2C1_RX_DMA_PREEMPT_PRIORITY +#define I2C1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C1_RX_DMA_SUB_PRIORITY +#define I2C1_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C1_RX_DMA_SUB_PRIORITY */ #ifndef I2C1_RX_DMA_CONFIG #define I2C1_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C1_RX_DMA_RCC, \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .dma_irq = I2C1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C1_RX_DMA_INSTANCE, \ + I2C1_RX_DMA_RCC, \ + I2C1_RX_DMA_IRQ, \ + I2C1_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C1_RX, \ + I2C1_RX_DMA_PRIORITY, \ + I2C1_RX_DMA_PREEMPT_PRIORITY, \ + I2C1_RX_DMA_SUB_PRIORITY) #endif /* I2C1_RX_DMA_CONFIG */ #endif /* BSP_I2C1_RX_USING_DMA */ @@ -68,24 +99,54 @@ extern "C" { #endif /* BSP_USING_HARD_I2C2 */ #ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_PRIORITY +#define I2C2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C2_TX_DMA_PRIORITY */ + +#ifndef I2C2_TX_DMA_PREEMPT_PRIORITY +#define I2C2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C2_TX_DMA_SUB_PRIORITY +#define I2C2_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C2_TX_DMA_SUB_PRIORITY */ #ifndef I2C2_TX_DMA_CONFIG #define I2C2_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C2_TX_DMA_RCC, \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .dma_irq = I2C2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C2_TX_DMA_INSTANCE, \ + I2C2_TX_DMA_RCC, \ + I2C2_TX_DMA_IRQ, \ + I2C2_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C2_TX, \ + I2C2_TX_DMA_PRIORITY, \ + I2C2_TX_DMA_PREEMPT_PRIORITY, \ + I2C2_TX_DMA_SUB_PRIORITY) #endif /* I2C2_TX_DMA_CONFIG */ #endif /* BSP_I2C2_TX_USING_DMA */ #ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_PRIORITY +#define I2C2_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C2_RX_DMA_PRIORITY */ + +#ifndef I2C2_RX_DMA_PREEMPT_PRIORITY +#define I2C2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C2_RX_DMA_SUB_PRIORITY +#define I2C2_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C2_RX_DMA_SUB_PRIORITY */ #ifndef I2C2_RX_DMA_CONFIG #define I2C2_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C2_RX_DMA_RCC, \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .dma_irq = I2C2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C2_RX_DMA_INSTANCE, \ + I2C2_RX_DMA_RCC, \ + I2C2_RX_DMA_IRQ, \ + I2C2_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C2_RX, \ + I2C2_RX_DMA_PRIORITY, \ + I2C2_RX_DMA_PREEMPT_PRIORITY, \ + I2C2_RX_DMA_SUB_PRIORITY) #endif /* I2C2_RX_DMA_CONFIG */ #endif /* BSP_I2C2_RX_USING_DMA */ @@ -104,24 +165,54 @@ extern "C" { #endif /* BSP_USING_HARD_I2C3 */ #ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_PRIORITY +#define I2C3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C3_TX_DMA_PRIORITY */ + +#ifndef I2C3_TX_DMA_PREEMPT_PRIORITY +#define I2C3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C3_TX_DMA_SUB_PRIORITY +#define I2C3_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C3_TX_DMA_SUB_PRIORITY */ #ifndef I2C3_TX_DMA_CONFIG #define I2C3_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C3_TX_DMA_RCC, \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .dma_irq = I2C3_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C3_TX_DMA_INSTANCE, \ + I2C3_TX_DMA_RCC, \ + I2C3_TX_DMA_IRQ, \ + I2C3_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C3_TX, \ + I2C3_TX_DMA_PRIORITY, \ + I2C3_TX_DMA_PREEMPT_PRIORITY, \ + I2C3_TX_DMA_SUB_PRIORITY) #endif /* I2C3_TX_DMA_CONFIG */ #endif /* BSP_I2C3_TX_USING_DMA */ #ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_PRIORITY +#define I2C3_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C3_RX_DMA_PRIORITY */ + +#ifndef I2C3_RX_DMA_PREEMPT_PRIORITY +#define I2C3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C3_RX_DMA_SUB_PRIORITY +#define I2C3_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C3_RX_DMA_SUB_PRIORITY */ #ifndef I2C3_RX_DMA_CONFIG #define I2C3_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C3_RX_DMA_RCC, \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .dma_irq = I2C3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C3_RX_DMA_INSTANCE, \ + I2C3_RX_DMA_RCC, \ + I2C3_RX_DMA_IRQ, \ + I2C3_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C3_RX, \ + I2C3_RX_DMA_PRIORITY, \ + I2C3_RX_DMA_PREEMPT_PRIORITY, \ + I2C3_RX_DMA_SUB_PRIORITY) #endif /* I2C3_RX_DMA_CONFIG */ #endif /* BSP_I2C3_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/sdio_config.h index 22437ef8f63..595143189a0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/sdio_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-13 BalanceTWK first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SDIO_CONFIG_H__ @@ -19,15 +20,51 @@ extern "C" { #endif #ifdef BSP_USING_SDIO +#ifndef SDIO_RX_DMA_PRIORITY +#define SDIO_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_RX_DMA_PRIORITY */ + +#ifndef SDIO_RX_DMA_PREEMPT_PRIORITY +#define SDIO_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_RX_DMA_SUB_PRIORITY +#define SDIO_RX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_RX_DMA_SUB_PRIORITY */ + +#ifndef SDIO_TX_DMA_PRIORITY +#define SDIO_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_TX_DMA_PRIORITY */ + +#ifndef SDIO_TX_DMA_PREEMPT_PRIORITY +#define SDIO_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_TX_DMA_SUB_PRIORITY +#define SDIO_TX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_TX_DMA_SUB_PRIORITY */ + #define SDIO_BUS_CONFIG \ { \ - .Instance = SDIO, \ - .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Channel4, \ - .dma_rx.dma_irq = DMA2_Channel4_IRQn, \ - .dma_tx.Instance = DMA2_Channel4, \ - .dma_tx.dma_irq = DMA2_Channel4_IRQn, \ + .Instance = SDIO, \ + .dma_rx = STM32_DMA_RX_WORD_CONFIG_INIT_EX( \ + DMA2_Channel4, \ + RCC_AHBENR_DMA2EN, \ + DMA2_Channel4_IRQn, \ + 0U, \ + 0U, \ + SDIO_RX_DMA_PRIORITY, \ + SDIO_RX_DMA_PREEMPT_PRIORITY, \ + SDIO_RX_DMA_SUB_PRIORITY), \ + .dma_tx = STM32_DMA_TX_WORD_CONFIG_INIT_EX( \ + DMA2_Channel4, \ + RCC_AHBENR_DMA2EN, \ + DMA2_Channel4_IRQn, \ + 0U, \ + 0U, \ + SDIO_TX_DMA_PRIORITY, \ + SDIO_TX_DMA_PREEMPT_PRIORITY, \ + SDIO_TX_DMA_SUB_PRIORITY), \ } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/spi_config.h index bd98277cf30..3d53ef8520c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/spi_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version * 2019-01-05 SummerGift modify DMA support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -30,24 +31,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + 0U, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + 0U, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -63,24 +94,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + 0U, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + 0U, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -96,24 +157,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + 0U, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG #define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + 0U, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/uart_config.h index 540f5071f55..ae4ba29b626 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/uart_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-10-30 BalanceTWK first version * 2019-01-05 SummerGift modify DMA support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -30,24 +31,56 @@ extern "C" { #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG #define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG #define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ #endif /* BSP_USING_UART1 */ @@ -63,24 +96,56 @@ extern "C" { #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG #define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG #define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ #endif /* BSP_USING_UART2 */ @@ -96,24 +161,56 @@ extern "C" { #endif /* UART3_CONFIG */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG #define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG #define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ #endif /* BSP_USING_UART3 */ @@ -129,24 +226,56 @@ extern "C" { #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_RX_DMA_PRIORITY +#define UART4_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_RX_DMA_PRIORITY */ + +#ifndef UART4_RX_DMA_PREEMPT_PRIORITY +#define UART4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_RX_DMA_SUB_PRIORITY +#define UART4_RX_DMA_SUB_PRIORITY 0 +#endif /* UART4_RX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_RX_CONFIG #define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .dma_rcc = UART4_RX_DMA_RCC, \ - .dma_irq = UART4_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART4_RX_DMA_INSTANCE, \ + UART4_RX_DMA_RCC, \ + UART4_RX_DMA_IRQ, \ + UART4_RX_DMA_CHANNEL, \ + UART4_RX_DMA_REQUEST, \ + UART4_RX_DMA_PRIORITY, \ + UART4_RX_DMA_PREEMPT_PRIORITY, \ + UART4_RX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_RX_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_TX_DMA_PRIORITY +#define UART4_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_TX_DMA_PRIORITY */ + +#ifndef UART4_TX_DMA_PREEMPT_PRIORITY +#define UART4_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_TX_DMA_SUB_PRIORITY +#define UART4_TX_DMA_SUB_PRIORITY 0 +#endif /* UART4_TX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_TX_CONFIG #define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .dma_rcc = UART4_TX_DMA_RCC, \ - .dma_irq = UART4_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART4_TX_DMA_INSTANCE, \ + UART4_TX_DMA_RCC, \ + UART4_TX_DMA_IRQ, \ + UART4_TX_DMA_CHANNEL, \ + UART4_TX_DMA_REQUEST, \ + UART4_TX_DMA_PRIORITY, \ + UART4_TX_DMA_PREEMPT_PRIORITY, \ + UART4_TX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_TX_CONFIG */ #endif /* BSP_UART4_TX_USING_DMA */ #endif /* BSP_USING_UART4 */ @@ -163,11 +292,29 @@ extern "C" { #endif /* BSP_USING_UART5 */ #if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_RX_DMA_PRIORITY +#define UART5_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_RX_DMA_PRIORITY */ + +#ifndef UART5_RX_DMA_PREEMPT_PRIORITY +#define UART5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_RX_DMA_SUB_PRIORITY +#define UART5_RX_DMA_SUB_PRIORITY 0 +#endif /* UART5_RX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = DMA_NOT_AVAILABLE, \ - } +#define UART5_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART5_RX_DMA_INSTANCE, \ + UART5_RX_DMA_RCC, \ + UART5_RX_DMA_IRQ, \ + UART5_RX_DMA_CHANNEL, \ + UART5_RX_DMA_REQUEST, \ + UART5_RX_DMA_PRIORITY, \ + UART5_RX_DMA_PREEMPT_PRIORITY, \ + UART5_RX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/sdio_config.h index 437bc46591c..e3f14b260b6 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/sdio_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-13 BalanceTWK first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SDIO_CONFIG_H__ @@ -19,17 +20,71 @@ extern "C" { #endif #ifdef BSP_USING_SDIO +#ifndef SDIO_RX_DMA_PRIORITY +#define SDIO_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_RX_DMA_PRIORITY */ + +#ifndef SDIO_RX_DMA_PREEMPT_PRIORITY +#define SDIO_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_RX_DMA_SUB_PRIORITY +#define SDIO_RX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_RX_DMA_SUB_PRIORITY */ + +#ifndef SDIO_TX_DMA_PRIORITY +#define SDIO_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_TX_DMA_PRIORITY */ + +#ifndef SDIO_TX_DMA_PREEMPT_PRIORITY +#define SDIO_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_TX_DMA_SUB_PRIORITY +#define SDIO_TX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_TX_DMA_SUB_PRIORITY */ + #define SDIO_BUS_CONFIG \ { \ - .Instance = SDIO, \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_4, \ - .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ - .dma_tx.Instance = DMA2_Stream6, \ - .dma_tx.channel = DMA_CHANNEL_4, \ - .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + .Instance = SDIO, \ + .dma_rx = STM32_DMA_CONFIG_INIT_FIFO_EX( \ + DMA2_Stream3, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Stream3_IRQn, \ + DMA_CHANNEL_4, \ + 0U, \ + SDIO_RX_DMA_PRIORITY, \ + SDIO_RX_DMA_PREEMPT_PRIORITY, \ + SDIO_RX_DMA_SUB_PRIORITY, \ + DMA_PERIPH_TO_MEMORY, \ + DMA_PINC_DISABLE, \ + DMA_MINC_ENABLE, \ + DMA_PDATAALIGN_WORD, \ + DMA_MDATAALIGN_WORD, \ + DMA_PFCTRL, \ + DMA_FIFOMODE_ENABLE, \ + DMA_FIFO_THRESHOLD_FULL, \ + DMA_MBURST_INC4, \ + DMA_PBURST_INC4), \ + .dma_tx = STM32_DMA_CONFIG_INIT_FIFO_EX( \ + DMA2_Stream6, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Stream6_IRQn, \ + DMA_CHANNEL_4, \ + 0U, \ + SDIO_TX_DMA_PRIORITY, \ + SDIO_TX_DMA_PREEMPT_PRIORITY, \ + SDIO_TX_DMA_SUB_PRIORITY, \ + DMA_MEMORY_TO_PERIPH, \ + DMA_PINC_DISABLE, \ + DMA_MINC_ENABLE, \ + DMA_PDATAALIGN_WORD, \ + DMA_MDATAALIGN_WORD, \ + DMA_PFCTRL, \ + DMA_FIFOMODE_ENABLE, \ + DMA_FIFO_THRESHOLD_FULL, \ + DMA_MBURST_INC4, \ + DMA_PBURST_INC4), \ } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/spi_config.h index dc9db0a226f..3d53ef8520c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/spi_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version * 2019-01-05 SummerGift modify DMA support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -30,26 +31,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + 0U, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + 0U, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -65,26 +94,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .channel = SPI2_TX_DMA_CHANNEL, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + 0U, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .channel = SPI2_RX_DMA_CHANNEL, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + 0U, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -100,26 +157,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .channel = SPI3_TX_DMA_CHANNEL, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + 0U, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG #define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .channel = SPI3_RX_DMA_CHANNEL, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + 0U, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/uart_config.h index 3e06c4dac37..9a3a8fe9a24 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/uart_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version * 2019-01-03 zylx modify dma support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -29,26 +30,56 @@ extern "C" { #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } +#define UART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ #endif /* BSP_USING_UART1 */ @@ -64,26 +95,56 @@ extern "C" { #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } +#define UART2_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ #endif /* BSP_USING_UART2 */ @@ -99,26 +160,56 @@ extern "C" { #endif /* UART3_CONFIG */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .channel = UART3_RX_DMA_CHANNEL, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .channel = UART3_TX_DMA_CHANNEL, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } +#define UART3_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ #endif /* BSP_USING_UART3 */ @@ -134,28 +225,58 @@ extern "C" { #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_RX_DMA_PRIORITY +#define UART4_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_RX_DMA_PRIORITY */ + +#ifndef UART4_RX_DMA_PREEMPT_PRIORITY +#define UART4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_RX_DMA_SUB_PRIORITY +#define UART4_RX_DMA_SUB_PRIORITY 0 +#endif /* UART4_RX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .channel = UART4_RX_DMA_CHANNEL, \ - .dma_rcc = UART4_RX_DMA_RCC, \ - .dma_irq = UART4_RX_DMA_IRQ, \ - } +#define UART4_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART4_RX_DMA_INSTANCE, \ + UART4_RX_DMA_RCC, \ + UART4_RX_DMA_IRQ, \ + UART4_RX_DMA_CHANNEL, \ + UART4_RX_DMA_REQUEST, \ + UART4_RX_DMA_PRIORITY, \ + UART4_RX_DMA_PREEMPT_PRIORITY, \ + UART4_RX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_RX_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_TX_DMA_PRIORITY +#define UART4_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_TX_DMA_PRIORITY */ + +#ifndef UART4_TX_DMA_PREEMPT_PRIORITY +#define UART4_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_TX_DMA_SUB_PRIORITY +#define UART4_TX_DMA_SUB_PRIORITY 0 +#endif /* UART4_TX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_TX_CONFIG -#define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .channel = UART4_TX_DMA_CHANNEL, \ - .dma_rcc = UART4_TX_DMA_RCC, \ - .dma_irq = UART4_TX_DMA_IRQ, \ - } +#define UART4_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART4_TX_DMA_INSTANCE, \ + UART4_TX_DMA_RCC, \ + UART4_TX_DMA_IRQ, \ + UART4_TX_DMA_CHANNEL, \ + UART4_TX_DMA_REQUEST, \ + UART4_TX_DMA_PRIORITY, \ + UART4_TX_DMA_PREEMPT_PRIORITY, \ + UART4_TX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_TX_CONFIG */ -#endif /* BSP_UART4_RX_USING_DMA */ +#endif /* BSP_UART4_TX_USING_DMA */ #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_UART5) @@ -169,26 +290,56 @@ extern "C" { #endif /* UART5_CONFIG */ #if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_RX_DMA_PRIORITY +#define UART5_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_RX_DMA_PRIORITY */ + +#ifndef UART5_RX_DMA_PREEMPT_PRIORITY +#define UART5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_RX_DMA_SUB_PRIORITY +#define UART5_RX_DMA_SUB_PRIORITY 0 +#endif /* UART5_RX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .channel = UART5_RX_DMA_CHANNEL, \ - .dma_rcc = UART5_RX_DMA_RCC, \ - .dma_irq = UART5_RX_DMA_IRQ, \ - } +#define UART5_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART5_RX_DMA_INSTANCE, \ + UART5_RX_DMA_RCC, \ + UART5_RX_DMA_IRQ, \ + UART5_RX_DMA_CHANNEL, \ + UART5_RX_DMA_REQUEST, \ + UART5_RX_DMA_PRIORITY, \ + UART5_RX_DMA_PREEMPT_PRIORITY, \ + UART5_RX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ #if defined(BSP_UART5_TX_USING_DMA) +#ifndef UART5_TX_DMA_PRIORITY +#define UART5_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_TX_DMA_PRIORITY */ + +#ifndef UART5_TX_DMA_PREEMPT_PRIORITY +#define UART5_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_TX_DMA_SUB_PRIORITY +#define UART5_TX_DMA_SUB_PRIORITY 0 +#endif /* UART5_TX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_TX_CONFIG -#define UART5_DMA_TX_CONFIG \ - { \ - .Instance = UART5_TX_DMA_INSTANCE, \ - .channel = UART5_TX_DMA_CHANNEL, \ - .dma_rcc = UART5_TX_DMA_RCC, \ - .dma_irq = UART5_TX_DMA_IRQ, \ - } +#define UART5_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART5_TX_DMA_INSTANCE, \ + UART5_TX_DMA_RCC, \ + UART5_TX_DMA_IRQ, \ + UART5_TX_DMA_CHANNEL, \ + UART5_TX_DMA_REQUEST, \ + UART5_TX_DMA_PRIORITY, \ + UART5_TX_DMA_PREEMPT_PRIORITY, \ + UART5_TX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_TX_CONFIG */ #endif /* BSP_UART5_TX_USING_DMA */ #endif /* BSP_USING_UART5 */ @@ -204,26 +355,56 @@ extern "C" { #endif /* UART6_CONFIG */ #if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_RX_DMA_PRIORITY +#define UART6_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART6_RX_DMA_PRIORITY */ + +#ifndef UART6_RX_DMA_PREEMPT_PRIORITY +#define UART6_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART6_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART6_RX_DMA_SUB_PRIORITY +#define UART6_RX_DMA_SUB_PRIORITY 0 +#endif /* UART6_RX_DMA_SUB_PRIORITY */ + #ifndef UART6_DMA_RX_CONFIG -#define UART6_DMA_RX_CONFIG \ - { \ - .Instance = UART6_RX_DMA_INSTANCE, \ - .channel = UART6_RX_DMA_CHANNEL, \ - .dma_rcc = UART6_RX_DMA_RCC, \ - .dma_irq = UART6_RX_DMA_IRQ, \ - } +#define UART6_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART6_RX_DMA_INSTANCE, \ + UART6_RX_DMA_RCC, \ + UART6_RX_DMA_IRQ, \ + UART6_RX_DMA_CHANNEL, \ + UART6_RX_DMA_REQUEST, \ + UART6_RX_DMA_PRIORITY, \ + UART6_RX_DMA_PREEMPT_PRIORITY, \ + UART6_RX_DMA_SUB_PRIORITY) #endif /* UART6_DMA_RX_CONFIG */ #endif /* BSP_UART6_RX_USING_DMA */ #if defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_TX_DMA_PRIORITY +#define UART6_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART6_TX_DMA_PRIORITY */ + +#ifndef UART6_TX_DMA_PREEMPT_PRIORITY +#define UART6_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART6_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART6_TX_DMA_SUB_PRIORITY +#define UART6_TX_DMA_SUB_PRIORITY 0 +#endif /* UART6_TX_DMA_SUB_PRIORITY */ + #ifndef UART6_DMA_TX_CONFIG -#define UART6_DMA_TX_CONFIG \ - { \ - .Instance = UART6_TX_DMA_INSTANCE, \ - .channel = UART6_TX_DMA_CHANNEL, \ - .dma_rcc = UART6_TX_DMA_RCC, \ - .dma_irq = UART6_TX_DMA_IRQ, \ - } +#define UART6_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART6_TX_DMA_INSTANCE, \ + UART6_TX_DMA_RCC, \ + UART6_TX_DMA_IRQ, \ + UART6_TX_DMA_CHANNEL, \ + UART6_TX_DMA_REQUEST, \ + UART6_TX_DMA_PRIORITY, \ + UART6_TX_DMA_PREEMPT_PRIORITY, \ + UART6_TX_DMA_SUB_PRIORITY) #endif /* UART6_DMA_TX_CONFIG */ #endif /* BSP_UART6_TX_USING_DMA */ #endif /* BSP_USING_UART6 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/uart_config.h index 6777c852737..57a86fbeddb 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/uart_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version * 2019-01-03 zylx modify dma support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -29,26 +30,56 @@ extern "C" { #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } +#define UART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ #endif /* BSP_USING_UART1 */ @@ -64,26 +95,56 @@ extern "C" { #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } +#define UART2_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ #endif /* BSP_USING_UART2 */ @@ -99,26 +160,56 @@ extern "C" { #endif /* UART3_CONFIG */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .channel = UART3_RX_DMA_CHANNEL, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .channel = UART3_TX_DMA_CHANNEL, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } +#define UART3_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ #endif /* BSP_USING_UART3 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h index c1111d5ecfc..412a9427290 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h @@ -8,6 +8,7 @@ * 2024-02-06 Dyyt587 first version * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG * 2024-06-23 wdfk-prog Add I2C4 config entries + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __I2C_HARD_CONFIG_H__ #define __I2C_HARD_CONFIG_H__ @@ -33,46 +34,56 @@ extern "C" { #endif /* BSP_USING_HARD_I2C1 */ #ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_PRIORITY +#define I2C1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C1_TX_DMA_PRIORITY */ + +#ifndef I2C1_TX_DMA_PREEMPT_PRIORITY +#define I2C1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C1_TX_DMA_SUB_PRIORITY +#define I2C1_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C1_TX_DMA_SUB_PRIORITY */ + #ifndef I2C1_TX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define I2C1_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C1_TX_DMA_RCC, \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .dma_irq = I2C1_TX_DMA_IRQ, \ - .channel = I2C1_TX_DMA_CHANNEL \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) -#define I2C1_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C1_TX_DMA_RCC, \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .dma_irq = I2C1_TX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C1_TX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C1_TX_DMA_INSTANCE, \ + I2C1_TX_DMA_RCC, \ + I2C1_TX_DMA_IRQ, \ + I2C1_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C1_TX, \ + I2C1_TX_DMA_PRIORITY, \ + I2C1_TX_DMA_PREEMPT_PRIORITY, \ + I2C1_TX_DMA_SUB_PRIORITY) #endif /* I2C1_TX_DMA_CONFIG */ #endif /* BSP_I2C1_TX_USING_DMA */ #ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_PRIORITY +#define I2C1_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C1_RX_DMA_PRIORITY */ + +#ifndef I2C1_RX_DMA_PREEMPT_PRIORITY +#define I2C1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C1_RX_DMA_SUB_PRIORITY +#define I2C1_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C1_RX_DMA_SUB_PRIORITY */ + #ifndef I2C1_RX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) -#define I2C1_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C1_RX_DMA_RCC, \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .dma_irq = I2C1_RX_DMA_IRQ, \ - .channel = I2C1_RX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) #define I2C1_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C1_RX_DMA_RCC, \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .dma_irq = I2C1_RX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C1_RX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C1_RX_DMA_INSTANCE, \ + I2C1_RX_DMA_RCC, \ + I2C1_RX_DMA_IRQ, \ + I2C1_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C1_RX, \ + I2C1_RX_DMA_PRIORITY, \ + I2C1_RX_DMA_PREEMPT_PRIORITY, \ + I2C1_RX_DMA_SUB_PRIORITY) #endif /* I2C1_RX_DMA_CONFIG */ #endif /* BSP_I2C1_RX_USING_DMA */ @@ -91,46 +102,56 @@ extern "C" { #endif /* BSP_USING_HARD_I2C2 */ #ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_PRIORITY +#define I2C2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C2_TX_DMA_PRIORITY */ + +#ifndef I2C2_TX_DMA_PREEMPT_PRIORITY +#define I2C2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C2_TX_DMA_SUB_PRIORITY +#define I2C2_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C2_TX_DMA_SUB_PRIORITY */ + #ifndef I2C2_TX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) -#define I2C2_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C2_TX_DMA_RCC, \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .dma_irq = I2C2_TX_DMA_IRQ, \ - .channel = I2C2_TX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) #define I2C2_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C2_TX_DMA_RCC, \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .dma_irq = I2C2_TX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C2_TX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C2_TX_DMA_INSTANCE, \ + I2C2_TX_DMA_RCC, \ + I2C2_TX_DMA_IRQ, \ + I2C2_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C2_TX, \ + I2C2_TX_DMA_PRIORITY, \ + I2C2_TX_DMA_PREEMPT_PRIORITY, \ + I2C2_TX_DMA_SUB_PRIORITY) #endif /* I2C2_TX_DMA_CONFIG */ #endif /* BSP_I2C2_TX_USING_DMA */ #ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_PRIORITY +#define I2C2_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C2_RX_DMA_PRIORITY */ + +#ifndef I2C2_RX_DMA_PREEMPT_PRIORITY +#define I2C2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C2_RX_DMA_SUB_PRIORITY +#define I2C2_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C2_RX_DMA_SUB_PRIORITY */ + #ifndef I2C2_RX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) -#define I2C2_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C2_RX_DMA_RCC, \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .dma_irq = I2C2_RX_DMA_IRQ, \ - .channel = I2C2_RX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) #define I2C2_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C2_RX_DMA_RCC, \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .dma_irq = I2C2_RX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C2_RX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C2_RX_DMA_INSTANCE, \ + I2C2_RX_DMA_RCC, \ + I2C2_RX_DMA_IRQ, \ + I2C2_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C2_RX, \ + I2C2_RX_DMA_PRIORITY, \ + I2C2_RX_DMA_PREEMPT_PRIORITY, \ + I2C2_RX_DMA_SUB_PRIORITY) #endif /* I2C2_RX_DMA_CONFIG */ #endif /* BSP_I2C2_RX_USING_DMA */ @@ -149,46 +170,56 @@ extern "C" { #endif /* BSP_USING_HARD_I2C3 */ #ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_PRIORITY +#define I2C3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C3_TX_DMA_PRIORITY */ + +#ifndef I2C3_TX_DMA_PREEMPT_PRIORITY +#define I2C3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C3_TX_DMA_SUB_PRIORITY +#define I2C3_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C3_TX_DMA_SUB_PRIORITY */ + #ifndef I2C3_TX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) -#define I2C3_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C3_TX_DMA_RCC, \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .dma_irq = I2C3_TX_DMA_IRQ, \ - .channel = I2C3_TX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) #define I2C3_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C3_TX_DMA_RCC, \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .dma_irq = I2C3_TX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C3_TX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C3_TX_DMA_INSTANCE, \ + I2C3_TX_DMA_RCC, \ + I2C3_TX_DMA_IRQ, \ + I2C3_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C3_TX, \ + I2C3_TX_DMA_PRIORITY, \ + I2C3_TX_DMA_PREEMPT_PRIORITY, \ + I2C3_TX_DMA_SUB_PRIORITY) #endif /* I2C3_TX_DMA_CONFIG */ #endif /* BSP_I2C3_TX_USING_DMA */ #ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_PRIORITY +#define I2C3_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C3_RX_DMA_PRIORITY */ + +#ifndef I2C3_RX_DMA_PREEMPT_PRIORITY +#define I2C3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C3_RX_DMA_SUB_PRIORITY +#define I2C3_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C3_RX_DMA_SUB_PRIORITY */ + #ifndef I2C3_RX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) -#define I2C3_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C3_RX_DMA_RCC, \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .dma_irq = I2C3_RX_DMA_IRQ, \ - .channel = I2C3_RX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) #define I2C3_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C3_RX_DMA_RCC, \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .dma_irq = I2C3_RX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C3_RX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C3_RX_DMA_INSTANCE, \ + I2C3_RX_DMA_RCC, \ + I2C3_RX_DMA_IRQ, \ + I2C3_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C3_RX, \ + I2C3_RX_DMA_PRIORITY, \ + I2C3_RX_DMA_PREEMPT_PRIORITY, \ + I2C3_RX_DMA_SUB_PRIORITY) #endif /* I2C3_RX_DMA_CONFIG */ #endif /* BSP_I2C3_RX_USING_DMA */ @@ -198,7 +229,7 @@ extern "C" { { \ .Instance = I2C4, \ .timing = 100000, \ - .timeout = 0x1000, \ + .timeout=0x1000, \ .name = "hwi2c4", \ .evirq_type = I2C4_EV_IRQn, \ .erirq_type = I2C4_ER_IRQn, \ @@ -207,46 +238,56 @@ extern "C" { #endif /* BSP_USING_HARD_I2C4 */ #ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_PRIORITY +#define I2C4_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C4_TX_DMA_PRIORITY */ + +#ifndef I2C4_TX_DMA_PREEMPT_PRIORITY +#define I2C4_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C4_TX_DMA_SUB_PRIORITY +#define I2C4_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C4_TX_DMA_SUB_PRIORITY */ + #ifndef I2C4_TX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) -#define I2C4_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C4_TX_DMA_RCC, \ - .Instance = I2C4_TX_DMA_INSTANCE, \ - .dma_irq = I2C4_TX_DMA_IRQ, \ - .channel = I2C4_TX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) #define I2C4_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C4_TX_DMA_RCC, \ - .Instance = I2C4_TX_DMA_INSTANCE, \ - .dma_irq = I2C4_TX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C4_TX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C4_TX_DMA_INSTANCE, \ + I2C4_TX_DMA_RCC, \ + I2C4_TX_DMA_IRQ, \ + I2C4_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C4_TX, \ + I2C4_TX_DMA_PRIORITY, \ + I2C4_TX_DMA_PREEMPT_PRIORITY, \ + I2C4_TX_DMA_SUB_PRIORITY) #endif /* I2C4_TX_DMA_CONFIG */ #endif /* BSP_I2C4_TX_USING_DMA */ #ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_PRIORITY +#define I2C4_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C4_RX_DMA_PRIORITY */ + +#ifndef I2C4_RX_DMA_PREEMPT_PRIORITY +#define I2C4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C4_RX_DMA_SUB_PRIORITY +#define I2C4_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C4_RX_DMA_SUB_PRIORITY */ + #ifndef I2C4_RX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) -#define I2C4_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C4_RX_DMA_RCC, \ - .Instance = I2C4_RX_DMA_INSTANCE, \ - .dma_irq = I2C4_RX_DMA_IRQ, \ - .channel = I2C4_RX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) #define I2C4_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C4_RX_DMA_RCC, \ - .Instance = I2C4_RX_DMA_INSTANCE, \ - .dma_irq = I2C4_RX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C4_RX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C4_RX_DMA_INSTANCE, \ + I2C4_RX_DMA_RCC, \ + I2C4_RX_DMA_IRQ, \ + I2C4_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C4_RX, \ + I2C4_RX_DMA_PRIORITY, \ + I2C4_RX_DMA_PREEMPT_PRIORITY, \ + I2C4_RX_DMA_SUB_PRIORITY) #endif /* I2C4_RX_DMA_CONFIG */ #endif /* BSP_I2C4_RX_USING_DMA */ @@ -254,4 +295,4 @@ extern "C" { } #endif -#endif /*__I2C_CONFIG_H__ */ +#endif /* __I2C_HARD_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/qspi_config.h index 6c986bba124..f541796956b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/qspi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-22 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __QSPI_CONFIG_H__ @@ -30,19 +31,29 @@ extern "C" { #endif /* BSP_USING_QSPI */ #ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_PRIORITY +#define QSPI_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* QSPI_DMA_PRIORITY */ + +#ifndef QSPI_DMA_PREEMPT_PRIORITY +#define QSPI_DMA_PREEMPT_PRIORITY 0 +#endif /* QSPI_DMA_PREEMPT_PRIORITY */ + +#ifndef QSPI_DMA_SUB_PRIORITY +#define QSPI_DMA_SUB_PRIORITY 0 +#endif /* QSPI_DMA_SUB_PRIORITY */ + #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .Init.Channel = QSPI_DMA_CHANNEL, \ - .Init.Direction = DMA_PERIPH_TO_MEMORY, \ - .Init.PeriphInc = DMA_PINC_DISABLE, \ - .Init.MemInc = DMA_MINC_ENABLE, \ - .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ - .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ - .Init.Mode = DMA_NORMAL, \ - .Init.Priority = DMA_PRIORITY_LOW \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + QSPI_DMA_INSTANCE, \ + QSPI_DMA_RCC, \ + QSPI_DMA_IRQ, \ + QSPI_DMA_CHANNEL, \ + 0U, \ + QSPI_DMA_PRIORITY, \ + QSPI_DMA_PREEMPT_PRIORITY, \ + QSPI_DMA_SUB_PRIORITY) #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/sdio_config.h index eb209fa2c2d..a9fcb84312e 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/sdio_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-13 BalanceTWK first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SDIO_CONFIG_H__ @@ -19,17 +20,71 @@ extern "C" { #endif #ifdef BSP_USING_SDIO +#ifndef SDIO_RX_DMA_PRIORITY +#define SDIO_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_RX_DMA_PRIORITY */ + +#ifndef SDIO_RX_DMA_PREEMPT_PRIORITY +#define SDIO_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_RX_DMA_SUB_PRIORITY +#define SDIO_RX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_RX_DMA_SUB_PRIORITY */ + +#ifndef SDIO_TX_DMA_PRIORITY +#define SDIO_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_TX_DMA_PRIORITY */ + +#ifndef SDIO_TX_DMA_PREEMPT_PRIORITY +#define SDIO_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_TX_DMA_SUB_PRIORITY +#define SDIO_TX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_TX_DMA_SUB_PRIORITY */ + #define SDIO_BUS_CONFIG \ { \ - .Instance = SDIO, \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_4, \ - .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ - .dma_tx.Instance = DMA2_Stream6, \ - .dma_tx.channel = DMA_CHANNEL_4, \ - .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + .Instance = SDIO, \ + .dma_rx = STM32_DMA_CONFIG_INIT_FIFO_EX( \ + DMA2_Stream3, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Stream3_IRQn, \ + DMA_CHANNEL_4, \ + 0U, \ + SDIO_RX_DMA_PRIORITY, \ + SDIO_RX_DMA_PREEMPT_PRIORITY, \ + SDIO_RX_DMA_SUB_PRIORITY, \ + DMA_PERIPH_TO_MEMORY, \ + DMA_PINC_DISABLE, \ + DMA_MINC_ENABLE, \ + DMA_PDATAALIGN_WORD, \ + DMA_MDATAALIGN_WORD, \ + DMA_PFCTRL, \ + DMA_FIFOMODE_ENABLE, \ + DMA_FIFO_THRESHOLD_FULL, \ + DMA_MBURST_INC4, \ + DMA_PBURST_INC4), \ + .dma_tx = STM32_DMA_CONFIG_INIT_FIFO_EX( \ + DMA2_Stream6, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Stream6_IRQn, \ + DMA_CHANNEL_4, \ + 0U, \ + SDIO_TX_DMA_PRIORITY, \ + SDIO_TX_DMA_PREEMPT_PRIORITY, \ + SDIO_TX_DMA_SUB_PRIORITY, \ + DMA_MEMORY_TO_PERIPH, \ + DMA_PINC_DISABLE, \ + DMA_MINC_ENABLE, \ + DMA_PDATAALIGN_WORD, \ + DMA_MDATAALIGN_WORD, \ + DMA_PFCTRL, \ + DMA_FIFOMODE_ENABLE, \ + DMA_FIFO_THRESHOLD_FULL, \ + DMA_MBURST_INC4, \ + DMA_PBURST_INC4), \ } #endif @@ -39,6 +94,3 @@ extern "C" { #endif #endif /*__SDIO_CONFIG_H__ */ - - - diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/spi_config.h index 2375b3cd5bd..e2e659bce0f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/spi_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version * 2019-01-03 zylx modify DMA support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -30,26 +31,56 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ + #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + 0U, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ + #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + 0U, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -65,26 +96,56 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ + #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .channel = SPI2_TX_DMA_CHANNEL, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + 0U, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ + #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .channel = SPI2_RX_DMA_CHANNEL, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + 0U, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -100,26 +161,56 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ + #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .channel = SPI3_TX_DMA_CHANNEL, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + 0U, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ + #ifndef SPI3_RX_DMA_CONFIG #define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .channel = SPI3_RX_DMA_CHANNEL, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + 0U, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ @@ -135,26 +226,56 @@ extern "C" { #endif /* BSP_USING_SPI4 */ #ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_PRIORITY +#define SPI4_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI4_TX_DMA_PRIORITY */ + +#ifndef SPI4_TX_DMA_PREEMPT_PRIORITY +#define SPI4_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_TX_DMA_SUB_PRIORITY +#define SPI4_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_TX_DMA_SUB_PRIORITY */ + #ifndef SPI4_TX_DMA_CONFIG #define SPI4_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI4_TX_DMA_RCC, \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .channel = SPI4_TX_DMA_CHANNEL, \ - .dma_irq = SPI4_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI4_TX_DMA_INSTANCE, \ + SPI4_TX_DMA_RCC, \ + SPI4_TX_DMA_IRQ, \ + SPI4_TX_DMA_CHANNEL, \ + 0U, \ + SPI4_TX_DMA_PRIORITY, \ + SPI4_TX_DMA_PREEMPT_PRIORITY, \ + SPI4_TX_DMA_SUB_PRIORITY) #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ #ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_PRIORITY +#define SPI4_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI4_RX_DMA_PRIORITY */ + +#ifndef SPI4_RX_DMA_PREEMPT_PRIORITY +#define SPI4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_RX_DMA_SUB_PRIORITY +#define SPI4_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_RX_DMA_SUB_PRIORITY */ + #ifndef SPI4_RX_DMA_CONFIG #define SPI4_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI4_RX_DMA_RCC, \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .channel = SPI4_RX_DMA_CHANNEL, \ - .dma_irq = SPI4_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI4_RX_DMA_INSTANCE, \ + SPI4_RX_DMA_RCC, \ + SPI4_RX_DMA_IRQ, \ + SPI4_RX_DMA_CHANNEL, \ + 0U, \ + SPI4_RX_DMA_PRIORITY, \ + SPI4_RX_DMA_PREEMPT_PRIORITY, \ + SPI4_RX_DMA_SUB_PRIORITY) #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ @@ -170,29 +291,124 @@ extern "C" { #endif /* BSP_USING_SPI5 */ #ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_PRIORITY +#define SPI5_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI5_TX_DMA_PRIORITY */ + +#ifndef SPI5_TX_DMA_PREEMPT_PRIORITY +#define SPI5_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI5_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_TX_DMA_SUB_PRIORITY +#define SPI5_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_TX_DMA_SUB_PRIORITY */ + #ifndef SPI5_TX_DMA_CONFIG #define SPI5_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI5_TX_DMA_RCC, \ - .Instance = SPI5_TX_DMA_INSTANCE, \ - .channel = SPI5_TX_DMA_CHANNEL, \ - .dma_irq = SPI5_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI5_TX_DMA_INSTANCE, \ + SPI5_TX_DMA_RCC, \ + SPI5_TX_DMA_IRQ, \ + SPI5_TX_DMA_CHANNEL, \ + 0U, \ + SPI5_TX_DMA_PRIORITY, \ + SPI5_TX_DMA_PREEMPT_PRIORITY, \ + SPI5_TX_DMA_SUB_PRIORITY) #endif /* SPI5_TX_DMA_CONFIG */ #endif /* BSP_SPI5_TX_USING_DMA */ #ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_PRIORITY +#define SPI5_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI5_RX_DMA_PRIORITY */ + +#ifndef SPI5_RX_DMA_PREEMPT_PRIORITY +#define SPI5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_RX_DMA_SUB_PRIORITY +#define SPI5_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_RX_DMA_SUB_PRIORITY */ + #ifndef SPI5_RX_DMA_CONFIG #define SPI5_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI5_RX_DMA_RCC, \ - .Instance = SPI5_RX_DMA_INSTANCE, \ - .channel = SPI5_RX_DMA_CHANNEL, \ - .dma_irq = SPI5_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI5_RX_DMA_INSTANCE, \ + SPI5_RX_DMA_RCC, \ + SPI5_RX_DMA_IRQ, \ + SPI5_RX_DMA_CHANNEL, \ + 0U, \ + SPI5_RX_DMA_PRIORITY, \ + SPI5_RX_DMA_PREEMPT_PRIORITY, \ + SPI5_RX_DMA_SUB_PRIORITY) #endif /* SPI5_RX_DMA_CONFIG */ #endif /* BSP_SPI5_RX_USING_DMA */ +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .Instance = SPI6, \ + .bus_name = "spi6", \ + .irq_type = SPI6_IRQn, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_PRIORITY +#define SPI6_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI6_TX_DMA_PRIORITY */ + +#ifndef SPI6_TX_DMA_PREEMPT_PRIORITY +#define SPI6_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI6_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI6_TX_DMA_SUB_PRIORITY +#define SPI6_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI6_TX_DMA_SUB_PRIORITY */ + +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI6_TX_DMA_INSTANCE, \ + SPI6_TX_DMA_RCC, \ + SPI6_TX_DMA_IRQ, \ + SPI6_TX_DMA_CHANNEL, \ + 0U, \ + SPI6_TX_DMA_PRIORITY, \ + SPI6_TX_DMA_PREEMPT_PRIORITY, \ + SPI6_TX_DMA_SUB_PRIORITY) +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ + +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_PRIORITY +#define SPI6_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI6_RX_DMA_PRIORITY */ + +#ifndef SPI6_RX_DMA_PREEMPT_PRIORITY +#define SPI6_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI6_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI6_RX_DMA_SUB_PRIORITY +#define SPI6_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI6_RX_DMA_SUB_PRIORITY */ + +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI6_RX_DMA_INSTANCE, \ + SPI6_RX_DMA_RCC, \ + SPI6_RX_DMA_IRQ, \ + SPI6_RX_DMA_CHANNEL, \ + 0U, \ + SPI6_RX_DMA_PRIORITY, \ + SPI6_RX_DMA_PREEMPT_PRIORITY, \ + SPI6_RX_DMA_SUB_PRIORITY) +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/uart_config.h index 441e98eb973..c068195f0bf 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/uart_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version * 2019-01-03 zylx modify dma support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -29,26 +30,56 @@ extern "C" { #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } +#define UART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ #endif /* BSP_USING_UART1 */ @@ -64,26 +95,56 @@ extern "C" { #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } +#define UART2_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ #endif /* BSP_USING_UART2 */ @@ -99,26 +160,56 @@ extern "C" { #endif /* UART3_CONFIG */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .channel = UART3_RX_DMA_CHANNEL, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .channel = UART3_TX_DMA_CHANNEL, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } +#define UART3_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ #endif /* BSP_USING_UART3 */ @@ -134,28 +225,58 @@ extern "C" { #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_RX_DMA_PRIORITY +#define UART4_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_RX_DMA_PRIORITY */ + +#ifndef UART4_RX_DMA_PREEMPT_PRIORITY +#define UART4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_RX_DMA_SUB_PRIORITY +#define UART4_RX_DMA_SUB_PRIORITY 0 +#endif /* UART4_RX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .channel = UART4_RX_DMA_CHANNEL, \ - .dma_rcc = UART4_RX_DMA_RCC, \ - .dma_irq = UART4_RX_DMA_IRQ, \ - } +#define UART4_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART4_RX_DMA_INSTANCE, \ + UART4_RX_DMA_RCC, \ + UART4_RX_DMA_IRQ, \ + UART4_RX_DMA_CHANNEL, \ + UART4_RX_DMA_REQUEST, \ + UART4_RX_DMA_PRIORITY, \ + UART4_RX_DMA_PREEMPT_PRIORITY, \ + UART4_RX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_RX_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_TX_DMA_PRIORITY +#define UART4_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_TX_DMA_PRIORITY */ + +#ifndef UART4_TX_DMA_PREEMPT_PRIORITY +#define UART4_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_TX_DMA_SUB_PRIORITY +#define UART4_TX_DMA_SUB_PRIORITY 0 +#endif /* UART4_TX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_TX_CONFIG -#define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .channel = UART4_TX_DMA_CHANNEL, \ - .dma_rcc = UART4_TX_DMA_RCC, \ - .dma_irq = UART4_TX_DMA_IRQ, \ - } +#define UART4_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART4_TX_DMA_INSTANCE, \ + UART4_TX_DMA_RCC, \ + UART4_TX_DMA_IRQ, \ + UART4_TX_DMA_CHANNEL, \ + UART4_TX_DMA_REQUEST, \ + UART4_TX_DMA_PRIORITY, \ + UART4_TX_DMA_PREEMPT_PRIORITY, \ + UART4_TX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_TX_CONFIG */ -#endif /* BSP_UART4_RX_USING_DMA */ +#endif /* BSP_UART4_TX_USING_DMA */ #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_UART5) @@ -169,26 +290,56 @@ extern "C" { #endif /* UART5_CONFIG */ #if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_RX_DMA_PRIORITY +#define UART5_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_RX_DMA_PRIORITY */ + +#ifndef UART5_RX_DMA_PREEMPT_PRIORITY +#define UART5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_RX_DMA_SUB_PRIORITY +#define UART5_RX_DMA_SUB_PRIORITY 0 +#endif /* UART5_RX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .channel = UART5_RX_DMA_CHANNEL, \ - .dma_rcc = UART5_RX_DMA_RCC, \ - .dma_irq = UART5_RX_DMA_IRQ, \ - } +#define UART5_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART5_RX_DMA_INSTANCE, \ + UART5_RX_DMA_RCC, \ + UART5_RX_DMA_IRQ, \ + UART5_RX_DMA_CHANNEL, \ + UART5_RX_DMA_REQUEST, \ + UART5_RX_DMA_PRIORITY, \ + UART5_RX_DMA_PREEMPT_PRIORITY, \ + UART5_RX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ #if defined(BSP_UART5_TX_USING_DMA) +#ifndef UART5_TX_DMA_PRIORITY +#define UART5_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_TX_DMA_PRIORITY */ + +#ifndef UART5_TX_DMA_PREEMPT_PRIORITY +#define UART5_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_TX_DMA_SUB_PRIORITY +#define UART5_TX_DMA_SUB_PRIORITY 0 +#endif /* UART5_TX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_TX_CONFIG -#define UART5_DMA_TX_CONFIG \ - { \ - .Instance = UART5_TX_DMA_INSTANCE, \ - .channel = UART5_TX_DMA_CHANNEL, \ - .dma_rcc = UART5_TX_DMA_RCC, \ - .dma_irq = UART5_TX_DMA_IRQ, \ - } +#define UART5_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART5_TX_DMA_INSTANCE, \ + UART5_TX_DMA_RCC, \ + UART5_TX_DMA_IRQ, \ + UART5_TX_DMA_CHANNEL, \ + UART5_TX_DMA_REQUEST, \ + UART5_TX_DMA_PRIORITY, \ + UART5_TX_DMA_PREEMPT_PRIORITY, \ + UART5_TX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_TX_CONFIG */ #endif /* BSP_UART5_TX_USING_DMA */ #endif /* BSP_USING_UART5 */ @@ -204,26 +355,56 @@ extern "C" { #endif /* UART6_CONFIG */ #if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_RX_DMA_PRIORITY +#define UART6_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART6_RX_DMA_PRIORITY */ + +#ifndef UART6_RX_DMA_PREEMPT_PRIORITY +#define UART6_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART6_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART6_RX_DMA_SUB_PRIORITY +#define UART6_RX_DMA_SUB_PRIORITY 0 +#endif /* UART6_RX_DMA_SUB_PRIORITY */ + #ifndef UART6_DMA_RX_CONFIG -#define UART6_DMA_RX_CONFIG \ - { \ - .Instance = UART6_RX_DMA_INSTANCE, \ - .channel = UART6_RX_DMA_CHANNEL, \ - .dma_rcc = UART6_RX_DMA_RCC, \ - .dma_irq = UART6_RX_DMA_IRQ, \ - } +#define UART6_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART6_RX_DMA_INSTANCE, \ + UART6_RX_DMA_RCC, \ + UART6_RX_DMA_IRQ, \ + UART6_RX_DMA_CHANNEL, \ + UART6_RX_DMA_REQUEST, \ + UART6_RX_DMA_PRIORITY, \ + UART6_RX_DMA_PREEMPT_PRIORITY, \ + UART6_RX_DMA_SUB_PRIORITY) #endif /* UART6_DMA_RX_CONFIG */ #endif /* BSP_UART6_RX_USING_DMA */ #if defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_TX_DMA_PRIORITY +#define UART6_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART6_TX_DMA_PRIORITY */ + +#ifndef UART6_TX_DMA_PREEMPT_PRIORITY +#define UART6_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART6_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART6_TX_DMA_SUB_PRIORITY +#define UART6_TX_DMA_SUB_PRIORITY 0 +#endif /* UART6_TX_DMA_SUB_PRIORITY */ + #ifndef UART6_DMA_TX_CONFIG -#define UART6_DMA_TX_CONFIG \ - { \ - .Instance = UART6_TX_DMA_INSTANCE, \ - .channel = UART6_TX_DMA_CHANNEL, \ - .dma_rcc = UART6_TX_DMA_RCC, \ - .dma_irq = UART6_TX_DMA_IRQ, \ - } +#define UART6_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART6_TX_DMA_INSTANCE, \ + UART6_TX_DMA_RCC, \ + UART6_TX_DMA_IRQ, \ + UART6_TX_DMA_CHANNEL, \ + UART6_TX_DMA_REQUEST, \ + UART6_TX_DMA_PRIORITY, \ + UART6_TX_DMA_PREEMPT_PRIORITY, \ + UART6_TX_DMA_SUB_PRIORITY) #endif /* UART6_DMA_TX_CONFIG */ #endif /* BSP_UART6_TX_USING_DMA */ #endif /* BSP_USING_UART6 */ @@ -233,32 +414,62 @@ extern "C" { #define UART7_CONFIG \ { \ .name = "uart7", \ - .Instance = UART7, \ - .irq_type = UART7_IRQn, \ + .Instance = UART7, \ + .irq_type = UART7_IRQn, \ } #endif /* UART7_CONFIG */ #if defined(BSP_UART7_RX_USING_DMA) +#ifndef UART7_RX_DMA_PRIORITY +#define UART7_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART7_RX_DMA_PRIORITY */ + +#ifndef UART7_RX_DMA_PREEMPT_PRIORITY +#define UART7_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART7_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART7_RX_DMA_SUB_PRIORITY +#define UART7_RX_DMA_SUB_PRIORITY 0 +#endif /* UART7_RX_DMA_SUB_PRIORITY */ + #ifndef UART7_DMA_RX_CONFIG -#define UART7_DMA_RX_CONFIG \ - { \ - .Instance = UART7_RX_DMA_INSTANCE, \ - .channel = UART7_RX_DMA_CHANNEL, \ - .dma_rcc = UART7_RX_DMA_RCC, \ - .dma_irq = UART7_RX_DMA_IRQ, \ - } +#define UART7_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART7_RX_DMA_INSTANCE, \ + UART7_RX_DMA_RCC, \ + UART7_RX_DMA_IRQ, \ + UART7_RX_DMA_CHANNEL, \ + UART7_RX_DMA_REQUEST, \ + UART7_RX_DMA_PRIORITY, \ + UART7_RX_DMA_PREEMPT_PRIORITY, \ + UART7_RX_DMA_SUB_PRIORITY) #endif /* UART7_DMA_RX_CONFIG */ #endif /* BSP_UART7_RX_USING_DMA */ #if defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_TX_DMA_PRIORITY +#define UART7_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART7_TX_DMA_PRIORITY */ + +#ifndef UART7_TX_DMA_PREEMPT_PRIORITY +#define UART7_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART7_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART7_TX_DMA_SUB_PRIORITY +#define UART7_TX_DMA_SUB_PRIORITY 0 +#endif /* UART7_TX_DMA_SUB_PRIORITY */ + #ifndef UART7_DMA_TX_CONFIG -#define UART7_DMA_TX_CONFIG \ - { \ - .Instance = UART7_TX_DMA_INSTANCE, \ - .channel = UART7_TX_DMA_CHANNEL, \ - .dma_rcc = UART7_TX_DMA_RCC, \ - .dma_irq = UART7_TX_DMA_IRQ, \ - } +#define UART7_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART7_TX_DMA_INSTANCE, \ + UART7_TX_DMA_RCC, \ + UART7_TX_DMA_IRQ, \ + UART7_TX_DMA_CHANNEL, \ + UART7_TX_DMA_REQUEST, \ + UART7_TX_DMA_PRIORITY, \ + UART7_TX_DMA_PREEMPT_PRIORITY, \ + UART7_TX_DMA_SUB_PRIORITY) #endif /* UART7_DMA_TX_CONFIG */ #endif /* BSP_UART7_TX_USING_DMA */ #endif /* BSP_USING_UART7 */ @@ -268,32 +479,62 @@ extern "C" { #define UART8_CONFIG \ { \ .name = "uart8", \ - .Instance = UART8, \ - .irq_type = UART8_IRQn, \ + .Instance = UART8, \ + .irq_type = UART8_IRQn, \ } #endif /* UART8_CONFIG */ #if defined(BSP_UART8_RX_USING_DMA) +#ifndef UART8_RX_DMA_PRIORITY +#define UART8_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART8_RX_DMA_PRIORITY */ + +#ifndef UART8_RX_DMA_PREEMPT_PRIORITY +#define UART8_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART8_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART8_RX_DMA_SUB_PRIORITY +#define UART8_RX_DMA_SUB_PRIORITY 0 +#endif /* UART8_RX_DMA_SUB_PRIORITY */ + #ifndef UART8_DMA_RX_CONFIG -#define UART8_DMA_RX_CONFIG \ - { \ - .Instance = UART8_RX_DMA_INSTANCE, \ - .channel = UART8_RX_DMA_CHANNEL, \ - .dma_rcc = UART8_RX_DMA_RCC, \ - .dma_irq = UART8_RX_DMA_IRQ, \ - } +#define UART8_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART8_RX_DMA_INSTANCE, \ + UART8_RX_DMA_RCC, \ + UART8_RX_DMA_IRQ, \ + UART8_RX_DMA_CHANNEL, \ + UART8_RX_DMA_REQUEST, \ + UART8_RX_DMA_PRIORITY, \ + UART8_RX_DMA_PREEMPT_PRIORITY, \ + UART8_RX_DMA_SUB_PRIORITY) #endif /* UART8_DMA_RX_CONFIG */ #endif /* BSP_UART8_RX_USING_DMA */ #if defined(BSP_UART8_TX_USING_DMA) +#ifndef UART8_TX_DMA_PRIORITY +#define UART8_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART8_TX_DMA_PRIORITY */ + +#ifndef UART8_TX_DMA_PREEMPT_PRIORITY +#define UART8_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART8_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART8_TX_DMA_SUB_PRIORITY +#define UART8_TX_DMA_SUB_PRIORITY 0 +#endif /* UART8_TX_DMA_SUB_PRIORITY */ + #ifndef UART8_DMA_TX_CONFIG -#define UART8_DMA_TX_CONFIG \ - { \ - .Instance = UART8_TX_DMA_INSTANCE, \ - .channel = UART8_TX_DMA_CHANNEL, \ - .dma_rcc = UART8_TX_DMA_RCC, \ - .dma_irq = UART8_TX_DMA_IRQ, \ - } +#define UART8_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART8_TX_DMA_INSTANCE, \ + UART8_TX_DMA_RCC, \ + UART8_TX_DMA_IRQ, \ + UART8_TX_DMA_CHANNEL, \ + UART8_TX_DMA_REQUEST, \ + UART8_TX_DMA_PRIORITY, \ + UART8_TX_DMA_PREEMPT_PRIORITY, \ + UART8_TX_DMA_SUB_PRIORITY) #endif /* UART8_DMA_TX_CONFIG */ #endif /* BSP_UART8_TX_USING_DMA */ #endif /* BSP_USING_UART8 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/qspi_config.h index a315b2f5cc6..bdecbbc6189 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/qspi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-22 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __QSPI_CONFIG_H__ @@ -30,19 +31,29 @@ extern "C" { #endif /* BSP_USING_QSPI */ #ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_PRIORITY +#define QSPI_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* QSPI_DMA_PRIORITY */ + +#ifndef QSPI_DMA_PREEMPT_PRIORITY +#define QSPI_DMA_PREEMPT_PRIORITY 0 +#endif /* QSPI_DMA_PREEMPT_PRIORITY */ + +#ifndef QSPI_DMA_SUB_PRIORITY +#define QSPI_DMA_SUB_PRIORITY 0 +#endif /* QSPI_DMA_SUB_PRIORITY */ + #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .Init.Channel = QSPI_DMA_CHANNEL, \ - .Init.Direction = DMA_PERIPH_TO_MEMORY, \ - .Init.PeriphInc = DMA_PINC_DISABLE, \ - .Init.MemInc = DMA_MINC_ENABLE, \ - .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ - .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ - .Init.Mode = DMA_NORMAL, \ - .Init.Priority = DMA_PRIORITY_LOW \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + QSPI_DMA_INSTANCE, \ + QSPI_DMA_RCC, \ + QSPI_DMA_IRQ, \ + QSPI_DMA_CHANNEL, \ + 0U, \ + QSPI_DMA_PRIORITY, \ + QSPI_DMA_PREEMPT_PRIORITY, \ + QSPI_DMA_SUB_PRIORITY) #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/sdio_config.h index b5bc4ac341c..6f46d5b8806 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/sdio_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-13 BalanceTWK first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SDIO_CONFIG_H__ @@ -19,17 +20,71 @@ extern "C" { #endif #ifdef BSP_USING_SDIO +#ifndef SDIO_RX_DMA_PRIORITY +#define SDIO_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_RX_DMA_PRIORITY */ + +#ifndef SDIO_RX_DMA_PREEMPT_PRIORITY +#define SDIO_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_RX_DMA_SUB_PRIORITY +#define SDIO_RX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_RX_DMA_SUB_PRIORITY */ + +#ifndef SDIO_TX_DMA_PRIORITY +#define SDIO_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_TX_DMA_PRIORITY */ + +#ifndef SDIO_TX_DMA_PREEMPT_PRIORITY +#define SDIO_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_TX_DMA_SUB_PRIORITY +#define SDIO_TX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_TX_DMA_SUB_PRIORITY */ + #define SDIO_BUS_CONFIG \ { \ .Instance = SDMMC1, \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_4, \ - .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ - .dma_tx.Instance = DMA2_Stream6, \ - .dma_tx.channel = DMA_CHANNEL_4, \ - .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + .dma_rx = STM32_DMA_CONFIG_INIT_FIFO_EX( \ + DMA2_Stream3, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Stream3_IRQn, \ + DMA_CHANNEL_4, \ + 0U, \ + SDIO_RX_DMA_PRIORITY, \ + SDIO_RX_DMA_PREEMPT_PRIORITY, \ + SDIO_RX_DMA_SUB_PRIORITY, \ + DMA_PERIPH_TO_MEMORY, \ + DMA_PINC_DISABLE, \ + DMA_MINC_ENABLE, \ + DMA_PDATAALIGN_WORD, \ + DMA_MDATAALIGN_WORD, \ + DMA_PFCTRL, \ + DMA_FIFOMODE_ENABLE, \ + DMA_FIFO_THRESHOLD_FULL, \ + DMA_MBURST_INC4, \ + DMA_PBURST_INC4), \ + .dma_tx = STM32_DMA_CONFIG_INIT_FIFO_EX( \ + DMA2_Stream6, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Stream6_IRQn, \ + DMA_CHANNEL_4, \ + 0U, \ + SDIO_TX_DMA_PRIORITY, \ + SDIO_TX_DMA_PREEMPT_PRIORITY, \ + SDIO_TX_DMA_SUB_PRIORITY, \ + DMA_MEMORY_TO_PERIPH, \ + DMA_PINC_DISABLE, \ + DMA_MINC_ENABLE, \ + DMA_PDATAALIGN_WORD, \ + DMA_MDATAALIGN_WORD, \ + DMA_PFCTRL, \ + DMA_FIFOMODE_ENABLE, \ + DMA_FIFO_THRESHOLD_FULL, \ + DMA_MBURST_INC4, \ + DMA_PBURST_INC4), \ } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/spi_config.h index e3a564c5a9d..b66f63a1f86 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/spi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -29,26 +30,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + 0U, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + 0U, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -64,26 +93,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .channel = SPI2_TX_DMA_CHANNEL, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + 0U, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .channel = SPI2_RX_DMA_CHANNEL, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + 0U, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -99,26 +156,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .channel = SPI3_TX_DMA_CHANNEL, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + 0U, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG #define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .channel = SPI3_RX_DMA_CHANNEL, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + 0U, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ @@ -134,26 +219,54 @@ extern "C" { #endif /* BSP_USING_SPI4 */ #ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_PRIORITY +#define SPI4_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI4_TX_DMA_PRIORITY */ + +#ifndef SPI4_TX_DMA_PREEMPT_PRIORITY +#define SPI4_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_TX_DMA_SUB_PRIORITY +#define SPI4_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_TX_DMA_SUB_PRIORITY */ #ifndef SPI4_TX_DMA_CONFIG #define SPI4_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI4_TX_DMA_RCC, \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .channel = SPI4_TX_DMA_CHANNEL, \ - .dma_irq = SPI4_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI4_TX_DMA_INSTANCE, \ + SPI4_TX_DMA_RCC, \ + SPI4_TX_DMA_IRQ, \ + SPI4_TX_DMA_CHANNEL, \ + 0U, \ + SPI4_TX_DMA_PRIORITY, \ + SPI4_TX_DMA_PREEMPT_PRIORITY, \ + SPI4_TX_DMA_SUB_PRIORITY) #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ #ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_PRIORITY +#define SPI4_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI4_RX_DMA_PRIORITY */ + +#ifndef SPI4_RX_DMA_PREEMPT_PRIORITY +#define SPI4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_RX_DMA_SUB_PRIORITY +#define SPI4_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_RX_DMA_SUB_PRIORITY */ #ifndef SPI4_RX_DMA_CONFIG #define SPI4_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI4_RX_DMA_RCC, \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .channel = SPI4_RX_DMA_CHANNEL, \ - .dma_irq = SPI4_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI4_RX_DMA_INSTANCE, \ + SPI4_RX_DMA_RCC, \ + SPI4_RX_DMA_IRQ, \ + SPI4_RX_DMA_CHANNEL, \ + 0U, \ + SPI4_RX_DMA_PRIORITY, \ + SPI4_RX_DMA_PREEMPT_PRIORITY, \ + SPI4_RX_DMA_SUB_PRIORITY) #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ @@ -169,26 +282,54 @@ extern "C" { #endif /* BSP_USING_SPI5 */ #ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_PRIORITY +#define SPI5_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI5_TX_DMA_PRIORITY */ + +#ifndef SPI5_TX_DMA_PREEMPT_PRIORITY +#define SPI5_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI5_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_TX_DMA_SUB_PRIORITY +#define SPI5_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_TX_DMA_SUB_PRIORITY */ #ifndef SPI5_TX_DMA_CONFIG #define SPI5_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI5_TX_DMA_RCC, \ - .Instance = SPI5_TX_DMA_INSTANCE, \ - .channel = SPI5_TX_DMA_CHANNEL, \ - .dma_irq = SPI5_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI5_TX_DMA_INSTANCE, \ + SPI5_TX_DMA_RCC, \ + SPI5_TX_DMA_IRQ, \ + SPI5_TX_DMA_CHANNEL, \ + 0U, \ + SPI5_TX_DMA_PRIORITY, \ + SPI5_TX_DMA_PREEMPT_PRIORITY, \ + SPI5_TX_DMA_SUB_PRIORITY) #endif /* SPI5_TX_DMA_CONFIG */ #endif /* BSP_SPI5_TX_USING_DMA */ #ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_PRIORITY +#define SPI5_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI5_RX_DMA_PRIORITY */ + +#ifndef SPI5_RX_DMA_PREEMPT_PRIORITY +#define SPI5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_RX_DMA_SUB_PRIORITY +#define SPI5_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_RX_DMA_SUB_PRIORITY */ #ifndef SPI5_RX_DMA_CONFIG #define SPI5_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI5_RX_DMA_RCC, \ - .Instance = SPI5_RX_DMA_INSTANCE, \ - .channel = SPI5_RX_DMA_CHANNEL, \ - .dma_irq = SPI5_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI5_RX_DMA_INSTANCE, \ + SPI5_RX_DMA_RCC, \ + SPI5_RX_DMA_IRQ, \ + SPI5_RX_DMA_CHANNEL, \ + 0U, \ + SPI5_RX_DMA_PRIORITY, \ + SPI5_RX_DMA_PREEMPT_PRIORITY, \ + SPI5_RX_DMA_SUB_PRIORITY) #endif /* SPI5_RX_DMA_CONFIG */ #endif /* BSP_SPI5_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/uart_config.h index c50839efcdd..305581cb33a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/uart_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version * 2019-01-05 zylx modify dma support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -30,14 +31,29 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ @@ -53,14 +69,29 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ @@ -76,14 +107,29 @@ extern "C" { #endif /* BSP_USING_UART3 */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .channel = UART3_RX_DMA_CHANNEL, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ @@ -99,14 +145,29 @@ extern "C" { #endif /* BSP_USING_UART4 */ #if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_RX_DMA_PRIORITY +#define UART4_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_RX_DMA_PRIORITY */ + +#ifndef UART4_RX_DMA_PREEMPT_PRIORITY +#define UART4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_RX_DMA_SUB_PRIORITY +#define UART4_RX_DMA_SUB_PRIORITY 0 +#endif /* UART4_RX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .channel = UART4_RX_DMA_CHANNEL, \ - .dma_rcc = UART4_RX_DMA_RCC, \ - .dma_irq = UART4_RX_DMA_IRQ, \ - } +#define UART4_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART4_RX_DMA_INSTANCE, \ + UART4_RX_DMA_RCC, \ + UART4_RX_DMA_IRQ, \ + UART4_RX_DMA_CHANNEL, \ + UART4_RX_DMA_REQUEST, \ + UART4_RX_DMA_PRIORITY, \ + UART4_RX_DMA_PREEMPT_PRIORITY, \ + UART4_RX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_RX_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ @@ -122,14 +183,29 @@ extern "C" { #endif /* BSP_USING_UART5 */ #if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_RX_DMA_PRIORITY +#define UART5_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_RX_DMA_PRIORITY */ + +#ifndef UART5_RX_DMA_PREEMPT_PRIORITY +#define UART5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_RX_DMA_SUB_PRIORITY +#define UART5_RX_DMA_SUB_PRIORITY 0 +#endif /* UART5_RX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .channel = UART5_RX_DMA_CHANNEL, \ - .dma_rcc = UART5_RX_DMA_RCC, \ - .dma_irq = UART5_RX_DMA_IRQ, \ - } +#define UART5_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART5_RX_DMA_INSTANCE, \ + UART5_RX_DMA_RCC, \ + UART5_RX_DMA_IRQ, \ + UART5_RX_DMA_CHANNEL, \ + UART5_RX_DMA_REQUEST, \ + UART5_RX_DMA_PRIORITY, \ + UART5_RX_DMA_PREEMPT_PRIORITY, \ + UART5_RX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ @@ -145,14 +221,29 @@ extern "C" { #endif /* BSP_USING_UART6 */ #if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_RX_DMA_PRIORITY +#define UART6_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART6_RX_DMA_PRIORITY */ + +#ifndef UART6_RX_DMA_PREEMPT_PRIORITY +#define UART6_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART6_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART6_RX_DMA_SUB_PRIORITY +#define UART6_RX_DMA_SUB_PRIORITY 0 +#endif /* UART6_RX_DMA_SUB_PRIORITY */ + #ifndef UART6_DMA_RX_CONFIG -#define UART6_DMA_RX_CONFIG \ - { \ - .Instance = UART6_RX_DMA_INSTANCE, \ - .channel = UART6_RX_DMA_CHANNEL, \ - .dma_rcc = UART6_RX_DMA_RCC, \ - .dma_irq = UART6_RX_DMA_IRQ, \ - } +#define UART6_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART6_RX_DMA_INSTANCE, \ + UART6_RX_DMA_RCC, \ + UART6_RX_DMA_IRQ, \ + UART6_RX_DMA_CHANNEL, \ + UART6_RX_DMA_REQUEST, \ + UART6_RX_DMA_PRIORITY, \ + UART6_RX_DMA_PREEMPT_PRIORITY, \ + UART6_RX_DMA_SUB_PRIORITY) #endif /* UART6_DMA_RX_CONFIG */ #endif /* BSP_UART6_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/spi_config.h index 0591c873179..14947b8bb65 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/spi_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-01-05 zylx first version * 2019-01-08 SummerGift clean up the code + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -30,26 +31,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .request = SPI1_TX_DMA_REQUEST, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + SPI1_TX_DMA_REQUEST, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .request = SPI1_RX_DMA_REQUEST, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + SPI1_RX_DMA_REQUEST, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -74,26 +103,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .request = SPI2_TX_DMA_REQUEST, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + SPI2_TX_DMA_REQUEST, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .request = SPI2_RX_DMA_REQUEST, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + SPI2_RX_DMA_REQUEST, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/uart_config.h index b8ed62c4c97..49ab71a5fa3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/uart_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-10-30 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -36,14 +37,29 @@ extern "C" { #endif /* defined(STM32G071xx) || defined(STM32G081xx) */ #endif /* LPUART1_CONFIG */ #if defined(BSP_LPUART1_RX_USING_DMA) +#ifndef LPUART1_DMA_PRIORITY +#define LPUART1_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* LPUART1_DMA_PRIORITY */ + +#ifndef LPUART1_DMA_PREEMPT_PRIORITY +#define LPUART1_DMA_PREEMPT_PRIORITY 0 +#endif /* LPUART1_DMA_PREEMPT_PRIORITY */ + +#ifndef LPUART1_DMA_SUB_PRIORITY +#define LPUART1_DMA_SUB_PRIORITY 0 +#endif /* LPUART1_DMA_SUB_PRIORITY */ + #ifndef LPUART1_DMA_CONFIG #define LPUART1_DMA_CONFIG \ - { \ - .Instance = LPUART1_RX_DMA_INSTANCE, \ - .request = LPUART1_RX_DMA_REQUEST, \ - .dma_rcc = LPUART1_RX_DMA_RCC, \ - .dma_irq = LPUART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + LPUART1_RX_DMA_INSTANCE, \ + LPUART1_RX_DMA_RCC, \ + LPUART1_RX_DMA_IRQ, \ + LPUART1_RX_DMA_CHANNEL, \ + LPUART1_RX_DMA_REQUEST, \ + LPUART1_DMA_PRIORITY, \ + LPUART1_DMA_PREEMPT_PRIORITY, \ + LPUART1_DMA_SUB_PRIORITY) #endif /* LPUART1_DMA_CONFIG */ #endif /* BSP_LPUART1_RX_USING_DMA */ #endif /* BSP_USING_LPUART1 */ @@ -60,26 +76,56 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG #define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .request = UART1_RX_DMA_REQUEST, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG #define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .request = UART1_TX_DMA_REQUEST, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -104,26 +150,56 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG #define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .request = UART2_RX_DMA_REQUEST, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG #define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .request = UART2_TX_DMA_REQUEST, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -169,14 +245,29 @@ extern "C" { #endif /* BSP_USING_UART3 */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .request = UART3_RX_DMA_REQUEST, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ @@ -222,14 +313,29 @@ extern "C" { #endif /* BSP_USING_UART4 */ #if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_RX_DMA_PRIORITY +#define UART4_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_RX_DMA_PRIORITY */ + +#ifndef UART4_RX_DMA_PREEMPT_PRIORITY +#define UART4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_RX_DMA_SUB_PRIORITY +#define UART4_RX_DMA_SUB_PRIORITY 0 +#endif /* UART4_RX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .request = UART4_RX_DMA_REQUEST, \ - .dma_rcc = UART4_RX_DMA_RCC, \ - .dma_irq = UART4_RX_DMA_IRQ, \ - } +#define UART4_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART4_RX_DMA_INSTANCE, \ + UART4_RX_DMA_RCC, \ + UART4_RX_DMA_IRQ, \ + UART4_RX_DMA_CHANNEL, \ + UART4_RX_DMA_REQUEST, \ + UART4_RX_DMA_PRIORITY, \ + UART4_RX_DMA_PREEMPT_PRIORITY, \ + UART4_RX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_RX_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ @@ -261,11 +367,29 @@ extern "C" { #endif /* BSP_USING_UART5 */ #if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_RX_DMA_PRIORITY +#define UART5_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_RX_DMA_PRIORITY */ + +#ifndef UART5_RX_DMA_PREEMPT_PRIORITY +#define UART5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_RX_DMA_SUB_PRIORITY +#define UART5_RX_DMA_SUB_PRIORITY 0 +#endif /* UART5_RX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = DMA_NOT_AVAILABLE, \ - } +#define UART5_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART5_RX_DMA_INSTANCE, \ + UART5_RX_DMA_RCC, \ + UART5_RX_DMA_IRQ, \ + UART5_RX_DMA_CHANNEL, \ + UART5_RX_DMA_REQUEST, \ + UART5_RX_DMA_PRIORITY, \ + UART5_RX_DMA_PREEMPT_PRIORITY, \ + UART5_RX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/qspi_config.h index 6c986bba124..f541796956b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/qspi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-22 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __QSPI_CONFIG_H__ @@ -30,19 +31,29 @@ extern "C" { #endif /* BSP_USING_QSPI */ #ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_PRIORITY +#define QSPI_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* QSPI_DMA_PRIORITY */ + +#ifndef QSPI_DMA_PREEMPT_PRIORITY +#define QSPI_DMA_PREEMPT_PRIORITY 0 +#endif /* QSPI_DMA_PREEMPT_PRIORITY */ + +#ifndef QSPI_DMA_SUB_PRIORITY +#define QSPI_DMA_SUB_PRIORITY 0 +#endif /* QSPI_DMA_SUB_PRIORITY */ + #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .Init.Channel = QSPI_DMA_CHANNEL, \ - .Init.Direction = DMA_PERIPH_TO_MEMORY, \ - .Init.PeriphInc = DMA_PINC_DISABLE, \ - .Init.MemInc = DMA_MINC_ENABLE, \ - .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ - .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ - .Init.Mode = DMA_NORMAL, \ - .Init.Priority = DMA_PRIORITY_LOW \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + QSPI_DMA_INSTANCE, \ + QSPI_DMA_RCC, \ + QSPI_DMA_IRQ, \ + QSPI_DMA_CHANNEL, \ + 0U, \ + QSPI_DMA_PRIORITY, \ + QSPI_DMA_PREEMPT_PRIORITY, \ + QSPI_DMA_SUB_PRIORITY) #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/sdio_config.h index da03304d6f0..c740e0b4e4b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/sdio_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-13 BalanceTWK first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SDIO_CONFIG_H__ @@ -19,17 +20,71 @@ extern "C" { #endif #ifdef BSP_USING_SDIO +#ifndef SDIO_RX_DMA_PRIORITY +#define SDIO_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_RX_DMA_PRIORITY */ + +#ifndef SDIO_RX_DMA_PREEMPT_PRIORITY +#define SDIO_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_RX_DMA_SUB_PRIORITY +#define SDIO_RX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_RX_DMA_SUB_PRIORITY */ + +#ifndef SDIO_TX_DMA_PRIORITY +#define SDIO_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_TX_DMA_PRIORITY */ + +#ifndef SDIO_TX_DMA_PREEMPT_PRIORITY +#define SDIO_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_TX_DMA_SUB_PRIORITY +#define SDIO_TX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_TX_DMA_SUB_PRIORITY */ + #define SDIO_BUS_CONFIG \ { \ - .Instance = SDIO, \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_4, \ - .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ - .dma_tx.Instance = DMA2_Stream6, \ - .dma_tx.channel = DMA_CHANNEL_4, \ - .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + .Instance = SDIO, \ + .dma_rx = STM32_DMA_CONFIG_INIT_FIFO_EX( \ + DMA2_Stream3, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Stream3_IRQn, \ + DMA_CHANNEL_4, \ + 0U, \ + SDIO_RX_DMA_PRIORITY, \ + SDIO_RX_DMA_PREEMPT_PRIORITY, \ + SDIO_RX_DMA_SUB_PRIORITY, \ + DMA_PERIPH_TO_MEMORY, \ + DMA_PINC_DISABLE, \ + DMA_MINC_ENABLE, \ + DMA_PDATAALIGN_WORD, \ + DMA_MDATAALIGN_WORD, \ + DMA_PFCTRL, \ + DMA_FIFOMODE_ENABLE, \ + DMA_FIFO_THRESHOLD_FULL, \ + DMA_MBURST_INC4, \ + DMA_PBURST_INC4), \ + .dma_tx = STM32_DMA_CONFIG_INIT_FIFO_EX( \ + DMA2_Stream6, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Stream6_IRQn, \ + DMA_CHANNEL_4, \ + 0U, \ + SDIO_TX_DMA_PRIORITY, \ + SDIO_TX_DMA_PREEMPT_PRIORITY, \ + SDIO_TX_DMA_SUB_PRIORITY, \ + DMA_MEMORY_TO_PERIPH, \ + DMA_PINC_DISABLE, \ + DMA_MINC_ENABLE, \ + DMA_PDATAALIGN_WORD, \ + DMA_MDATAALIGN_WORD, \ + DMA_PFCTRL, \ + DMA_FIFOMODE_ENABLE, \ + DMA_FIFO_THRESHOLD_FULL, \ + DMA_MBURST_INC4, \ + DMA_PBURST_INC4), \ } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/spi_config.h index 2375b3cd5bd..64b2fd17916 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/spi_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version * 2019-01-03 zylx modify DMA support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -30,26 +31,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + 0U, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + 0U, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -65,26 +94,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .channel = SPI2_TX_DMA_CHANNEL, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + 0U, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .channel = SPI2_RX_DMA_CHANNEL, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + 0U, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -100,26 +157,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .channel = SPI3_TX_DMA_CHANNEL, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + 0U, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG #define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .channel = SPI3_RX_DMA_CHANNEL, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + 0U, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ @@ -135,26 +220,54 @@ extern "C" { #endif /* BSP_USING_SPI4 */ #ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_PRIORITY +#define SPI4_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI4_TX_DMA_PRIORITY */ + +#ifndef SPI4_TX_DMA_PREEMPT_PRIORITY +#define SPI4_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_TX_DMA_SUB_PRIORITY +#define SPI4_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_TX_DMA_SUB_PRIORITY */ #ifndef SPI4_TX_DMA_CONFIG #define SPI4_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI4_TX_DMA_RCC, \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .channel = SPI4_TX_DMA_CHANNEL, \ - .dma_irq = SPI4_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI4_TX_DMA_INSTANCE, \ + SPI4_TX_DMA_RCC, \ + SPI4_TX_DMA_IRQ, \ + SPI4_TX_DMA_CHANNEL, \ + 0U, \ + SPI4_TX_DMA_PRIORITY, \ + SPI4_TX_DMA_PREEMPT_PRIORITY, \ + SPI4_TX_DMA_SUB_PRIORITY) #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ #ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_PRIORITY +#define SPI4_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI4_RX_DMA_PRIORITY */ + +#ifndef SPI4_RX_DMA_PREEMPT_PRIORITY +#define SPI4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_RX_DMA_SUB_PRIORITY +#define SPI4_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_RX_DMA_SUB_PRIORITY */ #ifndef SPI4_RX_DMA_CONFIG #define SPI4_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI4_RX_DMA_RCC, \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .channel = SPI4_RX_DMA_CHANNEL, \ - .dma_irq = SPI4_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI4_RX_DMA_INSTANCE, \ + SPI4_RX_DMA_RCC, \ + SPI4_RX_DMA_IRQ, \ + SPI4_RX_DMA_CHANNEL, \ + 0U, \ + SPI4_RX_DMA_PRIORITY, \ + SPI4_RX_DMA_PREEMPT_PRIORITY, \ + SPI4_RX_DMA_SUB_PRIORITY) #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ @@ -170,26 +283,54 @@ extern "C" { #endif /* BSP_USING_SPI5 */ #ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_PRIORITY +#define SPI5_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI5_TX_DMA_PRIORITY */ + +#ifndef SPI5_TX_DMA_PREEMPT_PRIORITY +#define SPI5_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI5_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_TX_DMA_SUB_PRIORITY +#define SPI5_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_TX_DMA_SUB_PRIORITY */ #ifndef SPI5_TX_DMA_CONFIG #define SPI5_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI5_TX_DMA_RCC, \ - .Instance = SPI5_TX_DMA_INSTANCE, \ - .channel = SPI5_TX_DMA_CHANNEL, \ - .dma_irq = SPI5_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI5_TX_DMA_INSTANCE, \ + SPI5_TX_DMA_RCC, \ + SPI5_TX_DMA_IRQ, \ + SPI5_TX_DMA_CHANNEL, \ + 0U, \ + SPI5_TX_DMA_PRIORITY, \ + SPI5_TX_DMA_PREEMPT_PRIORITY, \ + SPI5_TX_DMA_SUB_PRIORITY) #endif /* SPI5_TX_DMA_CONFIG */ #endif /* BSP_SPI5_TX_USING_DMA */ #ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_PRIORITY +#define SPI5_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI5_RX_DMA_PRIORITY */ + +#ifndef SPI5_RX_DMA_PREEMPT_PRIORITY +#define SPI5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_RX_DMA_SUB_PRIORITY +#define SPI5_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_RX_DMA_SUB_PRIORITY */ #ifndef SPI5_RX_DMA_CONFIG #define SPI5_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI5_RX_DMA_RCC, \ - .Instance = SPI5_RX_DMA_INSTANCE, \ - .channel = SPI5_RX_DMA_CHANNEL, \ - .dma_irq = SPI5_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI5_RX_DMA_INSTANCE, \ + SPI5_RX_DMA_RCC, \ + SPI5_RX_DMA_IRQ, \ + SPI5_RX_DMA_CHANNEL, \ + 0U, \ + SPI5_RX_DMA_PRIORITY, \ + SPI5_RX_DMA_PREEMPT_PRIORITY, \ + SPI5_RX_DMA_SUB_PRIORITY) #endif /* SPI5_RX_DMA_CONFIG */ #endif /* BSP_SPI5_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/uart_config.h index 7a632a9fe81..0c5c2577c5f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/uart_config.h @@ -8,6 +8,7 @@ * 2018-10-30 SummerGift first version * 2019-01-03 zylx modify dma support * 2019-10-03 xuzhuoyi modify for STM32G4 + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -29,14 +30,29 @@ extern "C" { } #endif /* LPUART1_CONFIG */ #if defined(BSP_LPUART1_RX_USING_DMA) +#ifndef LPUART1_DMA_PRIORITY +#define LPUART1_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* LPUART1_DMA_PRIORITY */ + +#ifndef LPUART1_DMA_PREEMPT_PRIORITY +#define LPUART1_DMA_PREEMPT_PRIORITY 0 +#endif /* LPUART1_DMA_PREEMPT_PRIORITY */ + +#ifndef LPUART1_DMA_SUB_PRIORITY +#define LPUART1_DMA_SUB_PRIORITY 0 +#endif /* LPUART1_DMA_SUB_PRIORITY */ + #ifndef LPUART1_DMA_CONFIG #define LPUART1_DMA_CONFIG \ - { \ - .Instance = LPUART1_RX_DMA_INSTANCE, \ - .request = LPUART1_RX_DMA_REQUEST, \ - .dma_rcc = LPUART1_RX_DMA_RCC, \ - .dma_irq = LPUART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + LPUART1_RX_DMA_INSTANCE, \ + LPUART1_RX_DMA_RCC, \ + LPUART1_RX_DMA_IRQ, \ + LPUART1_RX_DMA_CHANNEL, \ + LPUART1_RX_DMA_REQUEST, \ + LPUART1_DMA_PRIORITY, \ + LPUART1_DMA_PREEMPT_PRIORITY, \ + LPUART1_DMA_SUB_PRIORITY) #endif /* LPUART1_DMA_CONFIG */ #endif /* BSP_LPUART1_RX_USING_DMA */ #endif /* BSP_USING_LPUART1 */ @@ -52,26 +68,56 @@ extern "C" { #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } +#define UART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ #endif /* BSP_USING_UART1 */ @@ -87,26 +133,56 @@ extern "C" { #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } +#define UART2_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ #endif /* BSP_USING_UART2 */ @@ -122,26 +198,56 @@ extern "C" { #endif /* UART3_CONFIG */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .channel = UART3_RX_DMA_CHANNEL, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .channel = UART3_TX_DMA_CHANNEL, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } +#define UART3_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ #endif /* BSP_USING_UART3 */ @@ -157,28 +263,58 @@ extern "C" { #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_RX_DMA_PRIORITY +#define UART4_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_RX_DMA_PRIORITY */ + +#ifndef UART4_RX_DMA_PREEMPT_PRIORITY +#define UART4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_RX_DMA_SUB_PRIORITY +#define UART4_RX_DMA_SUB_PRIORITY 0 +#endif /* UART4_RX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .channel = UART4_RX_DMA_CHANNEL, \ - .dma_rcc = UART4_RX_DMA_RCC, \ - .dma_irq = UART4_RX_DMA_IRQ, \ - } +#define UART4_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART4_RX_DMA_INSTANCE, \ + UART4_RX_DMA_RCC, \ + UART4_RX_DMA_IRQ, \ + UART4_RX_DMA_CHANNEL, \ + UART4_RX_DMA_REQUEST, \ + UART4_RX_DMA_PRIORITY, \ + UART4_RX_DMA_PREEMPT_PRIORITY, \ + UART4_RX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_RX_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_TX_DMA_PRIORITY +#define UART4_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_TX_DMA_PRIORITY */ + +#ifndef UART4_TX_DMA_PREEMPT_PRIORITY +#define UART4_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_TX_DMA_SUB_PRIORITY +#define UART4_TX_DMA_SUB_PRIORITY 0 +#endif /* UART4_TX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_TX_CONFIG -#define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .channel = UART4_TX_DMA_CHANNEL, \ - .dma_rcc = UART4_TX_DMA_RCC, \ - .dma_irq = UART4_TX_DMA_IRQ, \ - } +#define UART4_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART4_TX_DMA_INSTANCE, \ + UART4_TX_DMA_RCC, \ + UART4_TX_DMA_IRQ, \ + UART4_TX_DMA_CHANNEL, \ + UART4_TX_DMA_REQUEST, \ + UART4_TX_DMA_PRIORITY, \ + UART4_TX_DMA_PREEMPT_PRIORITY, \ + UART4_TX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_TX_CONFIG */ -#endif /* BSP_UART4_RX_USING_DMA */ +#endif /* BSP_UART4_TX_USING_DMA */ #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_UART5) @@ -192,26 +328,56 @@ extern "C" { #endif /* UART5_CONFIG */ #if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_RX_DMA_PRIORITY +#define UART5_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_RX_DMA_PRIORITY */ + +#ifndef UART5_RX_DMA_PREEMPT_PRIORITY +#define UART5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_RX_DMA_SUB_PRIORITY +#define UART5_RX_DMA_SUB_PRIORITY 0 +#endif /* UART5_RX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .channel = UART5_RX_DMA_CHANNEL, \ - .dma_rcc = UART5_RX_DMA_RCC, \ - .dma_irq = UART5_RX_DMA_IRQ, \ - } +#define UART5_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART5_RX_DMA_INSTANCE, \ + UART5_RX_DMA_RCC, \ + UART5_RX_DMA_IRQ, \ + UART5_RX_DMA_CHANNEL, \ + UART5_RX_DMA_REQUEST, \ + UART5_RX_DMA_PRIORITY, \ + UART5_RX_DMA_PREEMPT_PRIORITY, \ + UART5_RX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ #if defined(BSP_UART5_TX_USING_DMA) +#ifndef UART5_TX_DMA_PRIORITY +#define UART5_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_TX_DMA_PRIORITY */ + +#ifndef UART5_TX_DMA_PREEMPT_PRIORITY +#define UART5_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_TX_DMA_SUB_PRIORITY +#define UART5_TX_DMA_SUB_PRIORITY 0 +#endif /* UART5_TX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_TX_CONFIG -#define UART5_DMA_TX_CONFIG \ - { \ - .Instance = UART5_TX_DMA_INSTANCE, \ - .channel = UART5_TX_DMA_CHANNEL, \ - .dma_rcc = UART5_TX_DMA_RCC, \ - .dma_irq = UART5_TX_DMA_IRQ, \ - } +#define UART5_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART5_TX_DMA_INSTANCE, \ + UART5_TX_DMA_RCC, \ + UART5_TX_DMA_IRQ, \ + UART5_TX_DMA_CHANNEL, \ + UART5_TX_DMA_REQUEST, \ + UART5_TX_DMA_PRIORITY, \ + UART5_TX_DMA_PREEMPT_PRIORITY, \ + UART5_TX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_TX_CONFIG */ #endif /* BSP_UART5_TX_USING_DMA */ #endif /* BSP_USING_UART5 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h5/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h5/uart_config.h index a94bb9ea1c7..76dc798adb8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h5/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h5/uart_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -27,14 +28,29 @@ extern "C" { } #endif /* LPUART1_CONFIG */ #if defined(BSP_LPUART1_RX_USING_DMA) +#ifndef LPUART1_DMA_PRIORITY +#define LPUART1_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* LPUART1_DMA_PRIORITY */ + +#ifndef LPUART1_DMA_PREEMPT_PRIORITY +#define LPUART1_DMA_PREEMPT_PRIORITY 0 +#endif /* LPUART1_DMA_PREEMPT_PRIORITY */ + +#ifndef LPUART1_DMA_SUB_PRIORITY +#define LPUART1_DMA_SUB_PRIORITY 0 +#endif /* LPUART1_DMA_SUB_PRIORITY */ + #ifndef LPUART1_DMA_CONFIG #define LPUART1_DMA_CONFIG \ - { \ - .Instance = LPUART1_RX_DMA_INSTANCE, \ - .request = LPUART1_RX_DMA_REQUEST, \ - .dma_rcc = LPUART1_RX_DMA_RCC, \ - .dma_irq = LPUART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + LPUART1_RX_DMA_INSTANCE, \ + LPUART1_RX_DMA_RCC, \ + LPUART1_RX_DMA_IRQ, \ + LPUART1_RX_DMA_CHANNEL, \ + LPUART1_RX_DMA_REQUEST, \ + LPUART1_DMA_PRIORITY, \ + LPUART1_DMA_PREEMPT_PRIORITY, \ + LPUART1_DMA_SUB_PRIORITY) #endif /* LPUART1_DMA_CONFIG */ #endif /* BSP_LPUART1_RX_USING_DMA */ #endif /* BSP_USING_LPUART1 */ @@ -51,26 +67,56 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .request = UART1_RX_DMA_REQUEST, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .request = UART1_TX_DMA_REQUEST, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } +#define UART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -86,26 +132,56 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .request = UART2_RX_DMA_REQUEST, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .request = UART2_TX_DMA_REQUEST, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } +#define UART2_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -121,26 +197,56 @@ extern "C" { #endif /* BSP_USING_UART3 */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .request = UART3_RX_DMA_REQUEST, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .request = UART3_TX_DMA_REQUEST, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } +#define UART3_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/i2c_hard_config.h index 55959f7324b..ab4bb81d06b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/i2c_hard_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/i2c_hard_config.h @@ -8,6 +8,7 @@ * 2024-02-06 Dyyt587 first version * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG * 2024-06-23 wdfk-prog Add H7 hard I2C config + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __I2C_HARD_CONFIG_H__ #define __I2C_HARD_CONFIG_H__ @@ -33,46 +34,54 @@ extern "C" { #endif /* BSP_USING_HARD_I2C1 */ #ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_PRIORITY +#define I2C1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C1_TX_DMA_PRIORITY */ + +#ifndef I2C1_TX_DMA_PREEMPT_PRIORITY +#define I2C1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C1_TX_DMA_SUB_PRIORITY +#define I2C1_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C1_TX_DMA_SUB_PRIORITY */ #ifndef I2C1_TX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define I2C1_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C1_TX_DMA_RCC, \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .dma_irq = I2C1_TX_DMA_IRQ, \ - .channel = I2C1_TX_DMA_CHANNEL \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) -#define I2C1_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C1_TX_DMA_RCC, \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .dma_irq = I2C1_TX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C1_TX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C1_TX_DMA_INSTANCE, \ + I2C1_TX_DMA_RCC, \ + I2C1_TX_DMA_IRQ, \ + I2C1_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C1_TX, \ + I2C1_TX_DMA_PRIORITY, \ + I2C1_TX_DMA_PREEMPT_PRIORITY, \ + I2C1_TX_DMA_SUB_PRIORITY) #endif /* I2C1_TX_DMA_CONFIG */ #endif /* BSP_I2C1_TX_USING_DMA */ #ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_PRIORITY +#define I2C1_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C1_RX_DMA_PRIORITY */ + +#ifndef I2C1_RX_DMA_PREEMPT_PRIORITY +#define I2C1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C1_RX_DMA_SUB_PRIORITY +#define I2C1_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C1_RX_DMA_SUB_PRIORITY */ #ifndef I2C1_RX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define I2C1_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C1_RX_DMA_RCC, \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .dma_irq = I2C1_RX_DMA_IRQ, \ - .channel = I2C1_RX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) -#define I2C1_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C1_RX_DMA_RCC, \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .dma_irq = I2C1_RX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C1_RX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C1_RX_DMA_INSTANCE, \ + I2C1_RX_DMA_RCC, \ + I2C1_RX_DMA_IRQ, \ + I2C1_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C1_RX, \ + I2C1_RX_DMA_PRIORITY, \ + I2C1_RX_DMA_PREEMPT_PRIORITY, \ + I2C1_RX_DMA_SUB_PRIORITY) #endif /* I2C1_RX_DMA_CONFIG */ #endif /* BSP_I2C1_RX_USING_DMA */ @@ -91,46 +100,54 @@ extern "C" { #endif /* BSP_USING_HARD_I2C2 */ #ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_PRIORITY +#define I2C2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C2_TX_DMA_PRIORITY */ + +#ifndef I2C2_TX_DMA_PREEMPT_PRIORITY +#define I2C2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C2_TX_DMA_SUB_PRIORITY +#define I2C2_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C2_TX_DMA_SUB_PRIORITY */ #ifndef I2C2_TX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define I2C2_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C2_TX_DMA_RCC, \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .dma_irq = I2C2_TX_DMA_IRQ, \ - .channel = I2C2_TX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) -#define I2C2_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C2_TX_DMA_RCC, \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .dma_irq = I2C2_TX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C2_TX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C2_TX_DMA_INSTANCE, \ + I2C2_TX_DMA_RCC, \ + I2C2_TX_DMA_IRQ, \ + I2C2_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C2_TX, \ + I2C2_TX_DMA_PRIORITY, \ + I2C2_TX_DMA_PREEMPT_PRIORITY, \ + I2C2_TX_DMA_SUB_PRIORITY) #endif /* I2C2_TX_DMA_CONFIG */ #endif /* BSP_I2C2_TX_USING_DMA */ #ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_PRIORITY +#define I2C2_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C2_RX_DMA_PRIORITY */ + +#ifndef I2C2_RX_DMA_PREEMPT_PRIORITY +#define I2C2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C2_RX_DMA_SUB_PRIORITY +#define I2C2_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C2_RX_DMA_SUB_PRIORITY */ #ifndef I2C2_RX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define I2C2_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C2_RX_DMA_RCC, \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .dma_irq = I2C2_RX_DMA_IRQ, \ - .channel = I2C2_RX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) -#define I2C2_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C2_RX_DMA_RCC, \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .dma_irq = I2C2_RX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C2_RX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C2_RX_DMA_INSTANCE, \ + I2C2_RX_DMA_RCC, \ + I2C2_RX_DMA_IRQ, \ + I2C2_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C2_RX, \ + I2C2_RX_DMA_PRIORITY, \ + I2C2_RX_DMA_PREEMPT_PRIORITY, \ + I2C2_RX_DMA_SUB_PRIORITY) #endif /* I2C2_RX_DMA_CONFIG */ #endif /* BSP_I2C2_RX_USING_DMA */ @@ -149,46 +166,54 @@ extern "C" { #endif /* BSP_USING_HARD_I2C3 */ #ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_PRIORITY +#define I2C3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C3_TX_DMA_PRIORITY */ + +#ifndef I2C3_TX_DMA_PREEMPT_PRIORITY +#define I2C3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C3_TX_DMA_SUB_PRIORITY +#define I2C3_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C3_TX_DMA_SUB_PRIORITY */ #ifndef I2C3_TX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define I2C3_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C3_TX_DMA_RCC, \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .dma_irq = I2C3_TX_DMA_IRQ, \ - .channel = I2C3_TX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) -#define I2C3_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C3_TX_DMA_RCC, \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .dma_irq = I2C3_TX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C3_TX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C3_TX_DMA_INSTANCE, \ + I2C3_TX_DMA_RCC, \ + I2C3_TX_DMA_IRQ, \ + I2C3_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C3_TX, \ + I2C3_TX_DMA_PRIORITY, \ + I2C3_TX_DMA_PREEMPT_PRIORITY, \ + I2C3_TX_DMA_SUB_PRIORITY) #endif /* I2C3_TX_DMA_CONFIG */ #endif /* BSP_I2C3_TX_USING_DMA */ #ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_PRIORITY +#define I2C3_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C3_RX_DMA_PRIORITY */ + +#ifndef I2C3_RX_DMA_PREEMPT_PRIORITY +#define I2C3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C3_RX_DMA_SUB_PRIORITY +#define I2C3_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C3_RX_DMA_SUB_PRIORITY */ #ifndef I2C3_RX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define I2C3_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C3_RX_DMA_RCC, \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .dma_irq = I2C3_RX_DMA_IRQ, \ - .channel = I2C3_RX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) -#define I2C3_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C3_RX_DMA_RCC, \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .dma_irq = I2C3_RX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C3_RX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C3_RX_DMA_INSTANCE, \ + I2C3_RX_DMA_RCC, \ + I2C3_RX_DMA_IRQ, \ + I2C3_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C3_RX, \ + I2C3_RX_DMA_PRIORITY, \ + I2C3_RX_DMA_PREEMPT_PRIORITY, \ + I2C3_RX_DMA_SUB_PRIORITY) #endif /* I2C3_RX_DMA_CONFIG */ #endif /* BSP_I2C3_RX_USING_DMA */ @@ -207,46 +232,54 @@ extern "C" { #endif /* BSP_USING_HARD_I2C4 */ #ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_PRIORITY +#define I2C4_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C4_TX_DMA_PRIORITY */ + +#ifndef I2C4_TX_DMA_PREEMPT_PRIORITY +#define I2C4_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* I2C4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C4_TX_DMA_SUB_PRIORITY +#define I2C4_TX_DMA_SUB_PRIORITY 0 +#endif /* I2C4_TX_DMA_SUB_PRIORITY */ #ifndef I2C4_TX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define I2C4_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C4_TX_DMA_RCC, \ - .Instance = I2C4_TX_DMA_INSTANCE, \ - .dma_irq = I2C4_TX_DMA_IRQ, \ - .channel = I2C4_TX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) -#define I2C4_TX_DMA_CONFIG \ - { \ - .dma_rcc = I2C4_TX_DMA_RCC, \ - .Instance = I2C4_TX_DMA_INSTANCE, \ - .dma_irq = I2C4_TX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C4_TX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + I2C4_TX_DMA_INSTANCE, \ + I2C4_TX_DMA_RCC, \ + I2C4_TX_DMA_IRQ, \ + I2C4_TX_DMA_CHANNEL, \ + DMA_REQUEST_I2C4_TX, \ + I2C4_TX_DMA_PRIORITY, \ + I2C4_TX_DMA_PREEMPT_PRIORITY, \ + I2C4_TX_DMA_SUB_PRIORITY) #endif /* I2C4_TX_DMA_CONFIG */ #endif /* BSP_I2C4_TX_USING_DMA */ #ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_PRIORITY +#define I2C4_RX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* I2C4_RX_DMA_PRIORITY */ + +#ifndef I2C4_RX_DMA_PREEMPT_PRIORITY +#define I2C4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* I2C4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef I2C4_RX_DMA_SUB_PRIORITY +#define I2C4_RX_DMA_SUB_PRIORITY 0 +#endif /* I2C4_RX_DMA_SUB_PRIORITY */ #ifndef I2C4_RX_DMA_CONFIG -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define I2C4_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C4_RX_DMA_RCC, \ - .Instance = I2C4_RX_DMA_INSTANCE, \ - .dma_irq = I2C4_RX_DMA_IRQ, \ - .channel = I2C4_RX_DMA_CHANNEL, \ - } -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) -#define I2C4_RX_DMA_CONFIG \ - { \ - .dma_rcc = I2C4_RX_DMA_RCC, \ - .Instance = I2C4_RX_DMA_INSTANCE, \ - .dma_irq = I2C4_RX_DMA_IRQ, \ - .request = DMA_REQUEST_I2C4_RX \ - } -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + I2C4_RX_DMA_INSTANCE, \ + I2C4_RX_DMA_RCC, \ + I2C4_RX_DMA_IRQ, \ + I2C4_RX_DMA_CHANNEL, \ + DMA_REQUEST_I2C4_RX, \ + I2C4_RX_DMA_PRIORITY, \ + I2C4_RX_DMA_PREEMPT_PRIORITY, \ + I2C4_RX_DMA_SUB_PRIORITY) #endif /* I2C4_RX_DMA_CONFIG */ #endif /* BSP_I2C4_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/qspi_config.h index a315b2f5cc6..bdecbbc6189 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/qspi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-22 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __QSPI_CONFIG_H__ @@ -30,19 +31,29 @@ extern "C" { #endif /* BSP_USING_QSPI */ #ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_PRIORITY +#define QSPI_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* QSPI_DMA_PRIORITY */ + +#ifndef QSPI_DMA_PREEMPT_PRIORITY +#define QSPI_DMA_PREEMPT_PRIORITY 0 +#endif /* QSPI_DMA_PREEMPT_PRIORITY */ + +#ifndef QSPI_DMA_SUB_PRIORITY +#define QSPI_DMA_SUB_PRIORITY 0 +#endif /* QSPI_DMA_SUB_PRIORITY */ + #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .Init.Channel = QSPI_DMA_CHANNEL, \ - .Init.Direction = DMA_PERIPH_TO_MEMORY, \ - .Init.PeriphInc = DMA_PINC_DISABLE, \ - .Init.MemInc = DMA_MINC_ENABLE, \ - .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ - .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ - .Init.Mode = DMA_NORMAL, \ - .Init.Priority = DMA_PRIORITY_LOW \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + QSPI_DMA_INSTANCE, \ + QSPI_DMA_RCC, \ + QSPI_DMA_IRQ, \ + QSPI_DMA_CHANNEL, \ + 0U, \ + QSPI_DMA_PRIORITY, \ + QSPI_DMA_PREEMPT_PRIORITY, \ + QSPI_DMA_SUB_PRIORITY) #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/sdio_config.h index b56b3034e6b..c5d5d2e9cb9 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/sdio_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-13 BalanceTWK first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SDIO_CONFIG_H__ @@ -19,17 +20,71 @@ extern "C" { #endif #ifdef BSP_USING_SDIO +#ifndef SDIO_RX_DMA_PRIORITY +#define SDIO_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_RX_DMA_PRIORITY */ + +#ifndef SDIO_RX_DMA_PREEMPT_PRIORITY +#define SDIO_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_RX_DMA_SUB_PRIORITY +#define SDIO_RX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_RX_DMA_SUB_PRIORITY */ + +#ifndef SDIO_TX_DMA_PRIORITY +#define SDIO_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_TX_DMA_PRIORITY */ + +#ifndef SDIO_TX_DMA_PREEMPT_PRIORITY +#define SDIO_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_TX_DMA_SUB_PRIORITY +#define SDIO_TX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_TX_DMA_SUB_PRIORITY */ + #define SDIO_BUS_CONFIG \ { \ .Instance = SDMMC1, \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_4, \ - .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ - .dma_tx.Instance = DMA2_Stream6, \ - .dma_tx.channel = DMA_CHANNEL_4, \ - .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + .dma_rx = STM32_DMA_CONFIG_INIT_FIFO_EX( \ + DMA2_Stream3, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Stream3_IRQn, \ + DMA_CHANNEL_4, \ + 0U, \ + SDIO_RX_DMA_PRIORITY, \ + SDIO_RX_DMA_PREEMPT_PRIORITY, \ + SDIO_RX_DMA_SUB_PRIORITY, \ + DMA_PERIPH_TO_MEMORY, \ + DMA_PINC_DISABLE, \ + DMA_MINC_ENABLE, \ + DMA_PDATAALIGN_WORD, \ + DMA_MDATAALIGN_WORD, \ + DMA_PFCTRL, \ + DMA_FIFOMODE_ENABLE, \ + DMA_FIFO_THRESHOLD_FULL, \ + DMA_MBURST_INC4, \ + DMA_PBURST_INC4), \ + .dma_tx = STM32_DMA_CONFIG_INIT_FIFO_EX( \ + DMA2_Stream6, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Stream6_IRQn, \ + DMA_CHANNEL_4, \ + 0U, \ + SDIO_TX_DMA_PRIORITY, \ + SDIO_TX_DMA_PREEMPT_PRIORITY, \ + SDIO_TX_DMA_SUB_PRIORITY, \ + DMA_MEMORY_TO_PERIPH, \ + DMA_PINC_DISABLE, \ + DMA_MINC_ENABLE, \ + DMA_PDATAALIGN_WORD, \ + DMA_MDATAALIGN_WORD, \ + DMA_PFCTRL, \ + DMA_FIFOMODE_ENABLE, \ + DMA_FIFO_THRESHOLD_FULL, \ + DMA_MBURST_INC4, \ + DMA_PBURST_INC4), \ } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/spi_config.h index 7caa420c873..f07e32edbed 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/spi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -29,26 +30,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - .request = DMA_REQUEST_SPI1_TX \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + DMA_REQUEST_SPI1_TX, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - .request = DMA_REQUEST_SPI1_RX \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + DMA_REQUEST_SPI1_RX, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -64,26 +93,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - .request = DMA_REQUEST_SPI2_TX \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + DMA_REQUEST_SPI2_TX, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - .request = DMA_REQUEST_SPI2_RX \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + DMA_REQUEST_SPI2_RX, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -99,26 +156,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - .request = DMA_REQUEST_SPI3_TX \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + DMA_REQUEST_SPI3_TX, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG #define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - .request = DMA_REQUEST_SPI3_RX \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + DMA_REQUEST_SPI3_RX, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ @@ -134,26 +219,54 @@ extern "C" { #endif /* BSP_USING_SPI4 */ #ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_PRIORITY +#define SPI4_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI4_TX_DMA_PRIORITY */ + +#ifndef SPI4_TX_DMA_PREEMPT_PRIORITY +#define SPI4_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_TX_DMA_SUB_PRIORITY +#define SPI4_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_TX_DMA_SUB_PRIORITY */ #ifndef SPI4_TX_DMA_CONFIG #define SPI4_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI4_TX_DMA_RCC, \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .dma_irq = SPI4_TX_DMA_IRQ, \ - .request = DMA_REQUEST_SPI4_TX \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI4_TX_DMA_INSTANCE, \ + SPI4_TX_DMA_RCC, \ + SPI4_TX_DMA_IRQ, \ + SPI4_TX_DMA_CHANNEL, \ + DMA_REQUEST_SPI4_TX, \ + SPI4_TX_DMA_PRIORITY, \ + SPI4_TX_DMA_PREEMPT_PRIORITY, \ + SPI4_TX_DMA_SUB_PRIORITY) #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ #ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_PRIORITY +#define SPI4_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI4_RX_DMA_PRIORITY */ + +#ifndef SPI4_RX_DMA_PREEMPT_PRIORITY +#define SPI4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_RX_DMA_SUB_PRIORITY +#define SPI4_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_RX_DMA_SUB_PRIORITY */ #ifndef SPI4_RX_DMA_CONFIG #define SPI4_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI4_RX_DMA_RCC, \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .dma_irq = SPI4_RX_DMA_IRQ, \ - .request = DMA_REQUEST_SPI4_RX \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI4_RX_DMA_INSTANCE, \ + SPI4_RX_DMA_RCC, \ + SPI4_RX_DMA_IRQ, \ + SPI4_RX_DMA_CHANNEL, \ + DMA_REQUEST_SPI4_RX, \ + SPI4_RX_DMA_PRIORITY, \ + SPI4_RX_DMA_PREEMPT_PRIORITY, \ + SPI4_RX_DMA_SUB_PRIORITY) #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ @@ -169,26 +282,54 @@ extern "C" { #endif /* BSP_USING_SPI5 */ #ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_PRIORITY +#define SPI5_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI5_TX_DMA_PRIORITY */ + +#ifndef SPI5_TX_DMA_PREEMPT_PRIORITY +#define SPI5_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI5_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_TX_DMA_SUB_PRIORITY +#define SPI5_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_TX_DMA_SUB_PRIORITY */ #ifndef SPI5_TX_DMA_CONFIG #define SPI5_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI5_TX_DMA_RCC, \ - .Instance = SPI5_TX_DMA_INSTANCE, \ - .dma_irq = SPI5_TX_DMA_IRQ, \ - .request = DMA_REQUEST_SPI5_TX \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI5_TX_DMA_INSTANCE, \ + SPI5_TX_DMA_RCC, \ + SPI5_TX_DMA_IRQ, \ + SPI5_TX_DMA_CHANNEL, \ + DMA_REQUEST_SPI5_TX, \ + SPI5_TX_DMA_PRIORITY, \ + SPI5_TX_DMA_PREEMPT_PRIORITY, \ + SPI5_TX_DMA_SUB_PRIORITY) #endif /* SPI5_TX_DMA_CONFIG */ #endif /* BSP_SPI5_TX_USING_DMA */ #ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_PRIORITY +#define SPI5_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI5_RX_DMA_PRIORITY */ + +#ifndef SPI5_RX_DMA_PREEMPT_PRIORITY +#define SPI5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_RX_DMA_SUB_PRIORITY +#define SPI5_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_RX_DMA_SUB_PRIORITY */ #ifndef SPI5_RX_DMA_CONFIG #define SPI5_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI5_RX_DMA_RCC, \ - .Instance = SPI5_RX_DMA_INSTANCE, \ - .dma_irq = SPI5_RX_DMA_IRQ, \ - .request = DMA_REQUEST_SPI5_RX \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI5_RX_DMA_INSTANCE, \ + SPI5_RX_DMA_RCC, \ + SPI5_RX_DMA_IRQ, \ + SPI5_RX_DMA_CHANNEL, \ + DMA_REQUEST_SPI5_RX, \ + SPI5_RX_DMA_PRIORITY, \ + SPI5_RX_DMA_PREEMPT_PRIORITY, \ + SPI5_RX_DMA_SUB_PRIORITY) #endif /* SPI5_RX_DMA_CONFIG */ #endif /* BSP_SPI5_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/uart_config.h index fbf9715dfdb..0fe5a4d8daa 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/uart_config.h @@ -8,6 +8,7 @@ * 2018-10-30 SummerGift first version * 2019-01-05 zylx modify dma support * 2020-05-02 whj4674672 support stm32h7 uart dma + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -31,14 +32,29 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG #define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .request = UART1_RX_DMA_REQUEST, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ @@ -54,25 +70,55 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG #define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .request = UART2_RX_DMA_REQUEST, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG #define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .request = UART2_TX_DMA_REQUEST, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -88,14 +134,29 @@ extern "C" { #endif /* BSP_USING_UART3 */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG #define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .request = UART3_RX_DMA_REQUEST, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ @@ -111,14 +172,29 @@ extern "C" { #endif /* BSP_USING_UART4 */ #if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_RX_DMA_PRIORITY +#define UART4_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_RX_DMA_PRIORITY */ + +#ifndef UART4_RX_DMA_PREEMPT_PRIORITY +#define UART4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_RX_DMA_SUB_PRIORITY +#define UART4_RX_DMA_SUB_PRIORITY 0 +#endif /* UART4_RX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_RX_CONFIG #define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .request = UART4_RX_DMA_REQUEST, \ - .dma_rcc = UART4_RX_DMA_RCC, \ - .dma_irq = UART4_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART4_RX_DMA_INSTANCE, \ + UART4_RX_DMA_RCC, \ + UART4_RX_DMA_IRQ, \ + UART4_RX_DMA_CHANNEL, \ + UART4_RX_DMA_REQUEST, \ + UART4_RX_DMA_PRIORITY, \ + UART4_RX_DMA_PREEMPT_PRIORITY, \ + UART4_RX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_RX_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ @@ -134,14 +210,29 @@ extern "C" { #endif /* BSP_USING_UART5 */ #if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_RX_DMA_PRIORITY +#define UART5_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_RX_DMA_PRIORITY */ + +#ifndef UART5_RX_DMA_PREEMPT_PRIORITY +#define UART5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_RX_DMA_SUB_PRIORITY +#define UART5_RX_DMA_SUB_PRIORITY 0 +#endif /* UART5_RX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_RX_CONFIG #define UART5_DMA_RX_CONFIG \ - { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .request = UART5_RX_DMA_REQUEST, \ - .dma_rcc = UART5_RX_DMA_RCC, \ - .dma_irq = UART5_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART5_RX_DMA_INSTANCE, \ + UART5_RX_DMA_RCC, \ + UART5_RX_DMA_IRQ, \ + UART5_RX_DMA_CHANNEL, \ + UART5_RX_DMA_REQUEST, \ + UART5_RX_DMA_PRIORITY, \ + UART5_RX_DMA_PREEMPT_PRIORITY, \ + UART5_RX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l0/uart_config.h index 392cf70306c..0779cd94d84 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l0/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l0/uart_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-10-30 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -29,13 +30,29 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ @@ -51,13 +68,29 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/sdio_config.h index 816ab992365..086fcfee74c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/sdio_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-13 BalanceTWK first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SDIO_CONFIG_H__ @@ -19,15 +20,51 @@ extern "C" { #endif #ifdef BSP_USING_SDIO +#ifndef SDIO_RX_DMA_PRIORITY +#define SDIO_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_RX_DMA_PRIORITY */ + +#ifndef SDIO_RX_DMA_PREEMPT_PRIORITY +#define SDIO_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_RX_DMA_SUB_PRIORITY +#define SDIO_RX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_RX_DMA_SUB_PRIORITY */ + +#ifndef SDIO_TX_DMA_PRIORITY +#define SDIO_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_TX_DMA_PRIORITY */ + +#ifndef SDIO_TX_DMA_PREEMPT_PRIORITY +#define SDIO_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_TX_DMA_SUB_PRIORITY +#define SDIO_TX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_TX_DMA_SUB_PRIORITY */ + #define SDIO_BUS_CONFIG \ { \ - .Instance = SDIO, \ - .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Channel4, \ - .dma_rx.dma_irq = DMA2_Channel4_IRQn, \ - .dma_tx.Instance = DMA2_Channel4, \ - .dma_tx.dma_irq = DMA2_Channel4_IRQn, \ + .Instance = SDIO, \ + .dma_rx = STM32_DMA_RX_WORD_CONFIG_INIT_EX( \ + DMA2_Channel4, \ + RCC_AHBENR_DMA2EN, \ + DMA2_Channel4_IRQn, \ + 0U, \ + 0U, \ + SDIO_RX_DMA_PRIORITY, \ + SDIO_RX_DMA_PREEMPT_PRIORITY, \ + SDIO_RX_DMA_SUB_PRIORITY), \ + .dma_tx = STM32_DMA_TX_WORD_CONFIG_INIT_EX( \ + DMA2_Channel4, \ + RCC_AHBENR_DMA2EN, \ + DMA2_Channel4_IRQn, \ + 0U, \ + 0U, \ + SDIO_TX_DMA_PRIORITY, \ + SDIO_TX_DMA_PREEMPT_PRIORITY, \ + SDIO_TX_DMA_SUB_PRIORITY), \ } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/spi_config.h index bd98277cf30..3d53ef8520c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/spi_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version * 2019-01-05 SummerGift modify DMA support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -30,24 +31,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + 0U, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + 0U, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -63,24 +94,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + 0U, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + 0U, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -96,24 +157,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + 0U, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG #define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + 0U, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/uart_config.h index 540f5071f55..ae4ba29b626 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/uart_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-10-30 BalanceTWK first version * 2019-01-05 SummerGift modify DMA support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -30,24 +31,56 @@ extern "C" { #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG #define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG #define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ #endif /* BSP_USING_UART1 */ @@ -63,24 +96,56 @@ extern "C" { #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG #define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG #define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ #endif /* BSP_USING_UART2 */ @@ -96,24 +161,56 @@ extern "C" { #endif /* UART3_CONFIG */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG #define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG #define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ #endif /* BSP_USING_UART3 */ @@ -129,24 +226,56 @@ extern "C" { #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_RX_DMA_PRIORITY +#define UART4_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_RX_DMA_PRIORITY */ + +#ifndef UART4_RX_DMA_PREEMPT_PRIORITY +#define UART4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_RX_DMA_SUB_PRIORITY +#define UART4_RX_DMA_SUB_PRIORITY 0 +#endif /* UART4_RX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_RX_CONFIG #define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .dma_rcc = UART4_RX_DMA_RCC, \ - .dma_irq = UART4_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART4_RX_DMA_INSTANCE, \ + UART4_RX_DMA_RCC, \ + UART4_RX_DMA_IRQ, \ + UART4_RX_DMA_CHANNEL, \ + UART4_RX_DMA_REQUEST, \ + UART4_RX_DMA_PRIORITY, \ + UART4_RX_DMA_PREEMPT_PRIORITY, \ + UART4_RX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_RX_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_TX_DMA_PRIORITY +#define UART4_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_TX_DMA_PRIORITY */ + +#ifndef UART4_TX_DMA_PREEMPT_PRIORITY +#define UART4_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_TX_DMA_SUB_PRIORITY +#define UART4_TX_DMA_SUB_PRIORITY 0 +#endif /* UART4_TX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_TX_CONFIG #define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .dma_rcc = UART4_TX_DMA_RCC, \ - .dma_irq = UART4_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART4_TX_DMA_INSTANCE, \ + UART4_TX_DMA_RCC, \ + UART4_TX_DMA_IRQ, \ + UART4_TX_DMA_CHANNEL, \ + UART4_TX_DMA_REQUEST, \ + UART4_TX_DMA_PRIORITY, \ + UART4_TX_DMA_PREEMPT_PRIORITY, \ + UART4_TX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_TX_CONFIG */ #endif /* BSP_UART4_TX_USING_DMA */ #endif /* BSP_USING_UART4 */ @@ -163,11 +292,29 @@ extern "C" { #endif /* BSP_USING_UART5 */ #if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_RX_DMA_PRIORITY +#define UART5_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_RX_DMA_PRIORITY */ + +#ifndef UART5_RX_DMA_PREEMPT_PRIORITY +#define UART5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_RX_DMA_SUB_PRIORITY +#define UART5_RX_DMA_SUB_PRIORITY 0 +#endif /* UART5_RX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = DMA_NOT_AVAILABLE, \ - } +#define UART5_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART5_RX_DMA_INSTANCE, \ + UART5_RX_DMA_RCC, \ + UART5_RX_DMA_IRQ, \ + UART5_RX_DMA_CHANNEL, \ + UART5_RX_DMA_REQUEST, \ + UART5_RX_DMA_PRIORITY, \ + UART5_RX_DMA_PREEMPT_PRIORITY, \ + UART5_RX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/qspi_config.h index bd89927b9e2..e7d0f96e1d7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/qspi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-22 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __QSPI_CONFIG_H__ @@ -30,19 +31,29 @@ extern "C" { #endif /* BSP_USING_QSPI */ #ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_PRIORITY +#define QSPI_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* QSPI_DMA_PRIORITY */ + +#ifndef QSPI_DMA_PREEMPT_PRIORITY +#define QSPI_DMA_PREEMPT_PRIORITY 0 +#endif /* QSPI_DMA_PREEMPT_PRIORITY */ + +#ifndef QSPI_DMA_SUB_PRIORITY +#define QSPI_DMA_SUB_PRIORITY 0 +#endif /* QSPI_DMA_SUB_PRIORITY */ + #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .Init.Request = QSPI_DMA_REQUEST, \ - .Init.Direction = DMA_PERIPH_TO_MEMORY, \ - .Init.PeriphInc = DMA_PINC_DISABLE, \ - .Init.MemInc = DMA_MINC_ENABLE, \ - .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ - .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ - .Init.Mode = DMA_NORMAL, \ - .Init.Priority = DMA_PRIORITY_LOW \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + QSPI_DMA_INSTANCE, \ + QSPI_DMA_RCC, \ + QSPI_DMA_IRQ, \ + QSPI_DMA_CHANNEL, \ + QSPI_DMA_REQUEST, \ + QSPI_DMA_PRIORITY, \ + QSPI_DMA_PREEMPT_PRIORITY, \ + QSPI_DMA_SUB_PRIORITY) #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/sdio_config.h index 0d0dadfc7f8..c84abe5d2ab 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/sdio_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-13 BalanceTWK first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SDIO_CONFIG_H__ @@ -19,17 +20,51 @@ extern "C" { #endif #ifdef BSP_USING_SDIO +#ifndef SDIO_RX_DMA_PRIORITY +#define SDIO_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_RX_DMA_PRIORITY */ + +#ifndef SDIO_RX_DMA_PREEMPT_PRIORITY +#define SDIO_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_RX_DMA_SUB_PRIORITY +#define SDIO_RX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_RX_DMA_SUB_PRIORITY */ + +#ifndef SDIO_TX_DMA_PRIORITY +#define SDIO_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_TX_DMA_PRIORITY */ + +#ifndef SDIO_TX_DMA_PREEMPT_PRIORITY +#define SDIO_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_TX_DMA_SUB_PRIORITY +#define SDIO_TX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_TX_DMA_SUB_PRIORITY */ + #define SDIO_BUS_CONFIG \ { \ .Instance = SDMMC1, \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Channel4, \ - .dma_rx.request = DMA_REQUEST_7, \ - .dma_rx.dma_irq = DMA2_Channel4_IRQn, \ - .dma_tx.Instance = DMA2_Channel5, \ - .dma_tx.request = DMA_REQUEST_7, \ - .dma_tx.dma_irq = DMA2_Channel5_IRQn, \ + .dma_rx = STM32_DMA_RX_WORD_CONFIG_INIT_EX( \ + DMA2_Channel4, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Channel4_IRQn, \ + 0U, \ + DMA_REQUEST_7, \ + SDIO_RX_DMA_PRIORITY, \ + SDIO_RX_DMA_PREEMPT_PRIORITY, \ + SDIO_RX_DMA_SUB_PRIORITY), \ + .dma_tx = STM32_DMA_TX_WORD_CONFIG_INIT_EX( \ + DMA2_Channel5, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Channel5_IRQn, \ + 0U, \ + DMA_REQUEST_7, \ + SDIO_TX_DMA_PRIORITY, \ + SDIO_TX_DMA_PREEMPT_PRIORITY, \ + SDIO_TX_DMA_SUB_PRIORITY), \ } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/spi_config.h index 2d08508c87c..d8a6640bc32 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/spi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -29,26 +30,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .request = SPI1_TX_DMA_REQUEST, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } +#define SPI1_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + SPI1_TX_DMA_REQUEST, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .request = SPI1_RX_DMA_REQUEST, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } +#define SPI1_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + SPI1_RX_DMA_REQUEST, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -64,26 +93,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .request = SPI2_TX_DMA_REQUEST, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } +#define SPI2_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + SPI2_TX_DMA_REQUEST, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .request = SPI2_RX_DMA_REQUEST, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } +#define SPI2_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + SPI2_RX_DMA_REQUEST, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -99,26 +156,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .request = SPI3_TX_DMA_REQUEST, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } +#define SPI3_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + SPI3_TX_DMA_REQUEST, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .request = SPI3_RX_DMA_REQUEST, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } +#define SPI3_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + SPI3_RX_DMA_REQUEST, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/uart_config.h index a94bb9ea1c7..76dc798adb8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/uart_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -27,14 +28,29 @@ extern "C" { } #endif /* LPUART1_CONFIG */ #if defined(BSP_LPUART1_RX_USING_DMA) +#ifndef LPUART1_DMA_PRIORITY +#define LPUART1_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* LPUART1_DMA_PRIORITY */ + +#ifndef LPUART1_DMA_PREEMPT_PRIORITY +#define LPUART1_DMA_PREEMPT_PRIORITY 0 +#endif /* LPUART1_DMA_PREEMPT_PRIORITY */ + +#ifndef LPUART1_DMA_SUB_PRIORITY +#define LPUART1_DMA_SUB_PRIORITY 0 +#endif /* LPUART1_DMA_SUB_PRIORITY */ + #ifndef LPUART1_DMA_CONFIG #define LPUART1_DMA_CONFIG \ - { \ - .Instance = LPUART1_RX_DMA_INSTANCE, \ - .request = LPUART1_RX_DMA_REQUEST, \ - .dma_rcc = LPUART1_RX_DMA_RCC, \ - .dma_irq = LPUART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + LPUART1_RX_DMA_INSTANCE, \ + LPUART1_RX_DMA_RCC, \ + LPUART1_RX_DMA_IRQ, \ + LPUART1_RX_DMA_CHANNEL, \ + LPUART1_RX_DMA_REQUEST, \ + LPUART1_DMA_PRIORITY, \ + LPUART1_DMA_PREEMPT_PRIORITY, \ + LPUART1_DMA_SUB_PRIORITY) #endif /* LPUART1_DMA_CONFIG */ #endif /* BSP_LPUART1_RX_USING_DMA */ #endif /* BSP_USING_LPUART1 */ @@ -51,26 +67,56 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .request = UART1_RX_DMA_REQUEST, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .request = UART1_TX_DMA_REQUEST, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } +#define UART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -86,26 +132,56 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .request = UART2_RX_DMA_REQUEST, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .request = UART2_TX_DMA_REQUEST, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } +#define UART2_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -121,26 +197,56 @@ extern "C" { #endif /* BSP_USING_UART3 */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .request = UART3_RX_DMA_REQUEST, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .request = UART3_TX_DMA_REQUEST, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } +#define UART3_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/qspi_config.h index bd89927b9e2..e7d0f96e1d7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/qspi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-22 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __QSPI_CONFIG_H__ @@ -30,19 +31,29 @@ extern "C" { #endif /* BSP_USING_QSPI */ #ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_PRIORITY +#define QSPI_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* QSPI_DMA_PRIORITY */ + +#ifndef QSPI_DMA_PREEMPT_PRIORITY +#define QSPI_DMA_PREEMPT_PRIORITY 0 +#endif /* QSPI_DMA_PREEMPT_PRIORITY */ + +#ifndef QSPI_DMA_SUB_PRIORITY +#define QSPI_DMA_SUB_PRIORITY 0 +#endif /* QSPI_DMA_SUB_PRIORITY */ + #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .Init.Request = QSPI_DMA_REQUEST, \ - .Init.Direction = DMA_PERIPH_TO_MEMORY, \ - .Init.PeriphInc = DMA_PINC_DISABLE, \ - .Init.MemInc = DMA_MINC_ENABLE, \ - .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ - .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ - .Init.Mode = DMA_NORMAL, \ - .Init.Priority = DMA_PRIORITY_LOW \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + QSPI_DMA_INSTANCE, \ + QSPI_DMA_RCC, \ + QSPI_DMA_IRQ, \ + QSPI_DMA_CHANNEL, \ + QSPI_DMA_REQUEST, \ + QSPI_DMA_PRIORITY, \ + QSPI_DMA_PREEMPT_PRIORITY, \ + QSPI_DMA_SUB_PRIORITY) #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/sdio_config.h index 2664de50da0..b2db972a1ba 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/sdio_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-13 BalanceTWK first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SDIO_CONFIG_H__ @@ -19,17 +20,51 @@ extern "C" { #endif #ifdef BSP_USING_SDIO +#ifndef SDIO_RX_DMA_PRIORITY +#define SDIO_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_RX_DMA_PRIORITY */ + +#ifndef SDIO_RX_DMA_PREEMPT_PRIORITY +#define SDIO_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_RX_DMA_SUB_PRIORITY +#define SDIO_RX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_RX_DMA_SUB_PRIORITY */ + +#ifndef SDIO_TX_DMA_PRIORITY +#define SDIO_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_TX_DMA_PRIORITY */ + +#ifndef SDIO_TX_DMA_PREEMPT_PRIORITY +#define SDIO_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_TX_DMA_SUB_PRIORITY +#define SDIO_TX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_TX_DMA_SUB_PRIORITY */ + #define SDIO_BUS_CONFIG \ { \ .Instance = SDMMC1, \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Channel4, \ - .dma_rx.request = DMA_REQUEST_7, \ - .dma_rx.dma_irq = DMA2_Channel4_IRQn, \ - .dma_tx.Instance = DMA2_Channel5, \ - .dma_tx.request = DMA_REQUEST_7, \ - .dma_tx.dma_irq = DMA2_Channel5_IRQn, \ + .dma_rx = STM32_DMA_RX_WORD_CONFIG_INIT_EX( \ + DMA2_Channel4, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Channel4_IRQn, \ + 0U, \ + DMA_REQUEST_7, \ + SDIO_RX_DMA_PRIORITY, \ + SDIO_RX_DMA_PREEMPT_PRIORITY, \ + SDIO_RX_DMA_SUB_PRIORITY), \ + .dma_tx = STM32_DMA_TX_WORD_CONFIG_INIT_EX( \ + DMA2_Channel5, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Channel5_IRQn, \ + 0U, \ + DMA_REQUEST_7, \ + SDIO_TX_DMA_PRIORITY, \ + SDIO_TX_DMA_PREEMPT_PRIORITY, \ + SDIO_TX_DMA_SUB_PRIORITY), \ } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/spi_config.h index 2d08508c87c..d8a6640bc32 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/spi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -29,26 +30,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .request = SPI1_TX_DMA_REQUEST, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } +#define SPI1_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + SPI1_TX_DMA_REQUEST, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .request = SPI1_RX_DMA_REQUEST, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } +#define SPI1_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + SPI1_RX_DMA_REQUEST, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -64,26 +93,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .request = SPI2_TX_DMA_REQUEST, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } +#define SPI2_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + SPI2_TX_DMA_REQUEST, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .request = SPI2_RX_DMA_REQUEST, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } +#define SPI2_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + SPI2_RX_DMA_REQUEST, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -99,26 +156,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .request = SPI3_TX_DMA_REQUEST, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } +#define SPI3_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + SPI3_TX_DMA_REQUEST, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .request = SPI3_RX_DMA_REQUEST, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } +#define SPI3_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + SPI3_RX_DMA_REQUEST, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/uart_config.h index a94bb9ea1c7..76dc798adb8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/uart_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -27,14 +28,29 @@ extern "C" { } #endif /* LPUART1_CONFIG */ #if defined(BSP_LPUART1_RX_USING_DMA) +#ifndef LPUART1_DMA_PRIORITY +#define LPUART1_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* LPUART1_DMA_PRIORITY */ + +#ifndef LPUART1_DMA_PREEMPT_PRIORITY +#define LPUART1_DMA_PREEMPT_PRIORITY 0 +#endif /* LPUART1_DMA_PREEMPT_PRIORITY */ + +#ifndef LPUART1_DMA_SUB_PRIORITY +#define LPUART1_DMA_SUB_PRIORITY 0 +#endif /* LPUART1_DMA_SUB_PRIORITY */ + #ifndef LPUART1_DMA_CONFIG #define LPUART1_DMA_CONFIG \ - { \ - .Instance = LPUART1_RX_DMA_INSTANCE, \ - .request = LPUART1_RX_DMA_REQUEST, \ - .dma_rcc = LPUART1_RX_DMA_RCC, \ - .dma_irq = LPUART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + LPUART1_RX_DMA_INSTANCE, \ + LPUART1_RX_DMA_RCC, \ + LPUART1_RX_DMA_IRQ, \ + LPUART1_RX_DMA_CHANNEL, \ + LPUART1_RX_DMA_REQUEST, \ + LPUART1_DMA_PRIORITY, \ + LPUART1_DMA_PREEMPT_PRIORITY, \ + LPUART1_DMA_SUB_PRIORITY) #endif /* LPUART1_DMA_CONFIG */ #endif /* BSP_LPUART1_RX_USING_DMA */ #endif /* BSP_USING_LPUART1 */ @@ -51,26 +67,56 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .request = UART1_RX_DMA_REQUEST, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .request = UART1_TX_DMA_REQUEST, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } +#define UART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -86,26 +132,56 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .request = UART2_RX_DMA_REQUEST, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .request = UART2_TX_DMA_REQUEST, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } +#define UART2_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -121,26 +197,56 @@ extern "C" { #endif /* BSP_USING_UART3 */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .request = UART3_RX_DMA_REQUEST, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .request = UART3_TX_DMA_REQUEST, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } +#define UART3_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/qspi_config.h index a315b2f5cc6..bdecbbc6189 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/qspi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-22 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __QSPI_CONFIG_H__ @@ -30,19 +31,29 @@ extern "C" { #endif /* BSP_USING_QSPI */ #ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_PRIORITY +#define QSPI_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* QSPI_DMA_PRIORITY */ + +#ifndef QSPI_DMA_PREEMPT_PRIORITY +#define QSPI_DMA_PREEMPT_PRIORITY 0 +#endif /* QSPI_DMA_PREEMPT_PRIORITY */ + +#ifndef QSPI_DMA_SUB_PRIORITY +#define QSPI_DMA_SUB_PRIORITY 0 +#endif /* QSPI_DMA_SUB_PRIORITY */ + #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .Init.Channel = QSPI_DMA_CHANNEL, \ - .Init.Direction = DMA_PERIPH_TO_MEMORY, \ - .Init.PeriphInc = DMA_PINC_DISABLE, \ - .Init.MemInc = DMA_MINC_ENABLE, \ - .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ - .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ - .Init.Mode = DMA_NORMAL, \ - .Init.Priority = DMA_PRIORITY_LOW \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + QSPI_DMA_INSTANCE, \ + QSPI_DMA_RCC, \ + QSPI_DMA_IRQ, \ + QSPI_DMA_CHANNEL, \ + 0U, \ + QSPI_DMA_PRIORITY, \ + QSPI_DMA_PREEMPT_PRIORITY, \ + QSPI_DMA_SUB_PRIORITY) #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/spi_config.h index d12a1071c05..4955b9ea24f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/spi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -29,26 +30,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .request = SPI1_TX_DMA_CHANNEL, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + SPI1_TX_DMA_CHANNEL, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .request = SPI1_RX_DMA_CHANNEL, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + SPI1_RX_DMA_CHANNEL, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -64,26 +93,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .request = SPI2_TX_DMA_CHANNEL, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + SPI2_TX_DMA_CHANNEL, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .request = SPI2_RX_DMA_CHANNEL, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + SPI2_RX_DMA_CHANNEL, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -99,26 +156,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .request = SPI3_TX_DMA_CHANNEL, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + SPI3_TX_DMA_CHANNEL, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG #define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .request = SPI3_RX_DMA_CHANNEL, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + SPI3_RX_DMA_CHANNEL, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ @@ -134,26 +219,54 @@ extern "C" { #endif /* BSP_USING_SPI4 */ #ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_PRIORITY +#define SPI4_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI4_TX_DMA_PRIORITY */ + +#ifndef SPI4_TX_DMA_PREEMPT_PRIORITY +#define SPI4_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_TX_DMA_SUB_PRIORITY +#define SPI4_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_TX_DMA_SUB_PRIORITY */ #ifndef SPI4_TX_DMA_CONFIG #define SPI4_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI4_TX_DMA_RCC, \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .request = SPI4_TX_DMA_CHANNEL, \ - .dma_irq = SPI4_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI4_TX_DMA_INSTANCE, \ + SPI4_TX_DMA_RCC, \ + SPI4_TX_DMA_IRQ, \ + SPI4_TX_DMA_CHANNEL, \ + SPI4_TX_DMA_CHANNEL, \ + SPI4_TX_DMA_PRIORITY, \ + SPI4_TX_DMA_PREEMPT_PRIORITY, \ + SPI4_TX_DMA_SUB_PRIORITY) #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ #ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_PRIORITY +#define SPI4_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI4_RX_DMA_PRIORITY */ + +#ifndef SPI4_RX_DMA_PREEMPT_PRIORITY +#define SPI4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_RX_DMA_SUB_PRIORITY +#define SPI4_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_RX_DMA_SUB_PRIORITY */ #ifndef SPI4_RX_DMA_CONFIG #define SPI4_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI4_RX_DMA_RCC, \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .request = SPI4_RX_DMA_CHANNEL, \ - .dma_irq = SPI4_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI4_RX_DMA_INSTANCE, \ + SPI4_RX_DMA_RCC, \ + SPI4_RX_DMA_IRQ, \ + SPI4_RX_DMA_CHANNEL, \ + SPI4_RX_DMA_CHANNEL, \ + SPI4_RX_DMA_PRIORITY, \ + SPI4_RX_DMA_PREEMPT_PRIORITY, \ + SPI4_RX_DMA_SUB_PRIORITY) #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ @@ -169,26 +282,54 @@ extern "C" { #endif /* BSP_USING_SPI5 */ #ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_PRIORITY +#define SPI5_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI5_TX_DMA_PRIORITY */ + +#ifndef SPI5_TX_DMA_PREEMPT_PRIORITY +#define SPI5_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI5_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_TX_DMA_SUB_PRIORITY +#define SPI5_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_TX_DMA_SUB_PRIORITY */ #ifndef SPI5_TX_DMA_CONFIG #define SPI5_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI5_TX_DMA_RCC, \ - .Instance = SPI5_TX_DMA_INSTANCE, \ - .request = SPI5_TX_DMA_CHANNEL, \ - .dma_irq = SPI5_TX_DMA_IRQ, \ - } + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI5_TX_DMA_INSTANCE, \ + SPI5_TX_DMA_RCC, \ + SPI5_TX_DMA_IRQ, \ + SPI5_TX_DMA_CHANNEL, \ + SPI5_TX_DMA_CHANNEL, \ + SPI5_TX_DMA_PRIORITY, \ + SPI5_TX_DMA_PREEMPT_PRIORITY, \ + SPI5_TX_DMA_SUB_PRIORITY) #endif /* SPI5_TX_DMA_CONFIG */ #endif /* BSP_SPI5_TX_USING_DMA */ #ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_PRIORITY +#define SPI5_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI5_RX_DMA_PRIORITY */ + +#ifndef SPI5_RX_DMA_PREEMPT_PRIORITY +#define SPI5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_RX_DMA_SUB_PRIORITY +#define SPI5_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_RX_DMA_SUB_PRIORITY */ #ifndef SPI5_RX_DMA_CONFIG #define SPI5_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI5_RX_DMA_RCC, \ - .Instance = SPI5_RX_DMA_INSTANCE, \ - .request = SPI5_RX_DMA_CHANNEL, \ - .dma_irq = SPI5_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI5_RX_DMA_INSTANCE, \ + SPI5_RX_DMA_RCC, \ + SPI5_RX_DMA_IRQ, \ + SPI5_RX_DMA_CHANNEL, \ + SPI5_RX_DMA_CHANNEL, \ + SPI5_RX_DMA_PRIORITY, \ + SPI5_RX_DMA_PREEMPT_PRIORITY, \ + SPI5_RX_DMA_SUB_PRIORITY) #endif /* SPI5_RX_DMA_CONFIG */ #endif /* BSP_SPI5_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/uart_config.h index c9107be191f..8e923b5d3e7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/uart_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version * 2019-01-03 zylx modify dma support + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -29,26 +30,56 @@ extern "C" { #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .request = UART1_RX_DMA_CHANNEL, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .request = UART1_TX_DMA_CHANNEL, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } +#define UART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ #endif /* BSP_USING_UART1 */ @@ -64,26 +95,56 @@ extern "C" { #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .request = UART2_RX_DMA_CHANNEL, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .request = UART2_TX_DMA_CHANNEL, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } +#define UART2_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ #endif /* BSP_USING_UART2 */ @@ -99,26 +160,56 @@ extern "C" { #endif /* UART3_CONFIG */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .request = UART3_RX_DMA_CHANNEL, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .request = UART3_TX_DMA_CHANNEL, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } +#define UART3_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ #endif /* BSP_USING_UART3 */ @@ -134,28 +225,58 @@ extern "C" { #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_RX_DMA_PRIORITY +#define UART4_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_RX_DMA_PRIORITY */ + +#ifndef UART4_RX_DMA_PREEMPT_PRIORITY +#define UART4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_RX_DMA_SUB_PRIORITY +#define UART4_RX_DMA_SUB_PRIORITY 0 +#endif /* UART4_RX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .request = UART4_RX_DMA_CHANNEL, \ - .dma_rcc = UART4_RX_DMA_RCC, \ - .dma_irq = UART4_RX_DMA_IRQ, \ - } +#define UART4_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART4_RX_DMA_INSTANCE, \ + UART4_RX_DMA_RCC, \ + UART4_RX_DMA_IRQ, \ + UART4_RX_DMA_CHANNEL, \ + UART4_RX_DMA_CHANNEL, \ + UART4_RX_DMA_PRIORITY, \ + UART4_RX_DMA_PREEMPT_PRIORITY, \ + UART4_RX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_RX_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_TX_DMA_PRIORITY +#define UART4_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART4_TX_DMA_PRIORITY */ + +#ifndef UART4_TX_DMA_PREEMPT_PRIORITY +#define UART4_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART4_TX_DMA_SUB_PRIORITY +#define UART4_TX_DMA_SUB_PRIORITY 0 +#endif /* UART4_TX_DMA_SUB_PRIORITY */ + #ifndef UART4_DMA_TX_CONFIG -#define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .request = UART4_TX_DMA_CHANNEL, \ - .dma_rcc = UART4_TX_DMA_RCC, \ - .dma_irq = UART4_TX_DMA_IRQ, \ - } +#define UART4_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART4_TX_DMA_INSTANCE, \ + UART4_TX_DMA_RCC, \ + UART4_TX_DMA_IRQ, \ + UART4_TX_DMA_CHANNEL, \ + UART4_TX_DMA_CHANNEL, \ + UART4_TX_DMA_PRIORITY, \ + UART4_TX_DMA_PREEMPT_PRIORITY, \ + UART4_TX_DMA_SUB_PRIORITY) #endif /* UART4_DMA_TX_CONFIG */ -#endif /* BSP_UART4_RX_USING_DMA */ +#endif /* BSP_UART4_TX_USING_DMA */ #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_UART5) @@ -169,26 +290,56 @@ extern "C" { #endif /* UART5_CONFIG */ #if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_RX_DMA_PRIORITY +#define UART5_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_RX_DMA_PRIORITY */ + +#ifndef UART5_RX_DMA_PREEMPT_PRIORITY +#define UART5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_RX_DMA_SUB_PRIORITY +#define UART5_RX_DMA_SUB_PRIORITY 0 +#endif /* UART5_RX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .request = UART5_RX_DMA_CHANNEL, \ - .dma_rcc = UART5_RX_DMA_RCC, \ - .dma_irq = UART5_RX_DMA_IRQ, \ - } +#define UART5_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART5_RX_DMA_INSTANCE, \ + UART5_RX_DMA_RCC, \ + UART5_RX_DMA_IRQ, \ + UART5_RX_DMA_CHANNEL, \ + UART5_RX_DMA_CHANNEL, \ + UART5_RX_DMA_PRIORITY, \ + UART5_RX_DMA_PREEMPT_PRIORITY, \ + UART5_RX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ #if defined(BSP_UART5_TX_USING_DMA) +#ifndef UART5_TX_DMA_PRIORITY +#define UART5_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART5_TX_DMA_PRIORITY */ + +#ifndef UART5_TX_DMA_PREEMPT_PRIORITY +#define UART5_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART5_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART5_TX_DMA_SUB_PRIORITY +#define UART5_TX_DMA_SUB_PRIORITY 0 +#endif /* UART5_TX_DMA_SUB_PRIORITY */ + #ifndef UART5_DMA_TX_CONFIG -#define UART5_DMA_TX_CONFIG \ - { \ - .Instance = UART5_TX_DMA_INSTANCE, \ - .request = UART5_TX_DMA_CHANNEL, \ - .dma_rcc = UART5_TX_DMA_RCC, \ - .dma_irq = UART5_TX_DMA_IRQ, \ - } +#define UART5_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART5_TX_DMA_INSTANCE, \ + UART5_TX_DMA_RCC, \ + UART5_TX_DMA_IRQ, \ + UART5_TX_DMA_CHANNEL, \ + UART5_TX_DMA_CHANNEL, \ + UART5_TX_DMA_PRIORITY, \ + UART5_TX_DMA_PREEMPT_PRIORITY, \ + UART5_TX_DMA_SUB_PRIORITY) #endif /* UART5_DMA_TX_CONFIG */ #endif /* BSP_UART5_TX_USING_DMA */ #endif /* BSP_USING_UART5 */ @@ -204,26 +355,56 @@ extern "C" { #endif /* UART6_CONFIG */ #if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_RX_DMA_PRIORITY +#define UART6_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART6_RX_DMA_PRIORITY */ + +#ifndef UART6_RX_DMA_PREEMPT_PRIORITY +#define UART6_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART6_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART6_RX_DMA_SUB_PRIORITY +#define UART6_RX_DMA_SUB_PRIORITY 0 +#endif /* UART6_RX_DMA_SUB_PRIORITY */ + #ifndef UART6_DMA_RX_CONFIG -#define UART6_DMA_RX_CONFIG \ - { \ - .Instance = UART6_RX_DMA_INSTANCE, \ - .request = UART6_RX_DMA_CHANNEL, \ - .dma_rcc = UART6_RX_DMA_RCC, \ - .dma_irq = UART6_RX_DMA_IRQ, \ - } +#define UART6_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART6_RX_DMA_INSTANCE, \ + UART6_RX_DMA_RCC, \ + UART6_RX_DMA_IRQ, \ + UART6_RX_DMA_CHANNEL, \ + UART6_RX_DMA_CHANNEL, \ + UART6_RX_DMA_PRIORITY, \ + UART6_RX_DMA_PREEMPT_PRIORITY, \ + UART6_RX_DMA_SUB_PRIORITY) #endif /* UART6_DMA_RX_CONFIG */ #endif /* BSP_UART6_RX_USING_DMA */ #if defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_TX_DMA_PRIORITY +#define UART6_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART6_TX_DMA_PRIORITY */ + +#ifndef UART6_TX_DMA_PREEMPT_PRIORITY +#define UART6_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART6_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART6_TX_DMA_SUB_PRIORITY +#define UART6_TX_DMA_SUB_PRIORITY 0 +#endif /* UART6_TX_DMA_SUB_PRIORITY */ + #ifndef UART6_DMA_TX_CONFIG -#define UART6_DMA_TX_CONFIG \ - { \ - .Instance = UART6_TX_DMA_INSTANCE, \ - .request = UART6_TX_DMA_CHANNEL, \ - .dma_rcc = UART6_TX_DMA_RCC, \ - .dma_irq = UART6_TX_DMA_IRQ, \ - } +#define UART6_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART6_TX_DMA_INSTANCE, \ + UART6_TX_DMA_RCC, \ + UART6_TX_DMA_IRQ, \ + UART6_TX_DMA_CHANNEL, \ + UART6_TX_DMA_CHANNEL, \ + UART6_TX_DMA_PRIORITY, \ + UART6_TX_DMA_PREEMPT_PRIORITY, \ + UART6_TX_DMA_SUB_PRIORITY) #endif /* UART6_DMA_TX_CONFIG */ #endif /* BSP_UART6_TX_USING_DMA */ #endif /* BSP_USING_UART6 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/qspi_config.h index bd89927b9e2..e7d0f96e1d7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/qspi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-22 zylx first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __QSPI_CONFIG_H__ @@ -30,19 +31,29 @@ extern "C" { #endif /* BSP_USING_QSPI */ #ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_PRIORITY +#define QSPI_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* QSPI_DMA_PRIORITY */ + +#ifndef QSPI_DMA_PREEMPT_PRIORITY +#define QSPI_DMA_PREEMPT_PRIORITY 0 +#endif /* QSPI_DMA_PREEMPT_PRIORITY */ + +#ifndef QSPI_DMA_SUB_PRIORITY +#define QSPI_DMA_SUB_PRIORITY 0 +#endif /* QSPI_DMA_SUB_PRIORITY */ + #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .Init.Request = QSPI_DMA_REQUEST, \ - .Init.Direction = DMA_PERIPH_TO_MEMORY, \ - .Init.PeriphInc = DMA_PINC_DISABLE, \ - .Init.MemInc = DMA_MINC_ENABLE, \ - .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ - .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ - .Init.Mode = DMA_NORMAL, \ - .Init.Priority = DMA_PRIORITY_LOW \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + QSPI_DMA_INSTANCE, \ + QSPI_DMA_RCC, \ + QSPI_DMA_IRQ, \ + QSPI_DMA_CHANNEL, \ + QSPI_DMA_REQUEST, \ + QSPI_DMA_PRIORITY, \ + QSPI_DMA_PREEMPT_PRIORITY, \ + QSPI_DMA_SUB_PRIORITY) #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/sdio_config.h index b61d870db59..9f123515e18 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/sdio_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/sdio_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-13 BalanceTWK first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SDIO_CONFIG_H__ @@ -19,17 +20,51 @@ extern "C" { #endif #ifdef BSP_USING_SDIO +#ifndef SDIO_RX_DMA_PRIORITY +#define SDIO_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_RX_DMA_PRIORITY */ + +#ifndef SDIO_RX_DMA_PREEMPT_PRIORITY +#define SDIO_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_RX_DMA_SUB_PRIORITY +#define SDIO_RX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_RX_DMA_SUB_PRIORITY */ + +#ifndef SDIO_TX_DMA_PRIORITY +#define SDIO_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* SDIO_TX_DMA_PRIORITY */ + +#ifndef SDIO_TX_DMA_PREEMPT_PRIORITY +#define SDIO_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* SDIO_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SDIO_TX_DMA_SUB_PRIORITY +#define SDIO_TX_DMA_SUB_PRIORITY 0 +#endif /* SDIO_TX_DMA_SUB_PRIORITY */ + #define SDIO_BUS_CONFIG \ { \ .Instance = SDMMC1, \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Channel4, \ - .dma_rx.request = DMA_REQUEST_7, \ - .dma_rx.dma_irq = DMA2_Channel4_IRQn, \ - .dma_tx.Instance = DMA2_Channel5, \ - .dma_tx.request = DMA_REQUEST_7, \ - .dma_tx.dma_irq = DMA2_Channel5_IRQn, \ + .dma_rx = STM32_DMA_RX_WORD_CONFIG_INIT_EX( \ + DMA2_Channel4, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Channel4_IRQn, \ + 0U, \ + DMA_REQUEST_7, \ + SDIO_RX_DMA_PRIORITY, \ + SDIO_RX_DMA_PREEMPT_PRIORITY, \ + SDIO_RX_DMA_SUB_PRIORITY), \ + .dma_tx = STM32_DMA_TX_WORD_CONFIG_INIT_EX( \ + DMA2_Channel5, \ + RCC_AHB1ENR_DMA2EN, \ + DMA2_Channel5_IRQn, \ + 0U, \ + DMA_REQUEST_7, \ + SDIO_TX_DMA_PRIORITY, \ + SDIO_TX_DMA_PREEMPT_PRIORITY, \ + SDIO_TX_DMA_SUB_PRIORITY), \ } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/spi_config.h index 2d08508c87c..d8a6640bc32 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/spi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -29,26 +30,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .request = SPI1_TX_DMA_REQUEST, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } +#define SPI1_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + SPI1_TX_DMA_REQUEST, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .request = SPI1_RX_DMA_REQUEST, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } +#define SPI1_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + SPI1_RX_DMA_REQUEST, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -64,26 +93,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .request = SPI2_TX_DMA_REQUEST, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } +#define SPI2_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + SPI2_TX_DMA_REQUEST, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .request = SPI2_RX_DMA_REQUEST, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } +#define SPI2_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + SPI2_RX_DMA_REQUEST, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -99,26 +156,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .request = SPI3_TX_DMA_REQUEST, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } +#define SPI3_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + SPI3_TX_DMA_REQUEST, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .request = SPI3_RX_DMA_REQUEST, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } +#define SPI3_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + SPI3_RX_DMA_REQUEST, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/uart_config.h index a94bb9ea1c7..76dc798adb8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/uart_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -27,14 +28,29 @@ extern "C" { } #endif /* LPUART1_CONFIG */ #if defined(BSP_LPUART1_RX_USING_DMA) +#ifndef LPUART1_DMA_PRIORITY +#define LPUART1_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* LPUART1_DMA_PRIORITY */ + +#ifndef LPUART1_DMA_PREEMPT_PRIORITY +#define LPUART1_DMA_PREEMPT_PRIORITY 0 +#endif /* LPUART1_DMA_PREEMPT_PRIORITY */ + +#ifndef LPUART1_DMA_SUB_PRIORITY +#define LPUART1_DMA_SUB_PRIORITY 0 +#endif /* LPUART1_DMA_SUB_PRIORITY */ + #ifndef LPUART1_DMA_CONFIG #define LPUART1_DMA_CONFIG \ - { \ - .Instance = LPUART1_RX_DMA_INSTANCE, \ - .request = LPUART1_RX_DMA_REQUEST, \ - .dma_rcc = LPUART1_RX_DMA_RCC, \ - .dma_irq = LPUART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + LPUART1_RX_DMA_INSTANCE, \ + LPUART1_RX_DMA_RCC, \ + LPUART1_RX_DMA_IRQ, \ + LPUART1_RX_DMA_CHANNEL, \ + LPUART1_RX_DMA_REQUEST, \ + LPUART1_DMA_PRIORITY, \ + LPUART1_DMA_PREEMPT_PRIORITY, \ + LPUART1_DMA_SUB_PRIORITY) #endif /* LPUART1_DMA_CONFIG */ #endif /* BSP_LPUART1_RX_USING_DMA */ #endif /* BSP_USING_LPUART1 */ @@ -51,26 +67,56 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .request = UART1_RX_DMA_REQUEST, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .request = UART1_TX_DMA_REQUEST, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } +#define UART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -86,26 +132,56 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .request = UART2_RX_DMA_REQUEST, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .request = UART2_TX_DMA_REQUEST, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } +#define UART2_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -121,26 +197,56 @@ extern "C" { #endif /* BSP_USING_UART3 */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .request = UART3_RX_DMA_REQUEST, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .request = UART3_TX_DMA_REQUEST, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } +#define UART3_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/qspi_config.h index 60964576c59..0237cb1a6d8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/qspi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2020-10-14 PeakRacing first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __QSPI_CONFIG_H__ @@ -30,19 +31,29 @@ extern "C" { #endif /* BSP_USING_QSPI */ #ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_PRIORITY +#define QSPI_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* QSPI_DMA_PRIORITY */ + +#ifndef QSPI_DMA_PREEMPT_PRIORITY +#define QSPI_DMA_PREEMPT_PRIORITY 0 +#endif /* QSPI_DMA_PREEMPT_PRIORITY */ + +#ifndef QSPI_DMA_SUB_PRIORITY +#define QSPI_DMA_SUB_PRIORITY 0 +#endif /* QSPI_DMA_SUB_PRIORITY */ + #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .Init.Request = QSPI_DMA_REQUEST, \ - .Init.Direction = DMA_PERIPH_TO_MEMORY, \ - .Init.PeriphInc = DMA_PINC_DISABLE, \ - .Init.MemInc = DMA_MINC_ENABLE, \ - .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ - .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ - .Init.Mode = DMA_NORMAL, \ - .Init.Priority = DMA_PRIORITY_LOW \ - } + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + QSPI_DMA_INSTANCE, \ + QSPI_DMA_RCC, \ + QSPI_DMA_IRQ, \ + QSPI_DMA_CHANNEL, \ + QSPI_DMA_REQUEST, \ + QSPI_DMA_PRIORITY, \ + QSPI_DMA_PREEMPT_PRIORITY, \ + QSPI_DMA_SUB_PRIORITY) #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/spi_config.h index fa63a162de3..5c1c2ed859c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/spi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2020-10-14 PeakRacing first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -29,26 +30,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .request = SPI1_TX_DMA_REQUEST, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } +#define SPI1_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + SPI1_TX_DMA_REQUEST, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .request = SPI1_RX_DMA_REQUEST, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } +#define SPI1_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + SPI1_RX_DMA_REQUEST, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -64,26 +93,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .request = SPI2_TX_DMA_REQUEST, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } +#define SPI2_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + SPI2_TX_DMA_REQUEST, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .request = SPI2_RX_DMA_REQUEST, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } +#define SPI2_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + SPI2_RX_DMA_REQUEST, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -99,26 +156,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .request = SPI3_TX_DMA_REQUEST, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } +#define SPI3_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + SPI3_TX_DMA_REQUEST, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .request = SPI3_RX_DMA_REQUEST, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } +#define SPI3_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + SPI3_RX_DMA_REQUEST, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/uart_config.h index b36e7bd94ca..ebf438b3f06 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/uart_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2020-10-14 PeakRacing first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -27,14 +28,29 @@ extern "C" { } #endif /* LPUART1_CONFIG */ #if defined(BSP_LPUART1_RX_USING_DMA) +#ifndef LPUART1_DMA_PRIORITY +#define LPUART1_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* LPUART1_DMA_PRIORITY */ + +#ifndef LPUART1_DMA_PREEMPT_PRIORITY +#define LPUART1_DMA_PREEMPT_PRIORITY 0 +#endif /* LPUART1_DMA_PREEMPT_PRIORITY */ + +#ifndef LPUART1_DMA_SUB_PRIORITY +#define LPUART1_DMA_SUB_PRIORITY 0 +#endif /* LPUART1_DMA_SUB_PRIORITY */ + #ifndef LPUART1_DMA_CONFIG #define LPUART1_DMA_CONFIG \ - { \ - .Instance = LPUART1_RX_DMA_INSTANCE, \ - .request = LPUART1_RX_DMA_REQUEST, \ - .dma_rcc = LPUART1_RX_DMA_RCC, \ - .dma_irq = LPUART1_RX_DMA_IRQ, \ - } + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + LPUART1_RX_DMA_INSTANCE, \ + LPUART1_RX_DMA_RCC, \ + LPUART1_RX_DMA_IRQ, \ + LPUART1_RX_DMA_CHANNEL, \ + LPUART1_RX_DMA_REQUEST, \ + LPUART1_DMA_PRIORITY, \ + LPUART1_DMA_PREEMPT_PRIORITY, \ + LPUART1_DMA_SUB_PRIORITY) #endif /* LPUART1_DMA_CONFIG */ #endif /* BSP_LPUART1_RX_USING_DMA */ #endif /* BSP_USING_LPUART1 */ @@ -51,26 +67,56 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .request = UART1_RX_DMA_REQUEST, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_DMA_PRIORITY +#define UART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_TX_DMA_PRIORITY */ + +#ifndef UART1_TX_DMA_PREEMPT_PRIORITY +#define UART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_TX_DMA_SUB_PRIORITY +#define UART1_TX_DMA_SUB_PRIORITY 0 +#endif /* UART1_TX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .request = UART1_TX_DMA_REQUEST, \ - .dma_rcc = UART1_TX_DMA_RCC, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - } +#define UART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART1_TX_DMA_INSTANCE, \ + UART1_TX_DMA_RCC, \ + UART1_TX_DMA_IRQ, \ + UART1_TX_DMA_CHANNEL, \ + UART1_TX_DMA_REQUEST, \ + UART1_TX_DMA_PRIORITY, \ + UART1_TX_DMA_PREEMPT_PRIORITY, \ + UART1_TX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -86,26 +132,56 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .request = UART2_RX_DMA_REQUEST, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_DMA_PRIORITY +#define UART2_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_TX_DMA_PRIORITY */ + +#ifndef UART2_TX_DMA_PREEMPT_PRIORITY +#define UART2_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_TX_DMA_SUB_PRIORITY +#define UART2_TX_DMA_SUB_PRIORITY 0 +#endif /* UART2_TX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .request = UART2_TX_DMA_REQUEST, \ - .dma_rcc = UART2_TX_DMA_RCC, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - } +#define UART2_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART2_TX_DMA_INSTANCE, \ + UART2_TX_DMA_RCC, \ + UART2_TX_DMA_IRQ, \ + UART2_TX_DMA_CHANNEL, \ + UART2_TX_DMA_REQUEST, \ + UART2_TX_DMA_PRIORITY, \ + UART2_TX_DMA_PREEMPT_PRIORITY, \ + UART2_TX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -121,26 +197,56 @@ extern "C" { #endif /* BSP_USING_UART3 */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .request = UART3_RX_DMA_REQUEST, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_DMA_PRIORITY +#define UART3_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_TX_DMA_PRIORITY */ + +#ifndef UART3_TX_DMA_PREEMPT_PRIORITY +#define UART3_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_TX_DMA_SUB_PRIORITY +#define UART3_TX_DMA_SUB_PRIORITY 0 +#endif /* UART3_TX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .request = UART3_TX_DMA_REQUEST, \ - .dma_rcc = UART3_TX_DMA_RCC, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - } +#define UART3_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + UART3_TX_DMA_INSTANCE, \ + UART3_TX_DMA_RCC, \ + UART3_TX_DMA_IRQ, \ + UART3_TX_DMA_CHANNEL, \ + UART3_TX_DMA_REQUEST, \ + UART3_TX_DMA_PRIORITY, \ + UART3_TX_DMA_PREEMPT_PRIORITY, \ + UART3_TX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/spi_config.h index 5c271ac97ae..a2226b3671f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/spi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __SPI_CONFIG_H__ @@ -29,26 +30,54 @@ extern "C" { #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_TX_DMA_RCC, \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .request = SPI1_TX_DMA_REQUEST, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - } +#define SPI1_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_CHANNEL, \ + SPI1_TX_DMA_REQUEST, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI1_RX_DMA_RCC, \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .request = SPI1_RX_DMA_REQUEST, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - } +#define SPI1_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_CHANNEL, \ + SPI1_RX_DMA_REQUEST, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -64,26 +93,54 @@ extern "C" { #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_TX_DMA_RCC, \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .request = SPI2_TX_DMA_REQUEST, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - } +#define SPI2_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_CHANNEL, \ + SPI2_TX_DMA_REQUEST, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI2_RX_DMA_RCC, \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .request = SPI2_RX_DMA_REQUEST, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - } +#define SPI2_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_CHANNEL, \ + SPI2_RX_DMA_REQUEST, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -99,26 +156,54 @@ extern "C" { #endif /* BSP_USING_SPI3 */ #ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_TX_DMA_RCC, \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .request = SPI3_TX_DMA_REQUEST, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - } +#define SPI3_TX_DMA_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_CHANNEL, \ + SPI3_TX_DMA_REQUEST, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .dma_rcc = SPI3_RX_DMA_RCC, \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .request = SPI3_RX_DMA_REQUEST, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - } +#define SPI3_RX_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_CHANNEL, \ + SPI3_RX_DMA_REQUEST, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/uart_config.h index b6d5f3edb27..026e6d1e7ce 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/uart_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2026-04-13 wdfk-prog Unify DMA config descriptors */ #ifndef __UART_CONFIG_H__ @@ -27,29 +28,60 @@ extern "C" { } #endif /* LPUART1_CONFIG */ #if defined(BSP_LPUART1_RX_USING_DMA) -#ifndef LPUART1_DMA_RX_CONFIG -#define LPUART1_DMA_RX_CONFIG \ - { \ - .Instance = LPUART1_RX_DMA_INSTANCE, \ - .request = LPUART1_RX_DMA_REQUEST, \ - .dma_rcc = LPUART1_RX_DMA_RCC, \ - .dma_irq = LPUART1_RX_DMA_IRQ, \ - } +#ifndef LPUART1_DMA_PRIORITY +#define LPUART1_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* LPUART1_DMA_PRIORITY */ + +#ifndef LPUART1_DMA_PREEMPT_PRIORITY +#define LPUART1_DMA_PREEMPT_PRIORITY 0 +#endif /* LPUART1_DMA_PREEMPT_PRIORITY */ + +#ifndef LPUART1_DMA_SUB_PRIORITY +#define LPUART1_DMA_SUB_PRIORITY 0 +#endif /* LPUART1_DMA_SUB_PRIORITY */ + +#ifndef LPUART1_DMA_CONFIG +#define LPUART1_DMA_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + LPUART1_RX_DMA_INSTANCE, \ + LPUART1_RX_DMA_RCC, \ + LPUART1_RX_DMA_IRQ, \ + LPUART1_RX_DMA_CHANNEL, \ + LPUART1_RX_DMA_REQUEST, \ + LPUART1_DMA_PRIORITY, \ + LPUART1_DMA_PREEMPT_PRIORITY, \ + LPUART1_DMA_SUB_PRIORITY) #endif /* LPUART1_DMA_CONFIG */ #endif /* BSP_LPUART1_RX_USING_DMA */ #if defined(BSP_LPUART1_TX_USING_DMA) +#ifndef LPUART1_TX_DMA_PRIORITY +#define LPUART1_TX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* LPUART1_TX_DMA_PRIORITY */ + +#ifndef LPUART1_TX_DMA_PREEMPT_PRIORITY +#define LPUART1_TX_DMA_PREEMPT_PRIORITY 0 +#endif /* LPUART1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef LPUART1_TX_DMA_SUB_PRIORITY +#define LPUART1_TX_DMA_SUB_PRIORITY 0 +#endif /* LPUART1_TX_DMA_SUB_PRIORITY */ + #ifndef LPUART1_DMA_TX_CONFIG -#define LPUART1_DMA_TX_CONFIG \ - { \ - .Instance = LPUART1_TX_DMA_INSTANCE, \ - .dma_rcc = LPUART1_TX_DMA_RCC, \ - .dma_irq = LPUART1_TX_DMA_IRQ, \ - } -#endif /* UART1_DMA_TX_CONFIG */ -#endif /* BSP_UART1_TX_USING_DMA */ -#endif /* BSP_USING_UART1 */ +#define LPUART1_DMA_TX_CONFIG \ + STM32_DMA_TX_BYTE_CONFIG_INIT_EX( \ + LPUART1_TX_DMA_INSTANCE, \ + LPUART1_TX_DMA_RCC, \ + LPUART1_TX_DMA_IRQ, \ + LPUART1_TX_DMA_CHANNEL, \ + LPUART1_TX_DMA_REQUEST, \ + LPUART1_TX_DMA_PRIORITY, \ + LPUART1_TX_DMA_PREEMPT_PRIORITY, \ + LPUART1_TX_DMA_SUB_PRIORITY) +#endif /* LPUART1_DMA_TX_CONFIG */ +#endif /* BSP_LPUART1_TX_USING_DMA */ +#endif /* BSP_USING_LPUART1 */ #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG @@ -63,14 +95,29 @@ extern "C" { #endif /* BSP_USING_UART1 */ #if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_RX_DMA_PRIORITY +#define UART1_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART1_RX_DMA_PRIORITY */ + +#ifndef UART1_RX_DMA_PREEMPT_PRIORITY +#define UART1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART1_RX_DMA_SUB_PRIORITY +#define UART1_RX_DMA_SUB_PRIORITY 0 +#endif /* UART1_RX_DMA_SUB_PRIORITY */ + #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .request = UART1_RX_DMA_REQUEST, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } +#define UART1_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART1_RX_DMA_INSTANCE, \ + UART1_RX_DMA_RCC, \ + UART1_RX_DMA_IRQ, \ + UART1_RX_DMA_CHANNEL, \ + UART1_RX_DMA_REQUEST, \ + UART1_RX_DMA_PRIORITY, \ + UART1_RX_DMA_PREEMPT_PRIORITY, \ + UART1_RX_DMA_SUB_PRIORITY) #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ @@ -86,14 +133,29 @@ extern "C" { #endif /* BSP_USING_UART2 */ #if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_RX_DMA_PRIORITY +#define UART2_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART2_RX_DMA_PRIORITY */ + +#ifndef UART2_RX_DMA_PREEMPT_PRIORITY +#define UART2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART2_RX_DMA_SUB_PRIORITY +#define UART2_RX_DMA_SUB_PRIORITY 0 +#endif /* UART2_RX_DMA_SUB_PRIORITY */ + #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .request = UART2_RX_DMA_REQUEST, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } +#define UART2_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART2_RX_DMA_INSTANCE, \ + UART2_RX_DMA_RCC, \ + UART2_RX_DMA_IRQ, \ + UART2_RX_DMA_CHANNEL, \ + UART2_RX_DMA_REQUEST, \ + UART2_RX_DMA_PRIORITY, \ + UART2_RX_DMA_PREEMPT_PRIORITY, \ + UART2_RX_DMA_SUB_PRIORITY) #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ @@ -109,14 +171,29 @@ extern "C" { #endif /* BSP_USING_UART3 */ #if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_RX_DMA_PRIORITY +#define UART3_RX_DMA_PRIORITY DMA_PRIORITY_MEDIUM +#endif /* UART3_RX_DMA_PRIORITY */ + +#ifndef UART3_RX_DMA_PREEMPT_PRIORITY +#define UART3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* UART3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef UART3_RX_DMA_SUB_PRIORITY +#define UART3_RX_DMA_SUB_PRIORITY 0 +#endif /* UART3_RX_DMA_SUB_PRIORITY */ + #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .request = UART3_RX_DMA_REQUEST, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - } +#define UART3_DMA_RX_CONFIG \ + STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX( \ + UART3_RX_DMA_INSTANCE, \ + UART3_RX_DMA_RCC, \ + UART3_RX_DMA_IRQ, \ + UART3_RX_DMA_CHANNEL, \ + UART3_RX_DMA_REQUEST, \ + UART3_RX_DMA_PRIORITY, \ + UART3_RX_DMA_PREEMPT_PRIORITY, \ + UART3_RX_DMA_SUB_PRIORITY) #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h index a95d43f040c..ff02efa64ca 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h @@ -14,6 +14,7 @@ #include #include +#include "drv_dma.h" #ifdef __cplusplus extern "C" { diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.c new file mode 100644 index 00000000000..498375417f6 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-04-13 wdfk-prog Add STM32 DMA common helpers + */ + +/** + * @file drv_dma.c + * @brief STM32 DMA common helper layer for peripheral drivers. + */ + +#include "drv_dma.h" + +// #define DRV_DEBUG +#define LOG_TAG "drv.dma" +#include + +#if defined(STM32_DMA_USES_REQUEST) +/** + * @brief Enable the DMAMUX clock when the current STM32 DMA path needs it. + */ +static void stm32_dma_enable_dmamux_clock(void) +{ +#if defined(DMAMUX1) && defined(__HAL_RCC_DMAMUX1_CLK_ENABLE) + __HAL_RCC_DMAMUX1_CLK_ENABLE(); +#elif defined(DMAMUX) && defined(__HAL_RCC_DMAMUX_CLK_ENABLE) + __HAL_RCC_DMAMUX_CLK_ENABLE(); +#endif /* defined(DMAMUX1) && defined(__HAL_RCC_DMAMUX1_CLK_ENABLE) */ +} +#endif /* defined(STM32_DMA_USES_REQUEST) */ + +/** + * @brief Enable the clock of one DMA controller and wait for the write to complete. + * @param dma_rcc RCC enable bit of the DMA controller. + */ +static void stm32_dma_enable_clock(rt_uint32_t dma_rcc) +{ + rt_uint32_t tmpreg = 0x00U; + +#if defined(STM32_DMA_USES_RCC_AHBENR) + SET_BIT(RCC->AHBENR, dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, dma_rcc); +#elif defined(STM32_DMA_USES_RCC_MP_AHB2ENSETR) + SET_BIT(RCC->MP_AHB2ENSETR, dma_rcc); + tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_rcc); +#elif defined(STM32_DMA_USES_RCC_AHB1ENR) + SET_BIT(RCC->AHB1ENR, dma_rcc); + tmpreg = READ_BIT(RCC->AHB1ENR, dma_rcc); +#endif /* defined(STM32_DMA_USES_RCC_AHBENR) || defined(STM32_DMA_USES_RCC_MP_AHB2ENSETR) || defined(STM32_DMA_USES_RCC_AHB1ENR) */ + +#if defined(STM32_DMA_USES_REQUEST) + stm32_dma_enable_dmamux_clock(); +#endif /* defined(STM32_DMA_USES_REQUEST) */ + + UNUSED(tmpreg); +} + +/** + * @brief Copy one static DMA descriptor into one HAL DMA handle. + * @param dma_handle DMA handle to update. + * @param dma_config Static DMA endpoint description. + */ +static void stm32_dma_apply_config(DMA_HandleTypeDef *dma_handle, + const struct stm32_dma_config *dma_config) +{ + dma_handle->Instance = dma_config->Instance; +#if defined(STM32_DMA_USES_CHANNEL) + dma_handle->Init.Channel = dma_config->channel; +#endif /* defined(STM32_DMA_USES_CHANNEL) */ +#if defined(STM32_DMA_USES_REQUEST) + dma_handle->Init.Request = dma_config->request; +#endif /* defined(STM32_DMA_USES_REQUEST) */ + dma_handle->Init.Direction = dma_config->direction; + dma_handle->Init.PeriphInc = dma_config->periph_inc; + dma_handle->Init.MemInc = dma_config->mem_inc; + dma_handle->Init.PeriphDataAlignment = dma_config->periph_data_alignment; + dma_handle->Init.MemDataAlignment = dma_config->mem_data_alignment; + dma_handle->Init.Mode = dma_config->mode; + dma_handle->Init.Priority = dma_config->priority; +#if defined(STM32_DMA_SUPPORTS_FIFO) + dma_handle->Init.FIFOMode = dma_config->fifo_mode; + dma_handle->Init.FIFOThreshold = dma_config->fifo_threshold; + dma_handle->Init.MemBurst = dma_config->mem_burst; + dma_handle->Init.PeriphBurst = dma_config->periph_burst; +#endif /* defined(STM32_DMA_SUPPORTS_FIFO) */ +} + +/** + * @brief Enable one DMA controller, apply the static descriptor and initialize HAL state. + * @param dma_handle DMA handle owned by one peripheral driver. + * @param dma_config Board-level DMA endpoint description. + * @retval RT_EOK Initialization succeeded. + * @retval -RT_ERROR HAL initialization failed. + */ +rt_err_t stm32_dma_init(DMA_HandleTypeDef *dma_handle, + const struct stm32_dma_config *dma_config) +{ + RT_ASSERT(dma_handle != RT_NULL); + RT_ASSERT(dma_config != RT_NULL); + + stm32_dma_enable_clock(dma_config->dma_rcc); + stm32_dma_apply_config(dma_handle, dma_config); + + LOG_D("dma init, dma=%p, irq=%d", dma_handle->Instance, dma_config->dma_irq); + + if (HAL_DMA_DeInit(dma_handle) != HAL_OK) + { + LOG_E("dma deinit failed, dma=%p, irq=%d", dma_handle->Instance, dma_config->dma_irq); + return -RT_ERROR; + } + + if (HAL_DMA_Init(dma_handle) != HAL_OK) + { + LOG_E("dma init failed, dma=%p, irq=%d", dma_handle->Instance, dma_config->dma_irq); + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief Initialize one DMA handle, attach it to the parent HAL handle and enable the DMA IRQ. + * @param dma_handle DMA handle owned by one peripheral driver. + * @param parent_handle Parent HAL handle, such as UART_HandleTypeDef or SPI_HandleTypeDef. + * @param dma_slot Address of the parent handle DMA slot, such as &huart->hdmarx. + * @param dma_config Board-level DMA endpoint description. + * @retval RT_EOK Initialization succeeded. + * @retval -RT_ERROR HAL initialization failed. + */ +rt_err_t stm32_dma_setup(DMA_HandleTypeDef *dma_handle, + void *parent_handle, + DMA_HandleTypeDef **dma_slot, + const struct stm32_dma_config *dma_config) +{ + rt_err_t result; + + result = stm32_dma_init(dma_handle, dma_config); + if (result != RT_EOK) + { + return result; + } + + if ((parent_handle != RT_NULL) && (dma_slot != RT_NULL)) + { + *dma_slot = dma_handle; + dma_handle->Parent = parent_handle; + } + + HAL_NVIC_SetPriority(dma_config->dma_irq, dma_config->preempt_priority, dma_config->sub_priority); + HAL_NVIC_EnableIRQ(dma_config->dma_irq); + + LOG_D("dma setup, dma=%p, irq=%d", dma_handle->Instance, dma_config->dma_irq); + + return RT_EOK; +} + +/** + * @brief Disable one DMA IRQ, optionally abort the current transfer and de-initialize HAL state. + * @param dma_handle DMA handle owned by one peripheral driver. + * @param dma_config Board-level DMA endpoint description. + * @param abort_first RT_TRUE aborts the ongoing transfer before HAL_DMA_DeInit(). + * @retval RT_EOK De-initialization succeeded. + * @retval -RT_ERROR HAL de-initialization failed. + */ +rt_err_t stm32_dma_deinit(DMA_HandleTypeDef *dma_handle, + const struct stm32_dma_config *dma_config, + rt_bool_t abort_first) +{ + RT_ASSERT(dma_handle != RT_NULL); + RT_ASSERT(dma_config != RT_NULL); + + HAL_NVIC_DisableIRQ(dma_config->dma_irq); + + LOG_D("dma deinit, dma=%p, irq=%d", dma_handle->Instance, dma_config->dma_irq); + + if (abort_first) + { + if (HAL_DMA_Abort(dma_handle) != HAL_OK) + { + LOG_W("dma abort failed, continue deinit, dma=%p, irq=%d", dma_handle->Instance, dma_config->dma_irq); + } + } + + if (HAL_DMA_DeInit(dma_handle) != HAL_OK) + { + LOG_E("dma deinit failed, dma=%p, irq=%d", dma_handle->Instance, dma_config->dma_irq); + return -RT_ERROR; + } + + return RT_EOK; +} diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h index 1fc6ffee442..6834c532513 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2026, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,6 +7,12 @@ * Date Author Notes * 2018-11-10 SummerGift first version * 2020-10-14 PeakRacing Porting for stm32wbxx + * 2026-04-13 wdfk-prog Add STM32 DMA common helpers + */ + +/** + * @file drv_dma.h + * @brief STM32 DMA common descriptors and helper interfaces. */ #ifndef __DRV_DMA_H_ @@ -19,33 +25,240 @@ extern "C" { #endif -#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5)\ +/** + * @brief DMA capability classification for STM32 series supported by this BSP. + */ +#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5) \ || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) \ - || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \ - || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) + || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) \ + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32L1) #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\ +#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \ || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) #define DMA_INSTANCE_TYPE DMA_Stream_TypeDef -#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */ +#endif /* defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5) +|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) +|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) +|| defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32L1)*/ -struct dma_config { - DMA_INSTANCE_TYPE *Instance; - rt_uint32_t dma_rcc; - IRQn_Type dma_irq; +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F3) +#define STM32_DMA_USES_CHANNEL +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F3) */ -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)|| defined(SOC_SERIES_STM32F3) - rt_uint32_t channel; -#endif +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) \ + || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) \ + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) +#define STM32_DMA_USES_REQUEST +#endif /* defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) +|| defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) +|| defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) */ -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\ - || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5) - rt_uint32_t request; -#endif +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \ + || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) +#define STM32_DMA_SUPPORTS_FIFO +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) */ + +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \ + || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) +#define STM32_DMA_USES_RCC_AHBENR +#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) */ + +#if defined(SOC_SERIES_STM32MP1) +#define STM32_DMA_USES_RCC_MP_AHB2ENSETR +#endif /* defined(SOC_SERIES_STM32MP1) */ + +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \ + || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) \ + || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5) \ + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) +#define STM32_DMA_USES_RCC_AHB1ENR +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) +|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5) +|| defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) */ + +#ifndef STM32_DMA_DEFAULT_PRIORITY +#define STM32_DMA_DEFAULT_PRIORITY DMA_PRIORITY_LOW +#endif /* STM32_DMA_DEFAULT_PRIORITY */ + +#ifndef STM32_DMA_DEFAULT_PREEMPT_PRIORITY +#define STM32_DMA_DEFAULT_PREEMPT_PRIORITY 0 +#endif /* STM32_DMA_DEFAULT_PREEMPT_PRIORITY */ + +#ifndef STM32_DMA_DEFAULT_SUB_PRIORITY +#define STM32_DMA_DEFAULT_SUB_PRIORITY 0 +#endif /* STM32_DMA_DEFAULT_SUB_PRIORITY */ + +/** + * @brief Static DMA endpoint description used by board-level config headers. + * + * This descriptor stores one complete DMA endpoint configuration so peripheral + * drivers can initialize DMA directly from the board-level config tables. + */ +struct stm32_dma_config +{ + DMA_INSTANCE_TYPE *Instance; /**< DMA controller instance pointer. */ + rt_uint32_t dma_rcc; /**< RCC enable bit for the DMA controller. */ + IRQn_Type dma_irq; /**< DMA global IRQ number. */ + rt_uint32_t priority; /**< DMA transfer priority. */ + rt_uint8_t preempt_priority; /**< NVIC preempt priority for the DMA IRQ. */ + rt_uint8_t sub_priority; /**< NVIC sub priority for the DMA IRQ. */ + +#ifdef STM32_DMA_USES_CHANNEL + rt_uint32_t channel; /**< DMA channel selector for stream-based DMA. */ +#endif /* STM32_DMA_USES_CHANNEL */ + +#ifdef STM32_DMA_USES_REQUEST + rt_uint32_t request; /**< DMA request selector for DMAMUX/request-based DMA. */ +#endif /* STM32_DMA_USES_REQUEST */ + + rt_uint32_t direction; /**< DMA transfer direction. */ + rt_uint32_t periph_inc; /**< Peripheral address increment mode. */ + rt_uint32_t mem_inc; /**< Memory address increment mode. */ + rt_uint32_t periph_data_alignment; /**< Peripheral data alignment. */ + rt_uint32_t mem_data_alignment; /**< Memory data alignment. */ + rt_uint32_t mode; /**< DMA transfer mode. */ + +#if defined(STM32_DMA_SUPPORTS_FIFO) + rt_uint32_t fifo_mode; /**< FIFO enable state. */ + rt_uint32_t fifo_threshold; /**< FIFO threshold selection. */ + rt_uint32_t mem_burst; /**< Memory burst transfer mode. */ + rt_uint32_t periph_burst; /**< Peripheral burst transfer mode. */ +#endif /* defined(STM32_DMA_SUPPORTS_FIFO) */ }; +/** + * @brief Optional selector fields kept in the descriptor for board-level readability. + */ +#if defined(STM32_DMA_USES_CHANNEL) +#define STM32_DMA_CHANNEL_FIELD(_channel) .channel = (_channel), +#else +#define STM32_DMA_CHANNEL_FIELD(_channel) +#endif /* defined(STM32_DMA_USES_CHANNEL) */ + +#if defined(STM32_DMA_USES_REQUEST) +#define STM32_DMA_REQUEST_FIELD(_request) .request = (_request), +#else +#define STM32_DMA_REQUEST_FIELD(_request) +#endif /* defined(STM32_DMA_USES_REQUEST) */ + +#if defined(STM32_DMA_SUPPORTS_FIFO) +#define STM32_DMA_FIFO_FIELD_DEFAULTS \ + .fifo_mode = DMA_FIFOMODE_DISABLE, \ + .fifo_threshold = DMA_FIFO_THRESHOLD_FULL, \ + .mem_burst = DMA_MBURST_INC4, \ + .periph_burst = DMA_PBURST_INC4, + +#define STM32_DMA_FIFO_FIELD_VALUES(_fifo_mode, _fifo_threshold, _mem_burst, _periph_burst) \ + .fifo_mode = (_fifo_mode), \ + .fifo_threshold = (_fifo_threshold), \ + .mem_burst = (_mem_burst), \ + .periph_burst = (_periph_burst), +#else +#define STM32_DMA_FIFO_FIELD_DEFAULTS +#define STM32_DMA_FIFO_FIELD_VALUES(_fifo_mode, _fifo_threshold, _mem_burst, _periph_burst) +#endif /* defined(STM32_DMA_SUPPORTS_FIFO) */ + +/** + * @brief Generic descriptor initializer with explicit DMA direction and data layout. + */ +#define STM32_DMA_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _channel, _request, _priority, _preempt_priority, _sub_priority, _direction, _periph_inc, _mem_inc, _periph_data_alignment, _mem_data_alignment, _mode) \ + { \ + .Instance = (_instance), \ + .dma_rcc = (_dma_rcc), \ + .dma_irq = (_dma_irq), \ + .priority = (_priority), \ + .preempt_priority = (_preempt_priority), \ + .sub_priority = (_sub_priority), \ + STM32_DMA_CHANNEL_FIELD(_channel) \ + STM32_DMA_REQUEST_FIELD(_request) \ + .direction = (_direction), \ + .periph_inc = (_periph_inc), \ + .mem_inc = (_mem_inc), \ + .periph_data_alignment = (_periph_data_alignment), \ + .mem_data_alignment = (_mem_data_alignment), \ + .mode = (_mode), \ + STM32_DMA_FIFO_FIELD_DEFAULTS \ + } + +/** + * @brief Generic descriptor initializer for controllers that expose FIFO and burst fields. + */ +#define STM32_DMA_CONFIG_INIT_FIFO_EX(_instance, _dma_rcc, _dma_irq, _channel, _request, _priority, _preempt_priority, _sub_priority, _direction, _periph_inc, _mem_inc, _periph_data_alignment, _mem_data_alignment, _mode, _fifo_mode, _fifo_threshold, _mem_burst, _periph_burst) \ + { \ + .Instance = (_instance), \ + .dma_rcc = (_dma_rcc), \ + .dma_irq = (_dma_irq), \ + .priority = (_priority), \ + .preempt_priority = (_preempt_priority), \ + .sub_priority = (_sub_priority), \ + STM32_DMA_CHANNEL_FIELD(_channel) \ + STM32_DMA_REQUEST_FIELD(_request) \ + .direction = (_direction), \ + .periph_inc = (_periph_inc), \ + .mem_inc = (_mem_inc), \ + .periph_data_alignment = (_periph_data_alignment), \ + .mem_data_alignment = (_mem_data_alignment), \ + .mode = (_mode), \ + STM32_DMA_FIFO_FIELD_VALUES(_fifo_mode, _fifo_threshold, _mem_burst, _periph_burst) \ + } + +/** + * @brief Common byte/word transfer descriptor helpers used by board-level config headers. + */ +#define STM32_DMA_RX_BYTE_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _channel, _request, _priority, _preempt_priority, _sub_priority) \ + STM32_DMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_channel), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_PERIPH_TO_MEMORY, DMA_PINC_DISABLE, DMA_MINC_ENABLE, DMA_PDATAALIGN_BYTE, DMA_MDATAALIGN_BYTE, DMA_NORMAL) + +#define STM32_DMA_TX_BYTE_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _channel, _request, _priority, _preempt_priority, _sub_priority) \ + STM32_DMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_channel), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_MEMORY_TO_PERIPH, DMA_PINC_DISABLE, DMA_MINC_ENABLE, DMA_PDATAALIGN_BYTE, DMA_MDATAALIGN_BYTE, DMA_NORMAL) + +#define STM32_DMA_RX_BYTE_CIRCULAR_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _channel, _request, _priority, _preempt_priority, _sub_priority) \ + STM32_DMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_channel), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_PERIPH_TO_MEMORY, DMA_PINC_DISABLE, DMA_MINC_ENABLE, DMA_PDATAALIGN_BYTE, DMA_MDATAALIGN_BYTE, DMA_CIRCULAR) + +#define STM32_DMA_RX_WORD_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _channel, _request, _priority, _preempt_priority, _sub_priority) \ + STM32_DMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_channel), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_PERIPH_TO_MEMORY, DMA_PINC_DISABLE, DMA_MINC_ENABLE, DMA_PDATAALIGN_WORD, DMA_MDATAALIGN_WORD, DMA_NORMAL) + +#define STM32_DMA_TX_WORD_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _channel, _request, _priority, _preempt_priority, _sub_priority) \ + STM32_DMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_channel), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_MEMORY_TO_PERIPH, DMA_PINC_DISABLE, DMA_MINC_ENABLE, DMA_PDATAALIGN_WORD, DMA_MDATAALIGN_WORD, DMA_NORMAL) + +/** + * @brief Apply one static DMA descriptor and initialize the HAL DMA handle. + * @param dma_handle DMA handle to initialize. + * @param dma_config Static DMA endpoint description. + * @retval RT_EOK Success. + * @retval -RT_ERROR HAL initialization failed. + */ +rt_err_t stm32_dma_init(DMA_HandleTypeDef *dma_handle, + const struct stm32_dma_config *dma_config); + +/** + * @brief Initialize one DMA handle, link it to the parent peripheral and enable its IRQ. + * @param dma_handle DMA handle to initialize. + * @param parent_handle Parent peripheral HAL handle. + * @param dma_slot Parent peripheral DMA slot address, such as &huart->hdmarx. + * @param dma_config Static DMA endpoint description. + * @retval RT_EOK Success. + * @retval -RT_ERROR HAL initialization failed. + */ +rt_err_t stm32_dma_setup(DMA_HandleTypeDef *dma_handle, + void *parent_handle, + DMA_HandleTypeDef **dma_slot, + const struct stm32_dma_config *dma_config); + +/** + * @brief Abort and de-initialize one DMA handle. + * @param dma_handle DMA handle to de-initialize. + * @param dma_config Static DMA endpoint description. + * @param abort_first RT_TRUE aborts the DMA transfer before de-initialization. + * @retval RT_EOK Success. + * @retval -RT_ERROR HAL abort or de-initialization failed. + */ +rt_err_t stm32_dma_deinit(DMA_HandleTypeDef *dma_handle, + const struct stm32_dma_config *dma_config, + rt_bool_t abort_first); + #ifdef __cplusplus } #endif -#endif /*__DRV_DMA_H_ */ +#endif /* __DRV_DMA_H_ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c index 2c3778199fc..568aeab8887 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c @@ -79,6 +79,29 @@ static void stm32_i2c_apply_default_config(struct stm32_i2c_config *cfg) } } +#if defined(BSP_I2C_RX_USING_DMA) || defined(BSP_I2C_TX_USING_DMA) +static void stm32_i2c_dma_rollback(struct stm32_i2c *i2c_drv, rt_uint16_t dma_flags) +{ +#if defined(BSP_I2C_RX_USING_DMA) + if (dma_flags & RT_DEVICE_FLAG_DMA_RX) + { + (void)stm32_dma_deinit(&i2c_drv->dma.handle_rx, i2c_drv->config->dma_rx, RT_FALSE); + i2c_drv->dma.handle_rx.Parent = RT_NULL; + i2c_drv->handle.hdmarx = RT_NULL; + } +#endif /* defined(BSP_I2C_RX_USING_DMA) */ + +#if defined(BSP_I2C_TX_USING_DMA) + if (dma_flags & RT_DEVICE_FLAG_DMA_TX) + { + (void)stm32_dma_deinit(&i2c_drv->dma.handle_tx, i2c_drv->config->dma_tx, RT_FALSE); + i2c_drv->dma.handle_tx.Parent = RT_NULL; + i2c_drv->handle.hdmatx = RT_NULL; + } +#endif /* defined(BSP_I2C_TX_USING_DMA) */ +} +#endif /* defined(BSP_I2C_RX_USING_DMA) || defined(BSP_I2C_TX_USING_DMA) */ + static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) { RT_ASSERT(i2c_drv != RT_NULL); @@ -129,25 +152,27 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) /* I2C2 DMA Init */ if (i2c_drv->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) { - HAL_DMA_Init(&i2c_drv->dma.handle_rx); - - __HAL_LINKDMA(&i2c_drv->handle, hdmarx, i2c_drv->dma.handle_rx); - - /* NVIC configuration for DMA transfer complete interrupt */ - HAL_NVIC_SetPriority(i2c_drv->config->dma_rx->dma_irq, 0, 0); - HAL_NVIC_EnableIRQ(i2c_drv->config->dma_rx->dma_irq); + if (stm32_dma_setup(&i2c_drv->dma.handle_rx, + &i2c_drv->handle, + &i2c_drv->handle.hdmarx, + i2c_drv->config->dma_rx) != RT_EOK) + { + stm32_i2c_dma_rollback(i2c_drv, RT_DEVICE_FLAG_DMA_RX); + return -RT_EFAULT; + } } #endif /* defined(BSP_I2C_RX_USING_DMA) */ #if defined(BSP_I2C_TX_USING_DMA) if (i2c_drv->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) { - HAL_DMA_Init(&i2c_drv->dma.handle_tx); - - __HAL_LINKDMA(&i2c_drv->handle, hdmatx, i2c_drv->dma.handle_tx); - - /* NVIC configuration for DMA transfer complete interrupt */ - HAL_NVIC_SetPriority(i2c_drv->config->dma_tx->dma_irq, 1, 0); - HAL_NVIC_EnableIRQ(i2c_drv->config->dma_tx->dma_irq); + if (stm32_dma_setup(&i2c_drv->dma.handle_tx, + &i2c_drv->handle, + &i2c_drv->handle.hdmatx, + i2c_drv->config->dma_tx) != RT_EOK) + { + stm32_i2c_dma_rollback(i2c_drv, RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX); + return -RT_EFAULT; + } } #endif /* defined(BSP_I2C_TX_USING_DMA) */ #if defined(BSP_I2C_USING_IRQ) @@ -533,94 +558,6 @@ int RT_hw_i2c_bus_init(void) i2c_objs[i].i2c_bus.config.max_hz = i2c_config[i].timing; i2c_objs[i].i2c_bus.config.usage_freq = i2c_config[i].timing; #endif - -#ifdef BSP_I2C_USING_DMA - if ((i2c_objs[i].i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX)) - { - i2c_objs[i].dma.handle_rx.Instance = i2c_config[i].dma_rx->Instance; -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - i2c_objs[i].dma.handle_rx.Init.Channel = i2c_config[i].dma_rx->channel; -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) - i2c_objs[i].dma.handle_rx.Init.Request = i2c_config[i].dma_rx->request; -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ -#ifndef SOC_SERIES_STM32U5 - i2c_objs[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - i2c_objs[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE; - i2c_objs[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE; - i2c_objs[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - i2c_objs[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - i2c_objs[i].dma.handle_rx.Init.Mode = DMA_NORMAL; - i2c_objs[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_LOW; -#endif -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) - i2c_objs[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - i2c_objs[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - i2c_objs[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4; - i2c_objs[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4; -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) */ - { - rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, i2c_config[i].dma_rx->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, i2c_config[i].dma_rx->dma_rcc); -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) - SET_BIT(RCC->AHB1ENR, i2c_config[i].dma_rx->dma_rcc); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1ENR, i2c_config[i].dma_rx->dma_rcc); -#elif defined(SOC_SERIES_STM32MP1) - __HAL_RCC_DMAMUX_CLK_ENABLE(); - SET_BIT(RCC->MP_AHB2ENSETR, i2c_config[i].dma_rx->dma_rcc); - tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, i2c_config[i].dma_rx->dma_rcc); -#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) */ - UNUSED(tmpreg); /* To avoid compiler warnings */ - } - } - - if (i2c_objs[i].i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) - { - i2c_objs[i].dma.handle_tx.Instance = i2c_config[i].dma_tx->Instance; -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - i2c_objs[i].dma.handle_tx.Init.Channel = i2c_config[i].dma_tx->channel; -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) - i2c_objs[i].dma.handle_tx.Init.Request = i2c_config[i].dma_tx->request; -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ -#ifndef SOC_SERIES_STM32U5 - i2c_objs[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; - i2c_objs[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; - i2c_objs[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; - i2c_objs[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - i2c_objs[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - i2c_objs[i].dma.handle_tx.Init.Mode = DMA_NORMAL; - i2c_objs[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW; -#endif /* SOC_SERIES_STM32U5 */ -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) - - i2c_objs[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - i2c_objs[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - i2c_objs[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; - i2c_objs[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) */ - { - rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, i2c_config[i].dma_tx->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, i2c_config[i].dma_tx->dma_rcc); -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) - SET_BIT(RCC->AHB1ENR, i2c_config[i].dma_tx->dma_rcc); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1ENR, i2c_config[i].dma_tx->dma_rcc); -#elif defined(SOC_SERIES_STM32MP1) - __HAL_RCC_DMAMUX_CLK_ENABLE(); - SET_BIT(RCC->MP_AHB2ENSETR, i2c_config[i].dma_tx->dma_rcc); - tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, i2c_config[i].dma_tx->dma_rcc); -#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) */ - UNUSED(tmpreg); /* To avoid compiler warnings */ - } - } - -#endif /* BSP_I2C_USING_DMA */ #if defined(BSP_I2C_USING_IRQ) rt_completion_init(&i2c_objs[i].completion); #endif /* defined(BSP_I2C_USING_IRQ) */ @@ -652,7 +589,7 @@ static void stm32_get_info(void) i2c_objs[I2C1_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_INT_TX; #elif defined(BSP_I2C1_TX_USING_DMA) i2c_objs[I2C1_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config I2C1_dma_tx = I2C1_TX_DMA_CONFIG; + static const struct stm32_dma_config I2C1_dma_tx = I2C1_TX_DMA_CONFIG; i2c_config[I2C1_INDEX].dma_tx = &I2C1_dma_tx; #endif /* defined (BSP_I2C1_TX_USING_INT) */ @@ -660,7 +597,7 @@ static void stm32_get_info(void) i2c_objs[I2C1_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_INT_RX; #elif defined(BSP_I2C1_RX_USING_DMA) i2c_objs[I2C1_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config I2C1_dma_rx = I2C1_RX_DMA_CONFIG; + static const struct stm32_dma_config I2C1_dma_rx = I2C1_RX_DMA_CONFIG; i2c_config[I2C1_INDEX].dma_rx = &I2C1_dma_rx; #endif /* defined (BSP_I2C1_RX_USING_INT) */ @@ -673,7 +610,7 @@ static void stm32_get_info(void) i2c_objs[I2C2_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_INT_TX; #elif defined(BSP_I2C2_TX_USING_DMA) i2c_objs[I2C2_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config I2C2_dma_tx = I2C2_TX_DMA_CONFIG; + static const struct stm32_dma_config I2C2_dma_tx = I2C2_TX_DMA_CONFIG; i2c_config[I2C2_INDEX].dma_tx = &I2C2_dma_tx; #endif /* defined (BSP_I2C2_TX_USING_INT) */ @@ -681,7 +618,7 @@ static void stm32_get_info(void) i2c_objs[I2C2_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_INT_RX; #elif defined(BSP_I2C2_RX_USING_DMA) i2c_objs[I2C2_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config I2C2_dma_rx = I2C2_RX_DMA_CONFIG; + static const struct stm32_dma_config I2C2_dma_rx = I2C2_RX_DMA_CONFIG; i2c_config[I2C2_INDEX].dma_rx = &I2C2_dma_rx; #endif /* defined (BSP_I2C2_RX_USING_INT) */ @@ -694,7 +631,7 @@ static void stm32_get_info(void) i2c_objs[I2C3_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_INT_TX; #elif defined(BSP_I2C3_TX_USING_DMA) i2c_objs[I2C3_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config I2C3_dma_tx = I2C3_TX_DMA_CONFIG; + static const struct stm32_dma_config I2C3_dma_tx = I2C3_TX_DMA_CONFIG; i2c_config[I2C3_INDEX].dma_tx = &I2C3_dma_tx; #endif /* defined (BSP_I2C3_TX_USING_INT) */ @@ -702,7 +639,7 @@ static void stm32_get_info(void) i2c_objs[I2C3_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_INT_RX; #elif defined(BSP_I2C3_RX_USING_DMA) i2c_objs[I2C3_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config I2C3_dma_rx = I2C3_RX_DMA_CONFIG; + static const struct stm32_dma_config I2C3_dma_rx = I2C3_RX_DMA_CONFIG; i2c_config[I2C3_INDEX].dma_rx = &I2C3_dma_rx; #endif /* defined (BSP_I2C3_RX_USING_INT) */ @@ -715,7 +652,7 @@ static void stm32_get_info(void) i2c_objs[I2C4_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_INT_TX; #elif defined(BSP_I2C4_TX_USING_DMA) i2c_objs[I2C4_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config I2C4_dma_tx = I2C4_TX_DMA_CONFIG; + static const struct stm32_dma_config I2C4_dma_tx = I2C4_TX_DMA_CONFIG; i2c_config[I2C4_INDEX].dma_tx = &I2C4_dma_tx; #endif /* defined (BSP_I2C4_TX_USING_INT) */ @@ -723,7 +660,7 @@ static void stm32_get_info(void) i2c_objs[I2C4_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_INT_RX; #elif defined(BSP_I2C4_RX_USING_DMA) i2c_objs[I2C4_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config I2C4_dma_rx = I2C4_RX_DMA_CONFIG; + static const struct stm32_dma_config I2C4_dma_rx = I2C4_RX_DMA_CONFIG; i2c_config[I2C4_INDEX].dma_rx = &I2C4_dma_rx; #endif /* defined (BSP_I2C4_RX_USING_INT) */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h index 2a2869511ca..adfec0a6974 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h @@ -136,10 +136,10 @@ struct stm32_i2c_config IRQn_Type evirq_type; IRQn_Type erirq_type; #ifdef BSP_I2C_RX_USING_DMA - struct dma_config *dma_rx; + const struct stm32_dma_config *dma_rx; #endif /* BSP_I2C_RX_USING_DMA */ #ifdef BSP_I2C_TX_USING_DMA - struct dma_config *dma_tx; + const struct stm32_dma_config *dma_tx; #endif /* BSP_I2C_TX_USING_DMA */ }; diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_qspi.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_qspi.c index 5be0be89c53..127d12d738e 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_qspi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_qspi.c @@ -11,6 +11,7 @@ #include "board.h" #include "drv_qspi.h" +#include "drv_dma.h" #include "drv_config.h" #ifdef RT_USING_QSPI @@ -32,6 +33,9 @@ struct stm32_qspi_bus struct rt_spi_bus _qspi_bus1; struct stm32_qspi_bus _stm32_qspi_bus; +#ifdef BSP_QSPI_USING_DMA +static const struct stm32_dma_config qspi_dma_config = QSPI_DMA_CONFIG; +#endif static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configuration *qspi_cfg) { @@ -92,29 +96,12 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu /* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */ HAL_NVIC_SetPriority(QSPI_IRQn, 0, 0); HAL_NVIC_EnableIRQ(QSPI_IRQn); - HAL_NVIC_SetPriority(QSPI_DMA_IRQ, 0, 0); - HAL_NVIC_EnableIRQ(QSPI_DMA_IRQ); - /* init QSPI DMA */ - if(QSPI_DMA_RCC == RCC_AHB1ENR_DMA1EN) - { - __HAL_RCC_DMA1_CLK_ENABLE(); - } - else + if (stm32_dma_setup(&qspi_bus->hdma_quadspi, &qspi_bus->QSPI_Handler, &qspi_bus->QSPI_Handler.hdma, &qspi_dma_config) != RT_EOK) { - __HAL_RCC_DMA2_CLK_ENABLE(); + LOG_E("qspi dma init failed"); + return -RT_ERROR; } - - HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma); - DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG; - qspi_bus->hdma_quadspi = hdma_quadspi_config; - - if (HAL_DMA_Init(&qspi_bus->hdma_quadspi) != HAL_OK) - { - LOG_E("qspi dma init failed (%d)!", result); - } - - __HAL_LINKDMA(&qspi_bus->QSPI_Handler, hdma, qspi_bus->hdma_quadspi); #endif /* BSP_QSPI_USING_DMA */ return result; diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdio.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdio.c index 8132ee0ac85..45f82636ad4 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdio.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdio.c @@ -687,64 +687,23 @@ struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des) */ void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize) { -#if defined(SOC_SERIES_STM32F1) - static uint32_t size = 0; - size += BufferSize * 4; sdio_obj.cfg = &sdio_config; - sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; - sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; - sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; - sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; - sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; - sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; - /* DMA_PFCTRL */ - HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); - HAL_DMA_Init(&sdio_obj.dma.handle_tx); - - HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); - -#elif defined(SOC_SERIES_STM32L4) - static uint32_t size = 0; - size += BufferSize * 4; - sdio_obj.cfg = &sdio_config; - sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; - sdio_obj.dma.handle_tx.Init.Request = sdio_config.dma_tx.request; - sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; - sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; - sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; - sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; - sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - sdio_obj.dma.handle_tx.Init.Mode = DMA_NORMAL; - sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; - - HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); - HAL_DMA_Init(&sdio_obj.dma.handle_tx); - - HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); -#else - static uint32_t size = 0; - size += BufferSize * 4; - sdio_obj.cfg = &sdio_config; - sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; - sdio_obj.dma.handle_tx.Init.Channel = sdio_config.dma_tx.channel; - sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; - sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; - sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; - sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; - sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - sdio_obj.dma.handle_tx.Init.Mode = DMA_PFCTRL; - sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; - sdio_obj.dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - sdio_obj.dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - sdio_obj.dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; - sdio_obj.dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; - /* DMA_PFCTRL */ - HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); - HAL_DMA_Init(&sdio_obj.dma.handle_tx); - - HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); -#endif + + if (stm32_dma_init(&sdio_obj.dma.handle_tx, &sdio_config.dma_tx) != RT_EOK) + { + LOG_E("sdio dma tx init failed"); + return; + } + + if (HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize) != HAL_OK) + { + LOG_E("sdio dma tx start failed"); + if (stm32_dma_deinit(&sdio_obj.dma.handle_tx, &sdio_config.dma_tx, RT_FALSE) != RT_EOK) + { + LOG_E("sdio dma tx rollback failed"); + } + return; + } } /** @@ -755,58 +714,23 @@ void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize) */ void SD_LowLevel_DMA_RxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize) { -#if defined(SOC_SERIES_STM32F1) - sdio_obj.cfg = &sdio_config; - sdio_obj.dma.handle_rx.Instance = sdio_config.dma_tx.Instance; - sdio_obj.dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - sdio_obj.dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - sdio_obj.dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE; - sdio_obj.dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; - sdio_obj.dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE; - sdio_obj.dma.handle_rx.Init.Priority = DMA_PRIORITY_MEDIUM; - - HAL_DMA_DeInit(&sdio_obj.dma.handle_rx); - HAL_DMA_Init(&sdio_obj.dma.handle_rx); - - HAL_DMA_Start(&sdio_obj.dma.handle_rx, (uint32_t)src, (uint32_t)dst, BufferSize); -#elif defined(SOC_SERIES_STM32L4) sdio_obj.cfg = &sdio_config; - sdio_obj.dma.handle_rx.Instance = sdio_config.dma_tx.Instance; - sdio_obj.dma.handle_rx.Init.Request = sdio_config.dma_tx.request; - sdio_obj.dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - sdio_obj.dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE; - sdio_obj.dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE; - sdio_obj.dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; - sdio_obj.dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - sdio_obj.dma.handle_rx.Init.Mode = DMA_NORMAL; - sdio_obj.dma.handle_rx.Init.Priority = DMA_PRIORITY_LOW; - - HAL_DMA_DeInit(&sdio_obj.dma.handle_rx); - HAL_DMA_Init(&sdio_obj.dma.handle_rx); - - HAL_DMA_Start(&sdio_obj.dma.handle_rx, (uint32_t)src, (uint32_t)dst, BufferSize); -#else - sdio_obj.cfg = &sdio_config; - sdio_obj.dma.handle_rx.Instance = sdio_config.dma_tx.Instance; - sdio_obj.dma.handle_rx.Init.Channel = sdio_config.dma_tx.channel; - sdio_obj.dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - sdio_obj.dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE; - sdio_obj.dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE; - sdio_obj.dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; - sdio_obj.dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - sdio_obj.dma.handle_rx.Init.Mode = DMA_PFCTRL; - sdio_obj.dma.handle_rx.Init.Priority = DMA_PRIORITY_MEDIUM; - sdio_obj.dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - sdio_obj.dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - sdio_obj.dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4; - sdio_obj.dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4; - - HAL_DMA_DeInit(&sdio_obj.dma.handle_rx); - HAL_DMA_Init(&sdio_obj.dma.handle_rx); - - HAL_DMA_Start(&sdio_obj.dma.handle_rx, (uint32_t)src, (uint32_t)dst, BufferSize); -#endif + if (stm32_dma_init(&sdio_obj.dma.handle_rx, &sdio_config.dma_rx) != RT_EOK) + { + LOG_E("sdio dma rx init failed"); + return; + } + + if (HAL_DMA_Start(&sdio_obj.dma.handle_rx, (uint32_t)src, (uint32_t)dst, BufferSize) != HAL_OK) + { + LOG_E("sdio dma rx start failed"); + if (stm32_dma_deinit(&sdio_obj.dma.handle_rx, &sdio_config.dma_rx, RT_FALSE) != RT_EOK) + { + LOG_E("sdio dma rx rollback failed"); + } + return; + } } /** @@ -847,19 +771,6 @@ int rt_hw_sdio_init(void) struct stm32_sdio_des sdio_des; SD_HandleTypeDef hsd; hsd.Instance = SDCARD_INSTANCE; - { - rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_STM32F1) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc); -#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F2) - SET_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc); -#endif - UNUSED(tmpreg); /* To avoid compiler warnings */ - } HAL_NVIC_SetPriority(SDIO_IRQn, 2, 0); HAL_NVIC_EnableIRQ(SDIO_IRQn); HAL_SD_MspInit(&hsd); diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdio.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdio.h index e28fc6dc813..06ad351be28 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdio.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdio.h @@ -169,7 +169,7 @@ struct stm32_sdio_des struct stm32_sdio_config { SDCARD_INSTANCE_TYPE *Instance; - struct dma_config dma_rx, dma_tx; + struct stm32_dma_config dma_rx, dma_tx; }; /* stm32 sdio dirver class */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c index 40506460d3d..e9e1e5af90e 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c @@ -11,6 +11,7 @@ * 2020-01-15 whj4674672 Porting for stm32h7xx * 2020-06-18 thread-liu Porting for stm32mp1xx * 2020-10-14 PeakRacing Porting for stm32wbxx + * 2025-09-22 wdfk_prog Refactor DMA */ #include @@ -80,6 +81,23 @@ static struct stm32_spi_config spi_config[] = static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; +static void stm32_spi_dma_rollback(struct stm32_spi *spi_drv, rt_uint16_t dma_flags) +{ + if (dma_flags & SPI_USING_RX_DMA_FLAG) + { + (void)stm32_dma_deinit(&spi_drv->dma.handle_rx, spi_drv->config->dma_rx, RT_FALSE); + spi_drv->dma.handle_rx.Parent = RT_NULL; + spi_drv->handle.hdmarx = RT_NULL; + } + + if (dma_flags & SPI_USING_TX_DMA_FLAG) + { + (void)stm32_dma_deinit(&spi_drv->dma.handle_tx, spi_drv->config->dma_tx, RT_FALSE); + spi_drv->dma.handle_tx.Parent = RT_NULL; + spi_drv->handle.hdmatx = RT_NULL; + } +} + static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg) { RT_ASSERT(spi_drv != RT_NULL); @@ -254,24 +272,26 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur /* DMA configuration */ if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) { - HAL_DMA_Init(&spi_drv->dma.handle_rx); - - __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx); - - /* NVIC configuration for DMA transfer complete interrupt */ - HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0); - HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq); + if (stm32_dma_setup(&spi_drv->dma.handle_rx, + &spi_drv->handle, + &spi_drv->handle.hdmarx, + spi_drv->config->dma_rx) != RT_EOK) + { + stm32_spi_dma_rollback(spi_drv, SPI_USING_RX_DMA_FLAG); + return -RT_EIO; + } } if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) { - HAL_DMA_Init(&spi_drv->dma.handle_tx); - - __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx); - - /* NVIC configuration for DMA transfer complete interrupt */ - HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 1, 0); - HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq); + if (stm32_dma_setup(&spi_drv->dma.handle_tx, + &spi_drv->handle, + &spi_drv->handle.hdmatx, + spi_drv->config->dma_tx) != RT_EOK) + { + stm32_spi_dma_rollback(spi_drv, SPI_USING_RX_DMA_FLAG | SPI_USING_TX_DMA_FLAG); + return -RT_EIO; + } } if(spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG || spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) @@ -286,7 +306,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { - #define DMA_TRANS_MIN_LEN 10 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ +#define DMA_TRANS_MIN_LEN 10 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ HAL_StatusTypeDef state = HAL_OK; rt_size_t message_length, already_send_length; @@ -583,94 +603,6 @@ static int rt_hw_spi_bus_init(void) spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; spi_bus_obj[i].handle.Instance = spi_config[i].Instance; - if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG) - { - /* Configure the DMA handler for Transmission process */ - spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance; -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel; -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) - spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request; -#endif -#ifndef SOC_SERIES_STM32U5 - spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE; - spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE; - spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL; - spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH; -#endif -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) - spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4; - spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4; -#endif - - { - rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) - SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); -#elif defined(SOC_SERIES_STM32MP1) - __HAL_RCC_DMAMUX_CLK_ENABLE(); - SET_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_rx->dma_rcc); - tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_rx->dma_rcc); -#endif - UNUSED(tmpreg); /* To avoid compiler warnings */ - } - } - - if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG) - { - /* Configure the DMA handler for Transmission process */ - spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance; -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel; -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) - spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request; -#endif -#ifndef SOC_SERIES_STM32U5 - spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; - spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; - spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; - spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL; - spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW; -#endif -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) - spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; - spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; -#endif - - { - rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc); -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) - SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); -#elif defined(SOC_SERIES_STM32MP1) - __HAL_RCC_DMAMUX_CLK_ENABLE(); - SET_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_tx->dma_rcc); - tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_tx->dma_rcc); -#endif - UNUSED(tmpreg); /* To avoid compiler warnings */ - } - } - /* initialize completion object */ rt_completion_init(&spi_bus_obj[i].cpt); @@ -1037,67 +969,67 @@ static void stm32_get_dma_info(void) { #ifdef BSP_SPI1_RX_USING_DMA spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; - static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG; + static const struct stm32_dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG; spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx; #endif #ifdef BSP_SPI1_TX_USING_DMA spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; - static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG; + static const struct stm32_dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG; spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx; #endif #ifdef BSP_SPI2_RX_USING_DMA spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; - static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG; + static const struct stm32_dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG; spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx; #endif #ifdef BSP_SPI2_TX_USING_DMA spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; - static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG; + static const struct stm32_dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG; spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx; #endif #ifdef BSP_SPI3_RX_USING_DMA spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; - static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG; + static const struct stm32_dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG; spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx; #endif #ifdef BSP_SPI3_TX_USING_DMA spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; - static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG; + static const struct stm32_dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG; spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx; #endif #ifdef BSP_SPI4_RX_USING_DMA spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; - static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG; + static const struct stm32_dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG; spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx; #endif #ifdef BSP_SPI4_TX_USING_DMA spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; - static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG; + static const struct stm32_dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG; spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx; #endif #ifdef BSP_SPI5_RX_USING_DMA spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; - static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG; + static const struct stm32_dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG; spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx; #endif #ifdef BSP_SPI5_TX_USING_DMA spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; - static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG; + static const struct stm32_dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG; spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx; #endif #ifdef BSP_SPI6_RX_USING_DMA spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; - static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG; + static const struct stm32_dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG; spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx; #endif #ifdef BSP_SPI6_TX_USING_DMA spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; - static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG; + static const struct stm32_dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG; spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx; #endif } diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.h index 746809cad99..62506ba7dcc 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.h @@ -34,7 +34,7 @@ struct stm32_spi_config SPI_TypeDef *Instance; char *bus_name; IRQn_Type irq_type; - struct dma_config *dma_rx, *dma_tx; + const struct stm32_dma_config *dma_rx, *dma_tx; }; struct stm32_spi_device diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c index 86be2bc4190..fb5d38592d1 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c @@ -262,23 +262,16 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar /* disable DMA */ if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { - HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq); - if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK) + if (stm32_dma_deinit(&(uart->dma_rx.handle), uart->config->dma_rx, RT_TRUE) != RT_EOK) { - RT_ASSERT(0); - } - - if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK) - { - RT_ASSERT(0); + LOG_E("%s dma rx deinit failed", uart->config->name); } } else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { - HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq); - if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK) + if (stm32_dma_deinit(&(uart->dma_tx.handle), uart->config->dma_tx, RT_FALSE) != RT_EOK) { - RT_ASSERT(0); + LOG_E("%s dma tx deinit failed", uart->config->name); } } #endif @@ -312,7 +305,7 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar { if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK ) { - RT_ASSERT(0) + LOG_E("%s uart deinit failed", uart->config->name); } break; } @@ -927,12 +920,12 @@ static void stm32_uart_get_dma_config(void) uart_obj[UART1_INDEX].uart_dma_flag = 0; #ifdef BSP_UART1_RX_USING_DMA uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; + static const struct stm32_dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; #endif #ifdef BSP_UART1_TX_USING_DMA uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; + static const struct stm32_dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx; #endif #endif @@ -941,12 +934,12 @@ static void stm32_uart_get_dma_config(void) uart_obj[UART2_INDEX].uart_dma_flag = 0; #ifdef BSP_UART2_RX_USING_DMA uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; + static const struct stm32_dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; #endif #ifdef BSP_UART2_TX_USING_DMA uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; + static const struct stm32_dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx; #endif #endif @@ -955,12 +948,12 @@ static void stm32_uart_get_dma_config(void) uart_obj[UART3_INDEX].uart_dma_flag = 0; #ifdef BSP_UART3_RX_USING_DMA uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG; + static const struct stm32_dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG; uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx; #endif #ifdef BSP_UART3_TX_USING_DMA uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG; + static const struct stm32_dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG; uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx; #endif #endif @@ -969,12 +962,12 @@ static void stm32_uart_get_dma_config(void) uart_obj[UART4_INDEX].uart_dma_flag = 0; #ifdef BSP_UART4_RX_USING_DMA uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; + static const struct stm32_dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx; #endif #ifdef BSP_UART4_TX_USING_DMA uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG; + static const struct stm32_dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG; uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx; #endif #endif @@ -983,12 +976,12 @@ static void stm32_uart_get_dma_config(void) uart_obj[UART5_INDEX].uart_dma_flag = 0; #ifdef BSP_UART5_RX_USING_DMA uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; + static const struct stm32_dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx; #endif #ifdef BSP_UART5_TX_USING_DMA uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG; + static const struct stm32_dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG; uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx; #endif #endif @@ -997,12 +990,12 @@ static void stm32_uart_get_dma_config(void) uart_obj[UART6_INDEX].uart_dma_flag = 0; #ifdef BSP_UART6_RX_USING_DMA uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; + static const struct stm32_dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx; #endif #ifdef BSP_UART6_TX_USING_DMA uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG; + static const struct stm32_dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG; uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx; #endif #endif @@ -1011,12 +1004,12 @@ static void stm32_uart_get_dma_config(void) uart_obj[UART7_INDEX].uart_dma_flag = 0; #ifdef BSP_UART7_RX_USING_DMA uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG; + static const struct stm32_dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG; uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx; #endif #ifdef BSP_UART7_TX_USING_DMA uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG; + static const struct stm32_dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG; uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx; #endif #endif @@ -1025,12 +1018,12 @@ static void stm32_uart_get_dma_config(void) uart_obj[UART8_INDEX].uart_dma_flag = 0; #ifdef BSP_UART8_RX_USING_DMA uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG; + static const struct stm32_dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG; uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx; #endif #ifdef BSP_UART8_TX_USING_DMA uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG; + static const struct stm32_dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG; uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx; #endif #endif @@ -1039,7 +1032,7 @@ static void stm32_uart_get_dma_config(void) uart_obj[LPUART1_INDEX].uart_dma_flag = 0; #ifdef BSP_LPUART1_RX_USING_DMA uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG; + static const struct stm32_dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG; uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx; #endif #endif @@ -1050,7 +1043,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) { struct rt_serial_rx_fifo *rx_fifo; DMA_HandleTypeDef *DMA_Handle; - struct dma_config *dma_config; + const struct stm32_dma_config *dma_config; struct stm32_uart *uart; RT_ASSERT(serial != RT_NULL); @@ -1069,81 +1062,27 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) } LOG_D("%s dma config start", uart->config->name); - { - rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \ - || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, dma_config->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc); -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \ - || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc); - tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc); -#elif defined(SOC_SERIES_STM32MP1) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc); - tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc); -#endif - -#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1) - /* enable DMAMUX clock for L4+ and G4 */ - __HAL_RCC_DMAMUX1_CLK_ENABLE(); -#elif defined(SOC_SERIES_STM32MP1) - __HAL_RCC_DMAMUX_CLK_ENABLE(); -#endif - - UNUSED(tmpreg); /* To avoid compiler warnings */ - } - - if (RT_DEVICE_FLAG_DMA_RX == flag) - { - __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle); - } - else if (RT_DEVICE_FLAG_DMA_TX == flag) - { - __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle); - } - -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) - DMA_Handle->Instance = dma_config->Instance; -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - DMA_Handle->Instance = dma_config->Instance; - DMA_Handle->Init.Channel = dma_config->channel; -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\ - || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) - DMA_Handle->Instance = dma_config->Instance; - DMA_Handle->Init.Request = dma_config->request; -#endif - DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE; - DMA_Handle->Init.MemInc = DMA_MINC_ENABLE; - DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - if (RT_DEVICE_FLAG_DMA_RX == flag) { - DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY; - DMA_Handle->Init.Mode = DMA_CIRCULAR; + if (stm32_dma_setup(DMA_Handle, + &(uart->handle), + &uart->handle.hdmarx, + dma_config) != RT_EOK) + { + LOG_E("%s dma rx config failed", uart->config->name); + return; + } } else if (RT_DEVICE_FLAG_DMA_TX == flag) { - DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH; - DMA_Handle->Init.Mode = DMA_NORMAL; - } - - DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM; -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) - DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE; -#endif - if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK) - { - RT_ASSERT(0); - } - - if (HAL_DMA_Init(DMA_Handle) != HAL_OK) - { - RT_ASSERT(0); + if (stm32_dma_setup(DMA_Handle, + &(uart->handle), + &uart->handle.hdmatx, + dma_config) != RT_EOK) + { + LOG_E("%s dma tx config failed", uart->config->name); + return; + } } /* enable interrupt */ @@ -1154,16 +1093,19 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK) { /* Transfer error in reception process */ - RT_ASSERT(0); + LOG_E("%s uart dma rx start failed", uart->config->name); + if (stm32_dma_deinit(DMA_Handle, dma_config, RT_FALSE) != RT_EOK) + { + LOG_E("%s uart dma rx rollback failed", uart->config->name); + } + uart->handle.hdmarx = RT_NULL; + DMA_Handle->Parent = RT_NULL; + return; } CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE); __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE); } - /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */ - HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0); - HAL_NVIC_EnableIRQ(dma_config->dma_irq); - HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); HAL_NVIC_EnableIRQ(uart->config->irq_type); diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h index f8b5e16af93..0fe1150246e 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h @@ -7,7 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version * 2019-03-05 whj4674672 add stm32h7 - * 2020-10-14 PeakRacing Porting for stm32wbxx + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx */ #ifndef __DRV_USART_H__ @@ -51,8 +51,8 @@ struct stm32_uart_config const char *name; USART_TypeDef *Instance; IRQn_Type irq_type; - struct dma_config *dma_rx; - struct dma_config *dma_tx; + const struct stm32_dma_config *dma_rx; + const struct stm32_dma_config *dma_tx; }; /* stm32 uart dirver class */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.c index 3dc578ba7e0..bb508db53bd 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.c @@ -237,28 +237,18 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar { __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE); - HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq); - if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK) + if (stm32_dma_deinit(&(uart->dma_rx.handle), uart->config->dma_rx, RT_TRUE) != RT_EOK) { - RT_ASSERT(0); - } - - if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK) - { - RT_ASSERT(0); + LOG_E("%s dma rx deinit failed", uart->config->name); } } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC); - HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq); - - HAL_DMA_Abort(&(uart->dma_tx.handle)); - - if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK) + if (stm32_dma_deinit(&(uart->dma_tx.handle), uart->config->dma_tx, RT_TRUE) != RT_EOK) { - RT_ASSERT(0); + LOG_E("%s dma tx deinit failed", uart->config->name); } } #endif @@ -286,19 +276,24 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg); break; - case RT_DEVICE_CHECK_OPTMODE: { + case RT_DEVICE_CHECK_OPTMODE: + { if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX) return RT_SERIAL_TX_BLOCKING_NO_BUFFER; else return RT_SERIAL_TX_BLOCKING_BUFFER; } case RT_DEVICE_CTRL_CLOSE: - if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK) + { + HAL_StatusTypeDef status = HAL_UART_DeInit(&uart->handle); + if (status != HAL_OK) { - RT_ASSERT(0) + LOG_E("(%s) serial deinit error %d!", serial->parent.parent.name, status); } break; } + } + return RT_EOK; } @@ -928,13 +923,13 @@ static void stm32_uart_get_config(void) #ifdef BSP_UART1_RX_USING_DMA uart_obj[UART1_INDEX].serial.config.dma_ping_bufsz = BSP_UART1_DMA_PING_BUFSIZE; uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; + static const struct stm32_dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; #endif #ifdef BSP_UART1_TX_USING_DMA uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; + static const struct stm32_dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx; #endif #endif @@ -949,13 +944,13 @@ static void stm32_uart_get_config(void) #ifdef BSP_UART2_RX_USING_DMA uart_obj[UART2_INDEX].serial.config.dma_ping_bufsz = BSP_UART2_DMA_PING_BUFSIZE; uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; + static const struct stm32_dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; #endif #ifdef BSP_UART2_TX_USING_DMA uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; + static const struct stm32_dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx; #endif #endif @@ -970,13 +965,13 @@ static void stm32_uart_get_config(void) #ifdef BSP_UART3_RX_USING_DMA uart_obj[UART3_INDEX].serial.config.dma_ping_bufsz = BSP_UART3_DMA_PING_BUFSIZE; uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG; + static const struct stm32_dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG; uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx; #endif #ifdef BSP_UART3_TX_USING_DMA uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG; + static const struct stm32_dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG; uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx; #endif #endif @@ -991,13 +986,13 @@ static void stm32_uart_get_config(void) #ifdef BSP_UART4_RX_USING_DMA uart_obj[UART4_INDEX].serial.config.dma_ping_bufsz = BSP_UART4_DMA_PING_BUFSIZE; uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; + static const struct stm32_dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx; #endif #ifdef BSP_UART4_TX_USING_DMA uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG; + static const struct stm32_dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG; uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx; #endif #endif @@ -1012,13 +1007,13 @@ static void stm32_uart_get_config(void) #ifdef BSP_UART5_RX_USING_DMA uart_obj[UART5_INDEX].serial.config.dma_ping_bufsz = BSP_UART5_DMA_PING_BUFSIZE; uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; + static const struct stm32_dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx; #endif #ifdef BSP_UART5_TX_USING_DMA uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG; + static const struct stm32_dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG; uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx; #endif #endif @@ -1033,13 +1028,13 @@ static void stm32_uart_get_config(void) #ifdef BSP_UART6_RX_USING_DMA uart_obj[UART6_INDEX].serial.config.dma_ping_bufsz = BSP_UART6_DMA_PING_BUFSIZE; uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; + static const struct stm32_dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx; #endif #ifdef BSP_UART6_TX_USING_DMA uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG; + static const struct stm32_dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG; uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx; #endif #endif @@ -1054,13 +1049,13 @@ static void stm32_uart_get_config(void) #ifdef BSP_UART7_RX_USING_DMA uart_obj[UART7_INDEX].serial.config.dma_ping_bufsz = BSP_UART7_DMA_PING_BUFSIZE; uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG; + static const struct stm32_dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG; uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx; #endif #ifdef BSP_UART7_TX_USING_DMA uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG; + static const struct stm32_dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG; uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx; #endif #endif @@ -1074,14 +1069,14 @@ static void stm32_uart_get_config(void) #ifdef BSP_UART8_RX_USING_DMA uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG; + static const struct stm32_dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG; uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx; #endif #ifdef BSP_UART8_TX_USING_DMA uart_obj[UART8_INDEX].serial.config.dma_ping_bufsz = BSP_UART8_DMA_PING_BUFSIZE; uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG; + static const struct stm32_dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG; uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx; #endif #endif @@ -1096,7 +1091,7 @@ static void stm32_uart_get_config(void) #ifdef BSP_LPUART1_RX_USING_DMA uart_obj[LPUART1_INDEX].serial.config.dma_ping_bufsz = BSP_LPUART1_DMA_PING_BUFSIZE; uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG; + static const struct stm32_dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG; uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx; #endif #endif @@ -1106,7 +1101,7 @@ static void stm32_uart_get_config(void) static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) { DMA_HandleTypeDef *DMA_Handle; - struct dma_config *dma_config; + const struct stm32_dma_config *dma_config; struct stm32_uart *uart; RT_ASSERT(serial != RT_NULL); @@ -1125,81 +1120,27 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) } LOG_D("%s dma config start", uart->config->name); - { - rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \ - || defined(SOC_SERIES_STM32L0) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, dma_config->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc); -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \ - || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc); - tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc); -#elif defined(SOC_SERIES_STM32MP1) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc); - tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc); -#endif - -#if defined(DMAMUX1) && (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) - /* enable DMAMUX clock for L4+ and G4 */ - __HAL_RCC_DMAMUX1_CLK_ENABLE(); -#elif defined(SOC_SERIES_STM32MP1) - __HAL_RCC_DMAMUX_CLK_ENABLE(); -#endif - - UNUSED(tmpreg); /* To avoid compiler warnings */ - } - if (RT_DEVICE_FLAG_DMA_RX == flag) { - __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle); - } - else if (RT_DEVICE_FLAG_DMA_TX == flag) - { - __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle); - } - -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) - DMA_Handle->Instance = dma_config->Instance; -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - DMA_Handle->Instance = dma_config->Instance; - DMA_Handle->Init.Channel = dma_config->channel; -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB) \ - || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) - DMA_Handle->Instance = dma_config->Instance; - DMA_Handle->Init.Request = dma_config->request; -#endif - DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE; - DMA_Handle->Init.MemInc = DMA_MINC_ENABLE; - DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - - if (RT_DEVICE_FLAG_DMA_RX == flag) - { - DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY; - DMA_Handle->Init.Mode = DMA_CIRCULAR; + if (stm32_dma_setup(DMA_Handle, + &(uart->handle), + &uart->handle.hdmarx, + dma_config) != RT_EOK) + { + LOG_E("%s dma rx config failed", uart->config->name); + return; + } } else if (RT_DEVICE_FLAG_DMA_TX == flag) { - DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH; - DMA_Handle->Init.Mode = DMA_NORMAL; - } - - DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM; -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) - DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE; -#endif - if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK) - { - RT_ASSERT(0); - } - - if (HAL_DMA_Init(DMA_Handle) != HAL_OK) - { - RT_ASSERT(0); + if (stm32_dma_setup(DMA_Handle, + &(uart->handle), + &uart->handle.hdmatx, + dma_config) != RT_EOK) + { + LOG_E("%s dma tx config failed", uart->config->name); + return; + } } /* enable interrupt */ @@ -1212,16 +1153,19 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) if (HAL_UART_Receive_DMA(&(uart->handle), ptr, serial->config.dma_ping_bufsz) != HAL_OK) { /* Transfer error in reception process */ - RT_ASSERT(0); + LOG_E("%s uart dma rx start failed", uart->config->name); + if (stm32_dma_deinit(DMA_Handle, dma_config, RT_FALSE) != RT_EOK) + { + LOG_E("%s uart dma rx rollback failed", uart->config->name); + } + uart->handle.hdmarx = RT_NULL; + DMA_Handle->Parent = RT_NULL; + return; } CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE); __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE); } - /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */ - HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0); - HAL_NVIC_EnableIRQ(dma_config->dma_irq); - HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); HAL_NVIC_EnableIRQ(uart->config->irq_type); @@ -1304,12 +1248,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) #endif /* RT_SERIAL_USING_DMA */ static const struct rt_uart_ops stm32_uart_ops = - { - .configure = stm32_configure, - .control = stm32_control, - .putc = stm32_putc, - .getc = stm32_getc, - .transmit = stm32_transmit}; +{ + .configure = stm32_configure, + .control = stm32_control, + .putc = stm32_putc, + .getc = stm32_getc, + .transmit = stm32_transmit +}; int rt_hw_usart_init(void) { diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.h index 2f263a70078..10c2b18a2fa 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.h @@ -56,8 +56,8 @@ struct stm32_uart_config IRQn_Type irq_type; #ifdef RT_SERIAL_USING_DMA - struct dma_config *dma_rx; - struct dma_config *dma_tx; + const struct stm32_dma_config *dma_rx; + const struct stm32_dma_config *dma_tx; #endif };