Session C: HBit dual-band representation (<2 x i64> packed lanes)

Every i64 value in a JITted OMC fn becomes a packed `<2 x i64>` LLVM
vector. Element 0 is the alpha band (the classical user-visible
value); element 1 is the beta band (the harmonic shadow). All
arithmetic, bitwise, and comparison ops emit packed vector
instructions that LLVM lowers to single SSE2 instructions on
x86-64 (paddq, psubq, pmuludq, etc).

This is the architectural shape Sovereign Lattice's HBit demos
target (per hbit_full_demo.omc — "dual-band registers (alpha, beta)",
"parallel alpha/beta computation"). Session C does the structural
work; later sessions add the cost-cut mechanisms on top.

New: omnimcode-codegen/src/dual_band.rs
  - DualBandLowerer struct mirrors FunctionLowerer's two-pass CFG
    construction (collect_leaders, collect_cleanup_pops, emit_body)
    but with VectorValue<<2 x i64>> as the carrier instead of i64.
  - Helpers: splat (scalar i64 -> <a,a>), bin_vec, cmp_vec,
    logical_vec — all emit packed ops.
  - Branch ops extract the alpha lane for the conditional decision
    (control flow is determined by the classical value, not by beta).
  - Recursive Call extracts alpha at the call boundary, calls the
    scalar entry, splats the i64 return back to vector.
  - Caller-facing fn signature stays scalar (i64 in, i64 out); the
    vector representation is internal. Lets the same JIT-lookup
    helpers (`get_i64_i64`) work for both modes.

New: JitContext::lower_function_dual_band(f) method
  - Emits a `<original_name>_hbit` suffixed fn so scalar and
    dual-band versions can coexist in the same module for
    parity testing.

Tests (5 parity + 1 IR snapshot, all passing):
  - hbit_double_matches_scalar: x+x matches scalar lowering
  - hbit_factorial_matches_scalar: factorial(0..12) matches
    including the recursive Call through the alpha-extract boundary
  - hbit_sum_to_n_matches_scalar: while loop with two locals
    (s, k) allocated as `alloca <2 x i64>`
  - hbit_max_with_branches: if/else with a comparison-driven branch
  - hbit_emitted_ir_contains_vector_ops: greps the printed IR
    for `<2 x i64>` and `add <2 x i64>` (architectural proof)
  - dual_band_ir_shape_for_double: snapshot test pinning the
    expected vector-op markers in IR so regressions break loud

What's NOT yet in Session C (deferred to Session D+):
  - Alpha and beta divergence — they're matched throughout. A
    `PhiShadow` op or `harmonic_shadow(x)` builtin that sets
    beta = phi_fold(alpha) is Session D's job.
  - @hbit pragma routing OMC source through dual-band codegen.
  - AVX-512 intrinsics for wider-than-128-bit packed dispatch.
  - Harmony monitoring opcode + predictive correction.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

Author: RandomCoder-lab