Decoder.v

// msrv32_decoder 21BCE0289
module msrv32_decoder(
	input trap_taken_in,
	input funct7_5_in,
	input [6:0] opcode_in,
	input [2:0] funct3_in,
	input [1:0] iadder_out_1_to_0_in,
	output [2:0] wb_mux_sel_out,
	output [2:0] imm_type_out,
	output [2:0] csr_op_out,
	output mem_wr_req_out,
	output [3:0] alu_opcode_out,
	output [1:0] load_size_out,
	output load_unsigned_out,
	output alu_src_out,
	output iadder_src_out,
	output csr_wr_en_out,
	output rf_wr_en_out,
	output illegal_instr_out,
	output misaligned_load_out,
	output misaligned_store_out
);

	reg is_branch;
	reg is_jal;
	reg is_jalr;
	reg is_auipc;
	reg is_lui;
	reg is_op;
	reg is_op_imm;
	reg is_load;
	reg is_store;
	reg is_system;
	reg is_misc_mem;

	reg is_csr;

	reg is_addi;
	reg is_slti;
	reg is_sltiu;
	reg is_andi;
	reg is_ori;
	reg is_xori;

	wire mal_word;
	wire mal_half;

	Functionality_Block Func_block(
		.is_branch(is_branch),
		.is_jal(is_jal),
		.is_jalr(is_jalr),
		.is_auipc(is_auipc),
		.is_lui(is_lui),
		.is_op(is_op),
		.is_op_imm(is_op_imm),
		.is_load(is_load),
		.is_store(is_store),
		.is_system(is_system),
		.is_misc_mem(is_misc_mem),
		.is_csr(is_csr),
		.rf_wr_en_out(rf_wr_en_out),
		.imm_type_out(imm_type_out),
		.wb_mux_sel_out(wb_mux_sel_out),
		.iaddr_src_out(iaddr_src_out),
		.is_implemented_instr(is_implemented_instr)
	);

	decoder_to_encoder_block decoder_encoder(
		.funct3_in(funct3_in),
		.is_op_imm(is_op_imm),
		.funct7_5_in(funct7_5_in),
		.w_alu_opcode_out(alu_opcode_out[3])
	);

	always@(*) begin
		is_branch = (opcode_in == 5'b11000) ? 1'b1 : 1'b0;
		is_jal = (opcode_in == 5'b11011) ? 1'b1 : 1'b0;
		is_jalr = (opcode_in == 5'b11001) ? 1'b1 : 1'b0;
		is_auipc = (opcode_in == 5'b00101) ? 1'b1 : 1'b0;
		is_lui = (opcode_in == 5'b01101) ? 1'b1 : 1'b0;
		is_op = (opcode_in == 5'b01100) ? 1'b1 : 1'b0;
		is_op_imm = (opcode_in == 5'b00100) ? 1'b1 : 1'b0;
		is_load = (opcode_in == 5'b00000) ? 1'b1 : 1'b0;
		is_store = (opcode_in == 5'b01000) ? 1'b1 : 1'b0;
		is_system = (opcode_in == 5'b11100) ? 1'b1 : 1'b0;
		is_misc_mem = (opcode_in == 5'b00011) ? 1'b1 : 1'b0;

		is_csr = ((funct3_in[0] | funct3_in[1] | funct3_in[2]) & is_system);
	end
	
	assign csr_wr_en_out = is_csr;
	assign illegal_instr_out = (~(is_implemented_instr)) | (~(opcode_in[1])) | (~(opcode_in[0]));
	assign alu_opcode_out[2:0] = funct3_in;
	assign load_size_out = funct3_in[1:0];
	assign load_unsigned_out = funct3_in[2];
	assign alu_src_out = opcode_in[5];
	assign iadder_src_out = (is_load | is_store | is_jalr);
	assign csr_op_out = funct3_in;
	assign mal_word = ((funct3_in[1] == 1'b1) && (iadder_out_1_to_0_in != 0)) ? 1'b1 : 1'b0;
	assign mal_half = ((funct3_in[0] == 1'b1) && (iadder_out_1_to_0_in[0] != 0)) ? 1'b1 : 1'b0;
	assign misaligned_load_out = ((mal_word | mal_half) & (is_load));
	assign misaligned_store_out = ((mal_word | mal_half) & (is_store));
	assign mem_wr_req_out = ((is_store) & (~(trap_taken_in | mal_word | mal_half)));
endmodule

module Functionality_Block(
	input is_branch,
	input is_jal,
	input is_jalr,
	input is_auipc,
	input is_lui,
	input is_op,
	input is_op_imm,
	input is_load,
	input is_store,
	input is_system,
	input is_misc_mem,
	input is_csr,
	output reg rf_wr_en_out,
	output reg [2:0] imm_type_out,
	output reg [2:0] wb_mux_sel_out,
	output reg iaddr_src_out,
	output reg is_implemented_instr
);
	always@(*) begin
		rf_wr_en_out = is_lui | is_auipc | is_jalr | is_jal | is_op | is_load | is_csr | is_op_imm;
	
		imm_type_out[0] = is_op_imm | is_load | is_jalr | is_branch | is_jal;
		imm_type_out[1] = is_store | is_branch | is_csr;
		imm_type_out[2] = is_lui | is_auipc | is_jal | is_csr;
	
		wb_mux_sel_out[0] = is_load | is_auipc | is_jal | is_jalr;
		wb_mux_sel_out[1] = is_lui | is_auipc;
		wb_mux_sel_out[2] = is_csr | is_jal | is_jalr;

		iaddr_src_out = is_load | is_store | is_jalr;

		is_implemented_instr = is_branch | is_lui | is_auipc | is_jalr | is_jal | is_op | is_load | is_store | is_system | is_csr | is_op_imm | is_misc_mem;
	end

endmodule

module decoder_to_encoder_block(
	input [2:0] funct3_in,
	input is_op_imm,
	input funct7_5_in,
	output w_alu_opcode_out
);
	parameter ADD = 3'b000,
		SLT = 3'b010,
		SLTU = 3'b100,
		AND = 3'b101,
		OR = 3'b110,
		XOR = 3'b111;

	reg w_000;
	reg w_010;
	reg w_100;
	reg w_101;
	reg w_110;
	reg w_111;

	wire is_addi;
	wire is_slti;
	wire is_sltiu;
	wire is_andi;
	wire is_ori;
	wire is_xori;

	wire w_alu;

	always@(*) begin
		w_000 = (funct3_in == ADD) ? 1'b1 : 1'b0;
		w_010 = (funct3_in == SLT) ? 1'b1 : 1'b0;
		w_100 = (funct3_in == SLTU) ? 1'b1 : 1'b0;
		w_101 = (funct3_in == AND) ? 1'b1 : 1'b0;
		w_110 = (funct3_in == OR) ? 1'b1 : 1'b0;
		w_111 = (funct3_in == XOR) ? 1'b1 : 1'b0;
	end
	
	assign is_addi = w_000 & is_op_imm;
	assign is_slti = w_010 & is_op_imm;
	assign is_sltiu = w_100 & is_op_imm;
	assign is_andi = w_101 & is_op_imm;
	assign is_ori = w_110 & is_op_imm;
	assign is_xori = w_111 & is_op_imm;
	assign w_alu = ~(is_addi | is_slti | is_sltiu | is_andi | is_ori | is_xori);
	assign w_alu_opcode_out = funct7_5_in & w_alu;
endmodule