ModelSim-Practice-VLSI-design/Decoder_tb.v at main · Rickisterr/ModelSim-Practice-VLSI-design · GitHub

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// Testbench for msrv32_decoder 21BCE0289
module Testbench_Decoder;
	reg trap_taken_in;
	reg funct7_5_in;
	reg [6:0] opcode_in;
	reg [2:0] funct3_in;
	reg [1:0] iadder_out_1_to_0_in;
	wire [2:0] wb_mux_sel_out;
	wire [2:0] imm_type_out;
	wire [2:0] csr_op_out;
	wire mem_wr_req_out;
	wire [3:0] alu_opcode_out;
	wire [1:0] load_size_out;
	wire load_unsigned_out;
	wire alu_src_out;
	wire iadder_src_out;
	wire csr_wr_en_out;
	wire rf_wr_en_out;
	wire illegal_instr_out;
	wire misaligned_load_out;
	wire misaligned_store_out;

	msrv32_decoder Decoder(
		.trap_taken_in(trap_taken_in),
		.funct7_5_in(funct7_5_in),
		.opcode_in(opcode_in),
		.funct3_in(funct3_in),
		.iadder_out_1_to_0_in(iadder_out_1_to_0_in),
		.wb_mux_sel_out(wb_mux_sel_out),
		.imm_type_out(imm_type_out),
		.csr_op_out(csr_op_out),
		.mem_wr_req_out(mem_wr_req_out),
		.alu_opcode_out(alu_opcode_out),
		.load_size_out(load_size_out),
		.load_unsigned_out(load_unsigned_out),
		.alu_src_out(alu_src_out),
		.iadder_src_out(iadder_src_out),
		.csr_wr_en_out(csr_wr_en_out),
		.rf_wr_en_out(rf_wr_en_out),
		.illegal_instr_out(illegal_instr_out),
		.misaligned_load_out(misaligned_load_out),
		.misaligned_store_out(misaligned_store_out)
	);

	initial begin
		trap_taken_in = 0;
		funct7_5_in = 1;
		opcode_in = 7'b011_0011;
		funct3_in = 3'b110;
		iadder_out_1_to_0_in = 2'b01;
		#10;

		iadder_out_1_to_0_in = 2'b00;
		#10;

		iadder_out_1_to_0_in = 2'b01;
		funct7_5_in = 0;
		opcode_in = 7'b000_0011;
		funct3_in = 3'b001;
		#10;

		funct3_in = 3'b010;
		#10;

		opcode_in = 7'b110_0111;
		funct3_in = 3'b000;
		#10;

		opcode_in = 7'b111_1111;
		#10;

		$stop;
	end

	always@(*) begin
		$display($time, "ns: trap_taken_in: %b, funct7_5_in: %b, opcode_in: %b, funct3_in: %b, iadder_out_1_to_0_in: %b", trap_taken_in, funct7_5_in, opcode_in, funct3_in, iadder_out_1_to_0_in);
	end
endmodule