ModelSim-Practice-VLSI-design/Load_Unit_tb.v.bak at main · Rickisterr/ModelSim-Practice-VLSI-design · GitHub

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// Testbench for msrv32_load_unit 21BCE0289
module Testbench_Load_Unit;
	reg ahb_resp_in;
	reg [31:0] ms_riscv32_mp_dmdata_in;
	reg [1:0] iadder_out_1_to_0_in;
	reg load_unsigned_in;
	reg [1:0] load_size_in;
	wire [31:0] lu_output_out;

	Load_Unit msrv32_load_unit(
		.ahb_resp_in(ahb_resp_in),
		.ms_riscv32_mp_dmdata_in(ms_riscv32_mp_dmdata_in),
		.iadder_out_1_to_0_in(iadder_out_1_to_0_in),
		.load_unsigned_in(load_unsigned_in),
		.load_size_in(load_size_in),
		.lu_output_out(lu_output_out)
	);

	initial begin
		ahb_resp_in = 1;
		ms_riscv32_mp_dmdata_in = 32'hf7f5f3f1;
		iadder_out_1_to_0_in = 2'b10;
		load_unsigned_in = 1;
		load_size_in = 2'b00;
		#10;

		ahb_resp_in = 0;
		#10;

		iadder_out_1_to_0_in = 2'b11;
		load_unsigned_in = 0;
		load_size_in = 2'b01;
		#10;

		load_size_in = 2'b11;
		#10;

		$stop;
	end

	always #10 $display($time, "ns: Output: %h", lu_output_out);
endmodule