-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathProcessor.cr.mti
More file actions
223 lines (161 loc) · 9.66 KB
/
Processor.cr.mti
File metadata and controls
223 lines (161 loc) · 9.66 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
C:/Users/sinha/Documents/Modelsim/Decoder_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Decoder_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_Decoder
Top level modules:
Testbench_Decoder
} {} {}} C:/Users/sinha/Documents/Modelsim/Instruction_Mux.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Instruction_Mux.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_instruction_mux
Top level modules:
msrv32_instruction_mux
} {} {}} C:/Users/sinha/Documents/Modelsim/Load_Unit_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Load_Unit_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_Load_Unit
Top level modules:
Testbench_Load_Unit
} {} {}} C:/Users/sinha/Documents/Modelsim/Store_Unit.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Store_Unit.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_store_unit
Top level modules:
msrv32_store_unit
} {} {}} C:/Users/sinha/Documents/Modelsim/Branch_Unit.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Branch_Unit.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_branch_unit
Top level modules:
msrv32_branch_unit
} {} {}} C:/Users/sinha/Documents/Modelsim/Reg_Block_2_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Reg_Block_2_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_Reg_Block_2
Top level modules:
Testbench_Reg_Block_2
} {} {}} C:/Users/sinha/Documents/Modelsim/Decoder.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Decoder.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_decoder
-- Compiling module Functionality_Block
-- Compiling module decoder_to_encoder_block
Top level modules:
msrv32_decoder
} {} {}} C:/Users/sinha/Documents/Modelsim/ALU_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/ALU_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_ALU
Top level modules:
Testbench_ALU
} {} {}} C:/Users/sinha/Documents/Modelsim/Write_Enable_Generator.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Write_Enable_Generator.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_wr_en_generator
Top level modules:
msrv32_wr_en_generator
} {} {}} C:/Users/sinha/Documents/Modelsim/Instruction_Mux_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Instruction_Mux_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_Instruction_Mux
Top level modules:
Testbench_Instruction_Mux
} {} {}} C:/Users/sinha/Documents/Modelsim/PC_MUX_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/PC_MUX_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_PC_MUX
Top level modules:
Testbench_PC_MUX
} {} {}} C:/Users/sinha/Documents/Modelsim/msrv32_machine_control.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/msrv32_machine_control.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_machine_control
Top level modules:
msrv32_machine_control
} {} {}} C:/Users/sinha/Documents/Modelsim/ALU.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/ALU.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_alu
Top level modules:
msrv32_alu
} {} {}} C:/Users/sinha/Documents/Modelsim/Branch_Unit_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Branch_Unit_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbranch_Branch_Unit
Top level modules:
Testbranch_Branch_Unit
} {} {}} C:/Users/sinha/Documents/Modelsim/msrv32_csr_file.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/msrv32_csr_file.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_csr_file
Top level modules:
msrv32_csr_file
} {} {}} C:/Users/sinha/Documents/Modelsim/Immediate_adder_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Immediate_adder_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_Immediate_adder
Top level modules:
Testbench_Immediate_adder
} {} {}} C:/Users/sinha/Documents/Modelsim/WB_Mux_Selection_Unit_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/WB_Mux_Selection_Unit_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_WB_Mux_Selection_Unit
Top level modules:
Testbench_WB_Mux_Selection_Unit
} {} {}} C:/Users/sinha/Documents/Modelsim/PC_MUX.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/PC_MUX.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module PC_add4
-- Compiling module Mux2x1
-- Compiling module Mux4x2
-- Compiling module msrv32_pc
Top level modules:
msrv32_pc
} {} {}} C:/Users/sinha/Documents/Modelsim/Write_Enable_Generator_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Write_Enable_Generator_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_Write_Enable_Generator
Top level modules:
Testbench_Write_Enable_Generator
} {} {}} C:/Users/sinha/Documents/Modelsim/Immediate_generator.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Immediate_generator.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_imm_generator
Top level modules:
msrv32_imm_generator
} {} {}} C:/Users/sinha/Documents/Modelsim/Integer_File.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Integer_File.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_integer_file
Top level modules:
msrv32_integer_file
} {} {}} C:/Users/sinha/Documents/Modelsim/Reg_Block_1_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Reg_Block_1_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_Reg_Block_1
Top level modules:
Testbench_Reg_Block_1
} {} {}} C:/Users/sinha/Documents/Modelsim/Immediate_adder.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Immediate_adder.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_imm_adder
Top level modules:
msrv32_imm_adder
} {} {}} C:/Users/sinha/Documents/Modelsim/WB_Mux_Selection_Unit.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/WB_Mux_Selection_Unit.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_wb_mux_sel_unit
Top level modules:
msrv32_wb_mux_sel_unit
} {} {}} C:/Users/sinha/Documents/Modelsim/Load_Unit.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Load_Unit.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_load_unit
Top level modules:
msrv32_load_unit
} {} {}} C:/Users/sinha/Documents/Modelsim/msrv32_top.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/msrv32_top.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_top
Top level modules:
msrv32_top
} {} {}} C:/Users/sinha/Documents/Modelsim/Reg_Block_1.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Reg_Block_1.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_reg_block_1
Top level modules:
msrv32_reg_block_1
} {} {}} C:/Users/sinha/Documents/Modelsim/Reg_Block_2.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Reg_Block_2.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module msrv32_reg_block2
Top level modules:
msrv32_reg_block2
} {} {}} C:/Users/sinha/Documents/Modelsim/Store_Unit_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Store_Unit_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_Store_Unit
Top level modules:
Testbench_Store_Unit
} {} {}} C:/Users/sinha/Documents/Modelsim/Immediate_generator_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Immediate_generator_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_Immediate_generator
Top level modules:
Testbench_Immediate_generator
} {} {}} C:/Users/sinha/Documents/Modelsim/Integer_File_tb.v {1 {vlog -work work -stats=none C:/Users/sinha/Documents/Modelsim/Integer_File_tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Testbench_Integer_File
Top level modules:
Testbench_Integer_File
} {} {}}