AES/transcript at main · Safan05/AES · GitHub

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# Reading pref.tcl
# OpenFile {D:/CUFE/1st Year/2nd term/logical design/AES.vs/ShiftRows_inv.v}
vlib work
vlog -reportprogress 300 -work work {D:/CUFE/1st Year/2nd term/logical design/AES.vs/ShiftRows_inv.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:17:10 on Apr 28,2024
# vlog -reportprogress 300 -work work D:/CUFE/1st Year/2nd term/logical design/AES.vs/ShiftRows_inv.v
# -- Compiling module ShiftRows_inv
#
# Top level modules:
# 	ShiftRows_inv
# End time: 16:17:10 on Apr 28,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlib work
# ** Warning: (vlib-34) Library already exists at "work".
vlog -reportprogress 300 -work work {D:/CUFE/1st Year/2nd term/logical design/AES.vs/ShiftRows_inv.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:17:18 on Apr 28,2024
# vlog -reportprogress 300 -work work D:/CUFE/1st Year/2nd term/logical design/AES.vs/ShiftRows_inv.v
# -- Compiling module ShiftRows_inv
#
# Top level modules:
# 	ShiftRows_inv
# End time: 16:17:18 on Apr 28,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work {D:/CUFE/1st Year/2nd term/logical design/AES.vs/work/ShiftRows_inv.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:17:32 on Apr 28,2024
# vlog -reportprogress 300 -work work D:/CUFE/1st Year/2nd term/logical design/AES.vs/work/ShiftRows_inv.v
# ** Error: (vlog-7) Failed to open design unit file "D:/CUFE/1st Year/2nd term/logical design/AES.vs/work/ShiftRows_inv.v" in read mode.
# No such file or directory. (errno = ENOENT)
# End time: 16:17:32 on Apr 28,2024, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0