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VLSI-System-Design

NCKU graduated level 2023

Lab 1 - 5 stage RISC-V CPU

RV32I-M with CSR instruction

Lab 2 - CPU + AXI

Implementation of AXI bus

Lab 3 - A system with CPU, SRAM, ROM, DRAM, Sensor and WDT

Build a system based on Lab2 and it supports ISR

Lab4 - A multi-clock domain system with level 1 cache

Add two level 1 cache for CPU, and deal with CDC by aFIFO

Final Project - A low bandwidth image compression system

Implement the JPEG compression EPU and embedded into the system