From 72e38ecd4caead3d2d5979514d41e2bbf0126cca Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Sat, 28 Feb 2026 05:58:55 +0000 Subject: [PATCH 1/3] Initial plan From 5df57d78b3a9141abf83b40085e0732a09a96fad Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Sat, 28 Feb 2026 06:03:39 +0000 Subject: [PATCH 2/3] Add API documentation for HDElkDiagramGen Co-authored-by: Readon <3614708+Readon@users.noreply.github.com> --- .../Libraries/EDA/tools/hdelkdiagramgen.rst | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 source/SpinalHDL/Libraries/EDA/tools/hdelkdiagramgen.rst diff --git a/source/SpinalHDL/Libraries/EDA/tools/hdelkdiagramgen.rst b/source/SpinalHDL/Libraries/EDA/tools/hdelkdiagramgen.rst new file mode 100644 index 00000000000..d5659d1e8ea --- /dev/null +++ b/source/SpinalHDL/Libraries/EDA/tools/hdelkdiagramgen.rst @@ -0,0 +1,43 @@ + +HDElkDiagramGen +=============== + +``HDElkDiagramGen`` is a tool that generates an interactive block diagram of a SpinalHDL design in an HTML file. +After running elaboration, pass the ``SpinalReport`` returned by ``SpinalVerilog`` or ``SpinalVHDL`` to generate the diagram. +Open the resulting HTML file in any modern web browser to explore the hierarchy. + +.. code-block:: scala + + import spinal.lib.tools.HDElkDiagramGen + + HDElkDiagramGen(SpinalVerilog(new MyToplevel)) + +This will create a file named ``MyToplevel.html`` in the current working directory. + +Usage +----- + +The tool accepts the ``SpinalReport`` produced by ``SpinalVerilog`` or ``SpinalVHDL``: + +.. code-block:: scala + + import spinal.lib.tools.HDElkDiagramGen + + // With Verilog output + HDElkDiagramGen(SpinalVerilog(new MyToplevel)) + + // With VHDL output + HDElkDiagramGen(SpinalVHDL(new MyToplevel)) + +Output +------ + +The generated ``.html`` file contains an interactive block diagram for every module in the design hierarchy, rendered using the `HDElk `_ library. +Open it in any modern web browser to navigate between diagrams. + +The diagram shows: + +* Input and output ports of each module +* Internal signals and registers +* Connections between sub-modules +* Clock domain colouring (each clock domain is assigned a distinct highlight colour; mixed-clock modules are marked separately) From d5f195073eeaa09ca37d2cf71151ef227ae60852 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Sat, 28 Feb 2026 06:06:44 +0000 Subject: [PATCH 3/3] Update HDElkDiagramGen docs: use SpinalSchemaGen package and add dependency Co-authored-by: Readon <3614708+Readon@users.noreply.github.com> --- .../Libraries/EDA/tools/hdelkdiagramgen.rst | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/source/SpinalHDL/Libraries/EDA/tools/hdelkdiagramgen.rst b/source/SpinalHDL/Libraries/EDA/tools/hdelkdiagramgen.rst index d5659d1e8ea..45fa3a0a338 100644 --- a/source/SpinalHDL/Libraries/EDA/tools/hdelkdiagramgen.rst +++ b/source/SpinalHDL/Libraries/EDA/tools/hdelkdiagramgen.rst @@ -2,18 +2,28 @@ HDElkDiagramGen =============== -``HDElkDiagramGen`` is a tool that generates an interactive block diagram of a SpinalHDL design in an HTML file. +``HDElkDiagramGen`` is a tool from the `SpinalSchemaGen `_ library that generates an interactive block diagram of a SpinalHDL design as an HTML file. After running elaboration, pass the ``SpinalReport`` returned by ``SpinalVerilog`` or ``SpinalVHDL`` to generate the diagram. Open the resulting HTML file in any modern web browser to explore the hierarchy. .. code-block:: scala - import spinal.lib.tools.HDElkDiagramGen + import spinal.schema.elk.HDElkDiagramGen HDElkDiagramGen(SpinalVerilog(new MyToplevel)) This will create a file named ``MyToplevel.html`` in the current working directory. +Setup +----- + +``HDElkDiagramGen`` lives in the separate ``spinalhdl-schema-gen`` library. +Add the following dependency to your ``build.sbt``: + +.. code-block:: scala + + libraryDependencies += "com.github.spinalhdl" %% "spinalhdl-schema-gen" % "0.0.4" + Usage ----- @@ -21,7 +31,7 @@ The tool accepts the ``SpinalReport`` produced by ``SpinalVerilog`` or ``SpinalV .. code-block:: scala - import spinal.lib.tools.HDElkDiagramGen + import spinal.schema.elk.HDElkDiagramGen // With Verilog output HDElkDiagramGen(SpinalVerilog(new MyToplevel))