Neurons without incoming synapses that are on a path from an input neuron are not properly handled in the generated network SystemVerilog file. This causes signals to go to an undetermined state (symbolized by the dreaded X in Vivado's sim). For example, an output neuron with no incoming synapses is declared by logic signed [NET_CHARGE_WIDTH-1:0] neur_95_inp [0:-1]; and neur_95_inp is not assigned anywhere (as there is no input to the neuron). In this case, the neur_95_inp array should be of size 1 (i.e. neur_95_inp[0:0]), and the only array value should be directly connected to logic value 0.
Neurons without incoming synapses that are on a path from an input neuron are not properly handled in the generated network SystemVerilog file. This causes signals to go to an undetermined state (symbolized by the dreaded
Xin Vivado's sim). For example, an output neuron with no incoming synapses is declared bylogic signed [NET_CHARGE_WIDTH-1:0] neur_95_inp [0:-1];andneur_95_inpis not assigned anywhere (as there is no input to the neuron). In this case, theneur_95_inparray should be of size 1 (i.e.neur_95_inp[0:0]), and the only array value should be directly connected to logic value 0.