From 88fa9bb0a4447f48a2e76ddeeff7276e29c90bac Mon Sep 17 00:00:00 2001 From: JayPankajPatel Date: Mon, 11 May 2026 01:50:01 -0700 Subject: [PATCH] Fix bit_width calculation for ascending bus ranges in writeBusDcls std::abs(from - to + 1) gives the wrong result when from < to (ascending ranges, e.g. [0:10]): abs(0 - 10 + 1) = 9 instead of 11. Moving +1 outside abs fixes both ascending and descending ranges: ascending [0:10]: abs(0 - 10) + 1 = 11 (correct) descending [10:0]: abs(10 - 0) + 1 = 11 (correct) Fixes #360 --- liberty/LibertyWriter.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/liberty/LibertyWriter.cc b/liberty/LibertyWriter.cc index ab8b8177..695b2ccb 100644 --- a/liberty/LibertyWriter.cc +++ b/liberty/LibertyWriter.cc @@ -275,7 +275,7 @@ LibertyWriter::writeBusDcls() sta::print(stream_, " type (\"{}\") {{\n", dcl->name()); sta::print(stream_, " base_type : array;\n"); sta::print(stream_, " data_type : bit;\n"); - sta::print(stream_, " bit_width : {};\n", std::abs(dcl->from() - dcl->to() + 1)); + sta::print(stream_, " bit_width : {};\n", std::abs(dcl->from() - dcl->to()) + 1); sta::print(stream_, " bit_from : {};\n", dcl->from()); sta::print(stream_, " bit_to : {};\n", dcl->to()); sta::print(stream_, " }}\n");