Multiple writes clarification

[PixelDust22]

simple_vulkan_synchronization/thsvs_simpler_vulkan_synchronization.h

Lines 936 to 937 in a4c7ede

	// Asserts that the access is a read, else it's a write and it should appear on its own.
	assert(prevAccess < THSVS_END_OF_READ_ACCESS || thBarrier.prevAccessCount == 1);

Currently we assert that pPrevAccesses and pNextAccesses can have at most one write access for each global barrier. Imagine a scenario like this:

1. RayTracing shader writes to buffer A
2. Compute shader writes to buffer B
3. Pipeline barrier
4. Compute shader reads from buffer A
5. RayTracing shader reads from buffer B

This should be a valid case, but the assertion is asking us to make it "appear on its own."
However, we only take one global memory barrier parameter in cmd_pipeline_barrier:

simple_vulkan_synchronization/thsvs_simpler_vulkan_synchronization.h

Line 1197 in a4c7ede

uint32_t memoryBarrierCount = (pGlobalBarrier != NULL) ? 1 : 0;

@Tobski Can you clarify what we could do in this case? Thanks.