Discovered during PR #192 (bump to f57ff99c).
Symptom
Running designs/src/coralnpu/dev/setup.sh against the new upstream produces a CoreMiniAxi.v that yosys-slang can't parse. The regex-based debug/slog strip pipeline (perl + sed /debug/d + sed /slog/d) damages the chisel-generated Verilog structure in multiple ways:
- Orphan
if (cond) headers when sed deletes the body line but leaves the conditional header.
- Orphan
always @(...) headers when the if-body was the sole content of the always block.
- Orphan
else clauses when an else if (debug_cond) middle clause of an if-else-if chain gets its if header sed-stripped.
fpnew_top SV struct literals ('{Width: 32, EnableVectors: 1'b0, ...}) — yosys-slang can't parse these. Same root cause as the floonoc v0.8.x Zfbfmin/fpnew issue.
I added several iterations of orphan-detection regexes to dev/setup.sh on the PR branch — each one surfaced a new structural break — and then disabled the strip entirely as a final test. Even with no strip, the raw sv2v output hits the fpnew_top struct literal at L25716.
What's working
The CoreMiniAxi.v committed on main (built from the old 7731fd6e pin) synthesizes cleanly with current yosys-slang. So the existing cached _final is real, not stale-cache.
What needs to happen
- Rewrite
dev/setup.sh strip logic with a real Verilog-aware approach (slang AST walk, or run the strip earlier on .sv before sv2v expansion).
- Resolve the fpnew SV struct literal issue (either via yosys-slang patch, sv2v flag, or local pre-processing).
Until both are addressed, the upstream pin can advance but the regenerated RTL won't match it.
Related
Discovered during PR #192 (bump to
f57ff99c).Symptom
Running
designs/src/coralnpu/dev/setup.shagainst the new upstream produces aCoreMiniAxi.vthat yosys-slang can't parse. The regex-based debug/slog strip pipeline (perl +sed /debug/d+sed /slog/d) damages the chisel-generated Verilog structure in multiple ways:if (cond)headers when sed deletes the body line but leaves the conditional header.always @(...)headers when the if-body was the sole content of the always block.elseclauses when anelse if (debug_cond)middle clause of an if-else-if chain gets itsifheader sed-stripped.fpnew_topSV struct literals ('{Width: 32, EnableVectors: 1'b0, ...}) — yosys-slang can't parse these. Same root cause as the floonoc v0.8.x Zfbfmin/fpnew issue.I added several iterations of orphan-detection regexes to
dev/setup.shon the PR branch — each one surfaced a new structural break — and then disabled the strip entirely as a final test. Even with no strip, the raw sv2v output hits thefpnew_topstruct literal at L25716.What's working
The CoreMiniAxi.v committed on
main(built from the old7731fd6epin) synthesizes cleanly with current yosys-slang. So the existing cached_finalis real, not stale-cache.What needs to happen
dev/setup.shstrip logic with a real Verilog-aware approach (slang AST walk, or run the strip earlier on.svbefore sv2v expansion).Until both are addressed, the upstream pin can advance but the regenerated RTL won't match it.
Related
enableFloat=True(always on for the AXI build) actively use fpnew.