Summary
On the 2026-06 toolchain upgrade, vortex-asap7 reaches 6_final but setup WNS regressed −56 ps → −135 ps (Fmax 0.87 → 0.81 GHz on the 1100 ps clock). Netlist essentially unchanged (211 921 vs 214 803 logic cells, −1.3 %).
Root cause
The worst path runs from a dcache fakeram_128x256 macro output through the cache response-queue logic to a capture flop — an SRAM-read-bound, single-cycle path. Flow knobs (util/density/halo) can't shorten the SRAM's intrinsic access delay.
Scope
Needs a pipeline/clock change — out of scope. The design was already setup-negative pre-upgrade (−56 ps); area/power within ~1.4 %. See designs/src/vortex/DECISIONS.md (asap7). Related: vortex n45/sky cell-growth issue (separate). Part of PR #195.
Summary
On the 2026-06 toolchain upgrade, vortex-asap7 reaches
6_finalbut setup WNS regressed −56 ps → −135 ps (Fmax 0.87 → 0.81 GHz on the 1100 ps clock). Netlist essentially unchanged (211 921 vs 214 803 logic cells, −1.3 %).Root cause
The worst path runs from a dcache
fakeram_128x256macro output through the cache response-queue logic to a capture flop — an SRAM-read-bound, single-cycle path. Flow knobs (util/density/halo) can't shorten the SRAM's intrinsic access delay.Scope
Needs a pipeline/clock change — out of scope. The design was already setup-negative pre-upgrade (−56 ps); area/power within ~1.4 %. See
designs/src/vortex/DECISIONS.md(asap7). Related: vortex n45/sky cell-growth issue (separate). Part of PR #195.