Possible example of structure:
import chisel3._
trait KvTransferControlIOParams {
val numberOfBuffers: Int
}
trait KvTransferControlIO extends KvTransferControlIOParams {
val command = Input(UInt(2.W))
val stop = Input(Bool())
val bufferInputSelect = Input(UInt(log2Ceil(numberOfBuffers).W))
val busy = Output(Bool())
}
trait KvTransferIOParams {
val busWidth: Int
val numberOfBuffers: Int
}
trait KvTransferIO extends KvTransferIOParams {
val data = Output(UInt(busWidth.W))
// Define other IO signals related to KvTransferIO here
}
class MyModule(params: KvTransferControlIOParams with KvTransferIOParams) extends Module {
val io = IO(new Bundle with KvTransferControlIO with KvTransferIO {
val numberOfBuffers = params.numberOfBuffers
val busWidth = params.busWidth
})
// Module logic goes here, you can use io.command, io.stop, io.bufferInputSelect, io.busy, io.data, etc.
}
val numberOfBuffers = 4 // Example number of buffers
val busWidth = 32 // Example bus width
val myModuleInstance = Module(new MyModule(new KvTransferControlIOParams {
val numberOfBuffers: Int = numberOfBuffers
} with KvTransferIOParams {
val busWidth: Int = busWidth
val numberOfBuffers: Int = numberOfBuffers
}))
Possible example of structure: