No SystemVerilog support for add_from_compile_order_file in vivado.py

[LarsAsplund]

This issue was moved from VUnit/vunit#796.

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There is no support for SystemVerilog files when using the add_from_compile_order_file function. It currently only support VHDL, Verilog and Verilog Headers. Currently it fails on an assert if a SystemVerilog file type exist in the generated compile_order.txt file.

Support can be added by changing:

vunit/vivado/vivado.py

from:
30    with_dependency_scan = []
31    for library_name, file_name in compile_order:
32        is_verilog = file_name.endswith(".v") or file_name.endswith(".vp")

to:
30    with_dependency_scan = []
31    for library_name, file_name in compile_order:
32        is_verilog = file_name.endswith(".v") or file_name.endswith(".vp") or file_name.endswith(".sv")
and

vunit/vivado/vivado.py

from:
91        for line in ifile.readlines():
92            library_name, file_type, file_name = line.strip().split(",", 2)
93            assert file_type in ("Verilog", "VHDL", "Verilog Header")
94            libraries.add(library_name)

to:
91        for line in ifile.readlines():
92            library_name, file_type, file_name = line.strip().split(",", 2)
93            assert file_type in ("Verilog", "VHDL", "Verilog Header",  "SystemVerilog")
94            libraries.add(library_name)

[rpatel3001]

Memory Initialization Files are also not currently supported. I am currently using a pre_config hook to copy them into simulator_output_path but it would be handy for vunit-vivado to do so automatically.