From 0358e211befceeba9ee2a7f153b738c74e4dec7c Mon Sep 17 00:00:00 2001 From: Peter Findlay Date: Tue, 11 Aug 2026 12:12:14 +0200 Subject: [PATCH] updating SYSTEM_VERILOG_EXTENSIONS to include .svh --- vunit/source_file.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vunit/source_file.py b/vunit/source_file.py index 3653262c4..17a185757 100644 --- a/vunit/source_file.py +++ b/vunit/source_file.py @@ -348,7 +348,7 @@ def add_to_library(self, library): # lower case representation of supported extensions VHDL_EXTENSIONS = (".vhd", ".vhdl", ".vho") VERILOG_EXTENSIONS = (".v", ".vp", ".vams", ".vo") -SYSTEM_VERILOG_EXTENSIONS = (".sv", ".svp") +SYSTEM_VERILOG_EXTENSIONS = (".sv", ".svh", ".svp") VERILOG_FILE_TYPES = ("verilog", "systemverilog") FILE_TYPES = ("vhdl",) + VERILOG_FILE_TYPES