From 49afce30f121d35b7f3409c45ff51bdf680c996b Mon Sep 17 00:00:00 2001 From: comex Date: Tue, 14 May 2024 13:57:49 -0700 Subject: [PATCH] neon_intrinsics.cpp: add some unimplemented f32 scalar encodings Add f32 cases mirroring the f64 ones. Caveat: This is far from comprehensive. It's just a set of instructions I happened to bump into in the binary I'm reverse engineering. Also, it would be nice if FNEG generated a standard negation instruction instead of an intrinsic, but I didn't try to implement that. --- arch/arm64/neon_intrinsics.cpp | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/neon_intrinsics.cpp b/arch/arm64/neon_intrinsics.cpp index 037fc1ae1c..d31bc2d6e3 100644 --- a/arch/arm64/neon_intrinsics.cpp +++ b/arch/arm64/neon_intrinsics.cpp @@ -15828,6 +15828,12 @@ bool NeonGetLowLevelILForInstruction( add_input_reg(inputs, il, instr.operands[2]); add_output_reg(outputs, il, instr.operands[0]); break; + case ENC_FMAX_S_FLOATDP2: + intrin_id = ARM64_INTRIN_VMAX_F32; // FMAX Sd,Sn,Sm + add_input_reg(inputs, il, instr.operands[1]); + add_input_reg(inputs, il, instr.operands[2]); + add_output_reg(outputs, il, instr.operands[0]); + break; case ENC_FMAX_H_FLOATDP2: intrin_id = ARM64_INTRIN_VMAXH_F16; // FMAX Hd,Hn,Hm add_input_reg(inputs, il, instr.operands[1]); @@ -15932,6 +15938,12 @@ bool NeonGetLowLevelILForInstruction( add_input_reg(inputs, il, instr.operands[2]); add_output_reg(outputs, il, instr.operands[0]); break; + case ENC_FMIN_S_FLOATDP2: + intrin_id = ARM64_INTRIN_VMIN_F32; // FMIN Sd,Sn,Sm + add_input_reg(inputs, il, instr.operands[1]); + add_input_reg(inputs, il, instr.operands[2]); + add_output_reg(outputs, il, instr.operands[0]); + break; case ENC_FMIN_H_FLOATDP2: intrin_id = ARM64_INTRIN_VMINH_F16; // FMIN Hd,Hn,Hm add_input_reg(inputs, il, instr.operands[1]); @@ -16322,6 +16334,11 @@ bool NeonGetLowLevelILForInstruction( add_input_reg(inputs, il, instr.operands[1]); add_output_reg(outputs, il, instr.operands[0]); break; + case ENC_FNEG_S_FLOATDP1: + intrin_id = ARM64_INTRIN_VNEG_F32; // FNEG Sd,Sn + add_input_reg(inputs, il, instr.operands[1]); + add_output_reg(outputs, il, instr.operands[0]); + break; case ENC_FNEG_H_FLOATDP1: intrin_id = ARM64_INTRIN_VNEGH_F16; // FNEG Hd,Hn add_input_reg(inputs, il, instr.operands[1]); @@ -16664,6 +16681,11 @@ bool NeonGetLowLevelILForInstruction( add_input_reg(inputs, il, instr.operands[1]); add_output_reg(outputs, il, instr.operands[0]); break; + case ENC_FSQRT_S_FLOATDP1: + intrin_id = ARM64_INTRIN_VSQRT_F32; // FSQRT Sd,Sn + add_input_reg(inputs, il, instr.operands[1]); + add_output_reg(outputs, il, instr.operands[0]); + break; case ENC_FSQRT_H_FLOATDP1: intrin_id = ARM64_INTRIN_VSQRTH_F16; // FSQRT Hd,Hn add_input_reg(inputs, il, instr.operands[1]);