From 8d08499daa8a8fd372c164d16135a99c8a74e2b3 Mon Sep 17 00:00:00 2001 From: Jean-Michel Deva <185384874+jeanmicheldeva@users.noreply.github.com> Date: Wed, 30 Oct 2024 18:00:42 +0100 Subject: [PATCH] RISC-V JALR: Handle cases where `rd`==`rs1`, and `rd`!=`zero` --- arch/riscv/src/lib.rs | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/riscv/src/lib.rs b/arch/riscv/src/lib.rs index aaeed66d2f..837e2b286c 100644 --- a/arch/riscv/src/lib.rs +++ b/arch/riscv/src/lib.rs @@ -711,6 +711,8 @@ impl architecture::Architecture fo }; res.add_branch(branch_type, None); + } else { + res.add_branch(BranchInfo::Unresolved, None); } } Op::Beq(ref b) @@ -1225,13 +1227,25 @@ impl architecture::Architecture fo (0, _, _) => il.jump(target).append(), // indirect jump (_, _, _) => { // indirect jump with storage of next address to non-`ra` register - il.set_reg( - max_width, - Register::from(rd), - il.const_ptr(addr.wrapping_add(inst_len)), - ) - .append(); - il.jump(target).append(); + if rd.id() == rs1.id() { + let tmp: llil::Register> = llil::Register::Temp(0); + il.set_reg(max_width, tmp, target).append(); + il.set_reg( + max_width, + Register::from(rd), + il.const_ptr(addr.wrapping_add(inst_len)), + ) + .append(); + il.jump(tmp).append(); + } else { + il.set_reg( + max_width, + Register::from(rd), + il.const_ptr(addr.wrapping_add(inst_len)), + ) + .append(); + il.jump(target).append(); + } } } }