From ac9f4b3d1672c705ce1f7f984c8729e284235b56 Mon Sep 17 00:00:00 2001 From: Ugochukwu Mmaduekwe Date: Wed, 8 Jul 2026 18:07:10 +0100 Subject: [PATCH] Prefix shared SIMD include scaffolding with Hlp to avoid CryptoLib collisions The SIMD prologue/save-restore scaffolding (Include\Simd\Common) and the CPUID/XGETBV probes (Include\Simd\CpuFeatures) are copied into both this library and CryptoLib4Pascal and have diverged (they branch on HASHLIB_* vs CRYPTOLIB_* defines). Exposed under identical names on both packages' include search path, they trip Lazarus "Duplicate file" warnings and let FPC's include resolution bind against the wrong library's copy. Rename the 24 shared files (Common x86_64/i386/aarch64 + CpuFeatures) with an Hlp prefix so no basename is shared with CryptoLib, updating the {$I} references and their comment mentions. The CpuIdQuery/XGetBvQuery procedures keep their names; only the include files are renamed. Paths stay .pas-relative, so the -Fi depth anchor still resolves and Delphi is unaffected. --- HashLib/src/Checksum/HlpAdler32Dispatch.pas | 12 +++++----- HashLib/src/Checksum/HlpCRCDispatch.pas | 24 +++++++++---------- HashLib/src/Crypto/HlpBlake2BDispatch.pas | 8 +++---- HashLib/src/Crypto/HlpBlake2SDispatch.pas | 8 +++---- HashLib/src/Crypto/HlpBlake3Dispatch.pas | 16 ++++++------- HashLib/src/Crypto/HlpSHA1Dispatch.pas | 10 ++++---- HashLib/src/Crypto/HlpSHA2_256Dispatch.pas | 10 ++++---- HashLib/src/Crypto/HlpSHA2_512Dispatch.pas | 8 +++---- HashLib/src/Crypto/HlpSHA3Dispatch.pas | 8 +++---- HashLib/src/Hash64/HlpXXHash3Dispatch.pas | 24 +++++++++---------- .../Simd/Adler32/Adler32BlocksSse2_i386.inc | 2 +- .../Simd/Adler32/Adler32BlocksSse2_x86_64.inc | 4 ++-- .../Simd/Adler32/Adler32BlocksSsse3_i386.inc | 2 +- .../Adler32/Adler32BlocksSsse3_x86_64.inc | 4 ++-- .../Argon2/Argon2FillBlockAvx2_x86_64.inc | 4 ++-- .../Simd/Argon2/Argon2FillBlockSse2_i386.inc | 2 +- .../Argon2/Argon2FillBlockSse2_x86_64.inc | 4 ++-- .../Blake2B/Blake2BCompressNeon_aarch64.inc | 4 ++-- .../Simd/Blake2B/Blake2BCompressSse2_i386.inc | 2 +- .../Blake2B/Blake2BCompressSse2_x86_64.inc | 4 ++-- .../Blake2S/Blake2SCompressAvx2_x86_64.inc | 4 ++-- .../Simd/Blake2S/Blake2SCompressSse2_i386.inc | 2 +- .../Blake2S/Blake2SCompressSse2_x86_64.inc | 4 ++-- .../Simd/Blake3/Blake3CompressAvx2_x86_64.inc | 4 ++-- .../Simd/Blake3/Blake3CompressSse2_i386.inc | 2 +- .../Simd/Blake3/Blake3CompressSse2_x86_64.inc | 4 ++-- .../Simd/Blake3/Blake3Hash4Neon_aarch64.inc | 4 ++-- .../Simd/Blake3/Blake3Hash4Sse2_i386.inc | 2 +- .../Simd/Blake3/Blake3Hash4Sse2_x86_64.inc | 6 ++--- .../Simd/Blake3/Blake3Hash8Avx2_x86_64.inc | 6 ++--- .../Simd/CRC/CRCFoldForwardPclmul_x86_64.inc | 6 ++--- .../Simd/CRC/CRCFoldForwardSse2_i386.inc | 2 +- .../Simd/CRC/CRCFoldForwardSse2_x86_64.inc | 2 +- .../Simd/CRC/CRCFoldForwardVpclmul_x86_64.inc | 6 ++--- .../Simd/CRC/CRCFoldReflected32Sse2_i386.inc | 2 +- .../CRC/CRCFoldReflected32Sse2_x86_64.inc | 2 +- .../CRC/CRCFoldReflectedPclmul_x86_64.inc | 6 ++--- .../Simd/CRC/CRCFoldReflectedSse2_i386.inc | 2 +- .../Simd/CRC/CRCFoldReflectedSse2_x86_64.inc | 2 +- .../CRC/CRCFoldReflectedVpclmul_x86_64.inc | 6 ++--- ... => HlpSimdNonVolatileRestore_aarch64.inc} | 4 ++-- ...c => HlpSimdNonVolatileRestore_x86_64.inc} | 4 ++-- ...inc => HlpSimdNonVolatileSave_aarch64.inc} | 2 +- ....inc => HlpSimdNonVolatileSave_x86_64.inc} | 2 +- ...ch64.inc => HlpSimdProc1Begin_aarch64.inc} | 2 +- ...in_i386.inc => HlpSimdProc1Begin_i386.inc} | 2 +- ...86_64.inc => HlpSimdProc1Begin_x86_64.inc} | 2 +- ...ch64.inc => HlpSimdProc2Begin_aarch64.inc} | 2 +- ...in_i386.inc => HlpSimdProc2Begin_i386.inc} | 2 +- ...86_64.inc => HlpSimdProc2Begin_x86_64.inc} | 2 +- ...ch64.inc => HlpSimdProc3Begin_aarch64.inc} | 2 +- ...in_i386.inc => HlpSimdProc3Begin_i386.inc} | 2 +- ...86_64.inc => HlpSimdProc3Begin_x86_64.inc} | 2 +- ...ch64.inc => HlpSimdProc4Begin_aarch64.inc} | 2 +- ...in_i386.inc => HlpSimdProc4Begin_i386.inc} | 2 +- ...86_64.inc => HlpSimdProc4Begin_x86_64.inc} | 2 +- ...ch64.inc => HlpSimdProc5Begin_aarch64.inc} | 2 +- ...in_i386.inc => HlpSimdProc5Begin_i386.inc} | 2 +- ...86_64.inc => HlpSimdProc5Begin_x86_64.inc} | 2 +- ...ch64.inc => HlpSimdProc6Begin_aarch64.inc} | 2 +- ...in_i386.inc => HlpSimdProc6Begin_i386.inc} | 2 +- ...86_64.inc => HlpSimdProc6Begin_x86_64.inc} | 2 +- .../{CpuIdQuery.inc => HlpCpuIdQuery.inc} | 0 .../{XGetBvQuery.inc => HlpXGetBvQuery.inc} | 0 .../Simd/SHA1/SHA1CompressAvx2_x86_64.inc | 8 +++---- .../Simd/SHA1/SHA1CompressShaNi_x86_64.inc | 8 +++---- .../Simd/SHA1/SHA1CompressSse2_i386.inc | 4 ++-- .../Simd/SHA1/SHA1CompressSse2_x86_64.inc | 8 +++---- .../Simd/SHA256/SHA256CompressAvx2_x86_64.inc | 8 +++---- .../SHA256/SHA256CompressShaNi_x86_64.inc | 8 +++---- .../Simd/SHA256/SHA256CompressSse2_i386.inc | 4 ++-- .../Simd/SHA256/SHA256CompressSse2_x86_64.inc | 8 +++---- .../SHA3/KeccakF1600Avx2Absorb_x86_64.inc | 6 ++--- .../Simd/SHA3/KeccakF1600Avx2_x86_64.inc | 4 ++-- .../KeccakF1600CryptoExtAbsorb_aarch64.inc | 4 ++-- .../SHA3/KeccakF1600CryptoExt_aarch64.inc | 4 ++-- .../Simd/SHA512/SHA512CompressAvx2_x86_64.inc | 8 +++---- .../Simd/SHA512/SHA512CompressSse2_i386.inc | 4 ++-- .../Simd/SHA512/SHA512CompressSse2_x86_64.inc | 8 +++---- .../Simd/Scrypt/ScryptSalsa8Sse2_i386.inc | 2 +- .../Include/Simd/XXH3/XXH3Acc512Sse2_i386.inc | 2 +- .../Simd/XXH3/XXH3InitSecretSse2_i386.inc | 2 +- .../Simd/XXH3/XXH3ScrambleSse2_i386.inc | 2 +- HashLib/src/KDF/HlpArgon2Dispatch.pas | 8 +++---- HashLib/src/KDF/HlpScryptDispatch.pas | 8 +++---- HashLib/src/Utils/HlpX86SimdFeatures.pas | 4 ++-- 86 files changed, 202 insertions(+), 202 deletions(-) rename HashLib/src/Include/Simd/Common/{SimdNonVolatileRestore_aarch64.inc => HlpSimdNonVolatileRestore_aarch64.inc} (74%) rename HashLib/src/Include/Simd/Common/{SimdNonVolatileRestore_x86_64.inc => HlpSimdNonVolatileRestore_x86_64.inc} (79%) rename HashLib/src/Include/Simd/Common/{SimdNonVolatileSave_aarch64.inc => HlpSimdNonVolatileSave_aarch64.inc} (93%) rename HashLib/src/Include/Simd/Common/{SimdNonVolatileSave_x86_64.inc => HlpSimdNonVolatileSave_x86_64.inc} (93%) rename HashLib/src/Include/Simd/Common/{SimdProc1Begin_aarch64.inc => HlpSimdProc1Begin_aarch64.inc} (91%) rename HashLib/src/Include/Simd/Common/{SimdProc1Begin_i386.inc => HlpSimdProc1Begin_i386.inc} (90%) rename HashLib/src/Include/Simd/Common/{SimdProc1Begin_x86_64.inc => HlpSimdProc1Begin_x86_64.inc} (91%) rename HashLib/src/Include/Simd/Common/{SimdProc2Begin_aarch64.inc => HlpSimdProc2Begin_aarch64.inc} (92%) rename HashLib/src/Include/Simd/Common/{SimdProc2Begin_i386.inc => HlpSimdProc2Begin_i386.inc} (91%) rename HashLib/src/Include/Simd/Common/{SimdProc2Begin_x86_64.inc => HlpSimdProc2Begin_x86_64.inc} (91%) rename HashLib/src/Include/Simd/Common/{SimdProc3Begin_aarch64.inc => HlpSimdProc3Begin_aarch64.inc} (92%) rename HashLib/src/Include/Simd/Common/{SimdProc3Begin_i386.inc => HlpSimdProc3Begin_i386.inc} (92%) rename HashLib/src/Include/Simd/Common/{SimdProc3Begin_x86_64.inc => HlpSimdProc3Begin_x86_64.inc} (93%) rename HashLib/src/Include/Simd/Common/{SimdProc4Begin_aarch64.inc => HlpSimdProc4Begin_aarch64.inc} (93%) rename HashLib/src/Include/Simd/Common/{SimdProc4Begin_i386.inc => HlpSimdProc4Begin_i386.inc} (95%) rename HashLib/src/Include/Simd/Common/{SimdProc4Begin_x86_64.inc => HlpSimdProc4Begin_x86_64.inc} (93%) rename HashLib/src/Include/Simd/Common/{SimdProc5Begin_aarch64.inc => HlpSimdProc5Begin_aarch64.inc} (94%) rename HashLib/src/Include/Simd/Common/{SimdProc5Begin_i386.inc => HlpSimdProc5Begin_i386.inc} (96%) rename HashLib/src/Include/Simd/Common/{SimdProc5Begin_x86_64.inc => HlpSimdProc5Begin_x86_64.inc} (94%) rename HashLib/src/Include/Simd/Common/{SimdProc6Begin_aarch64.inc => HlpSimdProc6Begin_aarch64.inc} (95%) rename HashLib/src/Include/Simd/Common/{SimdProc6Begin_i386.inc => HlpSimdProc6Begin_i386.inc} (97%) rename HashLib/src/Include/Simd/Common/{SimdProc6Begin_x86_64.inc => HlpSimdProc6Begin_x86_64.inc} (95%) rename HashLib/src/Include/Simd/CpuFeatures/{CpuIdQuery.inc => HlpCpuIdQuery.inc} (100%) rename HashLib/src/Include/Simd/CpuFeatures/{XGetBvQuery.inc => HlpXGetBvQuery.inc} (100%) diff --git a/HashLib/src/Checksum/HlpAdler32Dispatch.pas b/HashLib/src/Checksum/HlpAdler32Dispatch.pas index 0ff4915e..ad92822c 100644 --- a/HashLib/src/Checksum/HlpAdler32Dispatch.pas +++ b/HashLib/src/Checksum/HlpAdler32Dispatch.pas @@ -125,13 +125,13 @@ procedure Adler32_Update_Simd(AData: PByte; ALength: UInt32; ASums: Pointer; procedure Adler32_ProcessBlocks_Sse2(AData: PByte; ANumBlocks: UInt32; ASums, AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\Adler32\Adler32BlocksSse2_i386.inc} end; procedure Adler32_ProcessBlocks_Ssse3(AData: PByte; ANumBlocks: UInt32; ASums, AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\Adler32\Adler32BlocksSsse3_i386.inc} end; @@ -141,19 +141,19 @@ procedure Adler32_ProcessBlocks_Ssse3(AData: PByte; ANumBlocks: UInt32; procedure Adler32_ProcessBlocks_Sse2(AData: PByte; ANumBlocks: UInt32; ASums, AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Adler32\Adler32BlocksSse2_x86_64.inc} end; procedure Adler32_ProcessBlocks_Ssse3(AData: PByte; ANumBlocks: UInt32; ASums, AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Adler32\Adler32BlocksSsse3_x86_64.inc} end; procedure Adler32_ProcessBlocks_Avx2(AData: PByte; ANumBlocks: UInt32; ASums, AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Adler32\Adler32BlocksAvx2_x86_64.inc} end; @@ -189,7 +189,7 @@ procedure Adler32_Update_Ssse3(AData: PByte; ALength: UInt32; ASums: Pointer); procedure Adler32_ProcessBlocks_Neon(AData: PByte; ANumBlocks: UInt32; ASums, AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_aarch64.inc} {$I ..\Include\Simd\Adler32\Adler32BlocksNeon_aarch64.inc} end; diff --git a/HashLib/src/Checksum/HlpCRCDispatch.pas b/HashLib/src/Checksum/HlpCRCDispatch.pas index d58e79e5..edd6e6d9 100644 --- a/HashLib/src/Checksum/HlpCRCDispatch.pas +++ b/HashLib/src/Checksum/HlpCRCDispatch.pas @@ -361,19 +361,19 @@ procedure CRC_UpdateViaBitSerial(AData: PByte; ADataLength, AIndex: Int32; function CRC_Fold_Reflected_Sse2(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\CRC\CRCFoldReflectedSse2_x86_64.inc} end; function CRC_Fold_Forward_Sse2(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\CRC\CRCFoldForwardSse2_x86_64.inc} end; function CRC_Fold_Reflected32_Sse2(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\CRC\CRCFoldReflected32Sse2_x86_64.inc} end; @@ -383,19 +383,19 @@ function CRC_Fold_Reflected32_Sse2(AData: PByte; ALength: UInt32; function CRC_Fold_Reflected_Sse2(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\CRC\CRCFoldReflectedSse2_i386.inc} end; function CRC_Fold_Forward_Sse2(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\CRC\CRCFoldForwardSse2_i386.inc} end; function CRC_Fold_Reflected32_Sse2(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\CRC\CRCFoldReflected32Sse2_i386.inc} end; @@ -426,25 +426,25 @@ function CRC_Fold_Reflected32_Sse2(AData: PByte; ALength: UInt32; function CRC_Fold_Reflected_Pclmul(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\CRC\CRCFoldReflectedPclmul_x86_64.inc} end; function CRC_Fold_Reflected_Vpclmul(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\CRC\CRCFoldReflectedVpclmul_x86_64.inc} end; function CRC_Fold_Forward_Pclmul(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\CRC\CRCFoldForwardPclmul_x86_64.inc} end; function CRC_Fold_Forward_Vpclmul(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\CRC\CRCFoldForwardVpclmul_x86_64.inc} end; @@ -454,13 +454,13 @@ function CRC_Fold_Forward_Vpclmul(AData: PByte; ALength: UInt32; function CRC_Fold_Reflected_Pmull(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_aarch64.inc} {$I ..\Include\Simd\CRC\CRCFoldReflectedPmull_aarch64.inc} end; function CRC_Fold_Forward_Pmull(AData: PByte; ALength: UInt32; AState: Pointer; AConstants: Pointer): UInt64; - {$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_aarch64.inc} {$I ..\Include\Simd\CRC\CRCFoldForwardPmull_aarch64.inc} end; diff --git a/HashLib/src/Crypto/HlpBlake2BDispatch.pas b/HashLib/src/Crypto/HlpBlake2BDispatch.pas index d3bd0817..29c2dbc3 100644 --- a/HashLib/src/Crypto/HlpBlake2BDispatch.pas +++ b/HashLib/src/Crypto/HlpBlake2BDispatch.pas @@ -107,7 +107,7 @@ procedure Blake2B_Compress_Scalar(AState, AMsg, ACounterFlags, AIV: Pointer); {$IFDEF HASHLIB_I386_ASM} procedure Blake2B_Compress_Sse2(AState, AMsg, ACounterFlags, AIV: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\Blake2B\Blake2BCompressSse2_i386.inc} end; @@ -116,12 +116,12 @@ procedure Blake2B_Compress_Sse2(AState, AMsg, ACounterFlags, AIV: Pointer); {$IFDEF HASHLIB_X86_64_ASM} procedure Blake2B_Compress_Sse2(AState, AMsg, ACounterFlags, AIV: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Blake2B\Blake2BCompressSse2_x86_64.inc} end; procedure Blake2B_Compress_Avx2(AState, AMsg, ACounterFlags, AIV: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Blake2B\Blake2BCompressAvx2_x86_64.inc} end; @@ -130,7 +130,7 @@ procedure Blake2B_Compress_Avx2(AState, AMsg, ACounterFlags, AIV: Pointer); {$IFDEF HASHLIB_AARCH64_ASM} procedure Blake2B_Compress_Neon(AState, AMsg, ACounterFlags, AIV: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_aarch64.inc} {$I ..\Include\Simd\Blake2B\Blake2BCompressNeon_aarch64.inc} end; diff --git a/HashLib/src/Crypto/HlpBlake2SDispatch.pas b/HashLib/src/Crypto/HlpBlake2SDispatch.pas index 2eb3f85c..4afb7f89 100644 --- a/HashLib/src/Crypto/HlpBlake2SDispatch.pas +++ b/HashLib/src/Crypto/HlpBlake2SDispatch.pas @@ -105,7 +105,7 @@ procedure Blake2S_Compress_Scalar(AState, AMsg, ACounterFlags, AIV: Pointer); {$IFDEF HASHLIB_I386_ASM} procedure Blake2S_Compress_Sse2(AState, AMsg, ACounterFlags, AIV: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\Blake2S\Blake2SCompressSse2_i386.inc} end; @@ -114,12 +114,12 @@ procedure Blake2S_Compress_Sse2(AState, AMsg, ACounterFlags, AIV: Pointer); {$IFDEF HASHLIB_X86_64_ASM} procedure Blake2S_Compress_Sse2(AState, AMsg, ACounterFlags, AIV: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Blake2S\Blake2SCompressSse2_x86_64.inc} end; procedure Blake2S_Compress_Avx2(AState, AMsg, ACounterFlags, AIV: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Blake2S\Blake2SCompressAvx2_x86_64.inc} end; @@ -128,7 +128,7 @@ procedure Blake2S_Compress_Avx2(AState, AMsg, ACounterFlags, AIV: Pointer); {$IFDEF HASHLIB_AARCH64_ASM} procedure Blake2S_Compress_Neon(AState, AMsg, ACounterFlags, AIV: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_aarch64.inc} {$I ..\Include\Simd\Blake2S\Blake2SCompressNeon_aarch64.inc} end; diff --git a/HashLib/src/Crypto/HlpBlake3Dispatch.pas b/HashLib/src/Crypto/HlpBlake3Dispatch.pas index d41ab3f2..a065a7d4 100644 --- a/HashLib/src/Crypto/HlpBlake3Dispatch.pas +++ b/HashLib/src/Crypto/HlpBlake3Dispatch.pas @@ -621,13 +621,13 @@ procedure Blake3_HashMany_Scalar(AInput, AKey, AOut: Pointer; {$IFDEF HASHLIB_I386_ASM} procedure Blake3_Compress_Sse2(AState, AMsg, ACV, ACounterFlags: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\Blake3\Blake3CompressSse2_i386.inc} end; procedure Blake3_Hash4_Sse2(AInput, AKey, AOut: Pointer; ANumChunks: Int32; ACounter: UInt64; AFlags: UInt32); - {$I ..\Include\Simd\Common\SimdProc6Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc6Begin_i386.inc} {$I ..\Include\Simd\Blake3\Blake3Hash4Sse2_i386.inc} end; @@ -636,24 +636,24 @@ procedure Blake3_Hash4_Sse2(AInput, AKey, AOut: Pointer; {$IFDEF HASHLIB_X86_64_ASM} procedure Blake3_Compress_Sse2(AState, AMsg, ACV, ACounterFlags: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Blake3\Blake3CompressSse2_x86_64.inc} end; procedure Blake3_Compress_Avx2(AState, AMsg, ACV, ACounterFlags: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Blake3\Blake3CompressAvx2_x86_64.inc} end; procedure Blake3_Hash4_Sse2(AInput, AKey, AOut: Pointer; ANumChunks: Int32; ACounter: UInt64; AFlags: UInt32); - {$I ..\Include\Simd\Common\SimdProc6Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc6Begin_x86_64.inc} {$I ..\Include\Simd\Blake3\Blake3Hash4Sse2_x86_64.inc} end; procedure Blake3_Hash8_Avx2(AInput, AKey, AOut: Pointer; ANumChunks: Int32; ACounter: UInt64; AFlags: UInt32); - {$I ..\Include\Simd\Common\SimdProc6Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc6Begin_x86_64.inc} {$I ..\Include\Simd\Blake3\Blake3Hash8Avx2_x86_64.inc} end; @@ -710,13 +710,13 @@ procedure Blake3_HashMany_Avx2(AInput, AKey, AOut: Pointer; {$IFDEF HASHLIB_AARCH64_ASM} procedure Blake3_Compress_Neon(AState, AMsg, ACV, ACounterFlags: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_aarch64.inc} {$I ..\Include\Simd\Blake3\Blake3CompressNeon_aarch64.inc} end; procedure Blake3_Hash4_Neon(AInput, AKey, AOut: Pointer; ANumChunks: Int32; ACounter: UInt64; AFlags: UInt32); - {$I ..\Include\Simd\Common\SimdProc6Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc6Begin_aarch64.inc} {$I ..\Include\Simd\Blake3\Blake3Hash4Neon_aarch64.inc} end; diff --git a/HashLib/src/Crypto/HlpSHA1Dispatch.pas b/HashLib/src/Crypto/HlpSHA1Dispatch.pas index c2bd0816..0c8da7ad 100644 --- a/HashLib/src/Crypto/HlpSHA1Dispatch.pas +++ b/HashLib/src/Crypto/HlpSHA1Dispatch.pas @@ -144,7 +144,7 @@ procedure SHA1_Compress_Scalar(AState, AData: Pointer; ANumBlocks: UInt32); procedure SHA1_Compress_Sse2(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\SHA1\SHA1CompressSse2_i386.inc} end; @@ -159,7 +159,7 @@ procedure SHA1_Compress_Sse2_Wrap(AState, AData: Pointer; ANumBlocks: UInt32); procedure SHA1_Compress_ShaNi(AState, AData: Pointer; ANumBlocks: UInt32; AConstants, AMask: Pointer); - {$I ..\Include\Simd\Common\SimdProc5Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc5Begin_x86_64.inc} {$I ..\Include\Simd\SHA1\SHA1CompressShaNi_x86_64.inc} end; @@ -170,7 +170,7 @@ procedure SHA1_Compress_ShaNi_Wrap(AState, AData: Pointer; ANumBlocks: UInt32); procedure SHA1_Compress_Sse2(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\SHA1\SHA1CompressSse2_x86_64.inc} end; @@ -181,7 +181,7 @@ procedure SHA1_Compress_Sse2_Wrap(AState, AData: Pointer; ANumBlocks: UInt32); procedure SHA1_Compress_Avx2(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\SHA1\SHA1CompressAvx2_x86_64.inc} end; @@ -196,7 +196,7 @@ procedure SHA1_Compress_Avx2_Wrap(AState, AData: Pointer; ANumBlocks: UInt32); procedure SHA1_Compress_CryptoExt(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_aarch64.inc} {$I ..\Include\Simd\SHA1\SHA1CompressCryptoExt_aarch64.inc} end; diff --git a/HashLib/src/Crypto/HlpSHA2_256Dispatch.pas b/HashLib/src/Crypto/HlpSHA2_256Dispatch.pas index 63fe3aa2..55c5463a 100644 --- a/HashLib/src/Crypto/HlpSHA2_256Dispatch.pas +++ b/HashLib/src/Crypto/HlpSHA2_256Dispatch.pas @@ -164,7 +164,7 @@ procedure SHA256_Compress_Scalar(AState, AData: Pointer; ANumBlocks: UInt32); procedure SHA256_Compress_Sse2(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\SHA256\SHA256CompressSse2_i386.inc} end; @@ -174,7 +174,7 @@ procedure SHA256_Compress_Sse2(AState, AData: Pointer; ANumBlocks: UInt32; procedure SHA256_Compress_ShaNi(AState, AData: Pointer; ANumBlocks: UInt32; AConstants, AMask: Pointer); - {$I ..\Include\Simd\Common\SimdProc5Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc5Begin_x86_64.inc} {$I ..\Include\Simd\SHA256\SHA256CompressShaNi_x86_64.inc} end; @@ -185,13 +185,13 @@ procedure SHA256_Compress_ShaNi_Wrap(AState, AData: Pointer; ANumBlocks: UInt32) procedure SHA256_Compress_Sse2(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\SHA256\SHA256CompressSse2_x86_64.inc} end; procedure SHA256_Compress_Avx2(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\SHA256\SHA256CompressAvx2_x86_64.inc} end; @@ -215,7 +215,7 @@ procedure SHA256_Compress_Sse2_Wrap(AState, AData: Pointer; ANumBlocks: UInt32); procedure SHA256_Compress_CryptoExt(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_aarch64.inc} {$I ..\Include\Simd\SHA256\SHA256CompressCryptoExt_aarch64.inc} end; diff --git a/HashLib/src/Crypto/HlpSHA2_512Dispatch.pas b/HashLib/src/Crypto/HlpSHA2_512Dispatch.pas index bd5677d9..dfec4e61 100644 --- a/HashLib/src/Crypto/HlpSHA2_512Dispatch.pas +++ b/HashLib/src/Crypto/HlpSHA2_512Dispatch.pas @@ -223,7 +223,7 @@ procedure SHA512_Compress_Scalar(AState, AData: Pointer; ANumBlocks: UInt32); procedure SHA512_Compress_Sse2(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\SHA512\SHA512CompressSse2_i386.inc} end; @@ -233,13 +233,13 @@ procedure SHA512_Compress_Sse2(AState, AData: Pointer; ANumBlocks: UInt32; procedure SHA512_Compress_Sse2(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\SHA512\SHA512CompressSse2_x86_64.inc} end; procedure SHA512_Compress_Avx2(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\SHA512\SHA512CompressAvx2_x86_64.inc} end; @@ -267,7 +267,7 @@ procedure SHA512_Compress_Sse2_Wrap(AState, AData: Pointer; ANumBlocks: UInt32); procedure SHA512_Compress_CryptoExt(AState, AData: Pointer; ANumBlocks: UInt32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_aarch64.inc} {$I ..\Include\Simd\SHA512\SHA512CompressCryptoExt_aarch64.inc} end; diff --git a/HashLib/src/Crypto/HlpSHA3Dispatch.pas b/HashLib/src/Crypto/HlpSHA3Dispatch.pas index 6e53e62d..6381e481 100644 --- a/HashLib/src/Crypto/HlpSHA3Dispatch.pas +++ b/HashLib/src/Crypto/HlpSHA3Dispatch.pas @@ -469,7 +469,7 @@ procedure KeccakF1600_Absorb_Scalar(AState: Pointer; AData: PByte; ); procedure KeccakF1600_Avx2(AState: Pointer; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc2Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc2Begin_x86_64.inc} {$I ..\Include\Simd\SHA3\KeccakF1600Avx2_x86_64.inc} end; @@ -480,7 +480,7 @@ procedure KeccakF1600_Avx2_Wrap(AState: Pointer); procedure KeccakF1600_Avx2_Absorb(AState: Pointer; AData: PByte; ABlockCount: Int32; ABlockSize: Int32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc5Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc5Begin_x86_64.inc} {$I ..\Include\Simd\SHA3\KeccakF1600Avx2Absorb_x86_64.inc} end; @@ -499,7 +499,7 @@ procedure KeccakF1600_Avx2_Absorb_Wrap(AState: Pointer; AData: PByte; // 64-bit iota with ld1r), so no separate packed constant block is needed. procedure KeccakF1600_CryptoExt(AState: Pointer; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc2Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc2Begin_aarch64.inc} {$I ..\Include\Simd\SHA3\KeccakF1600CryptoExt_aarch64.inc} end; @@ -510,7 +510,7 @@ procedure KeccakF1600_CryptoExt_Wrap(AState: Pointer); procedure KeccakF1600_CryptoExt_Absorb(AState: Pointer; AData: PByte; ABlockCount: Int32; ABlockSize: Int32; AConstants: Pointer); - {$I ..\Include\Simd\Common\SimdProc5Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc5Begin_aarch64.inc} {$I ..\Include\Simd\SHA3\KeccakF1600CryptoExtAbsorb_aarch64.inc} end; diff --git a/HashLib/src/Hash64/HlpXXHash3Dispatch.pas b/HashLib/src/Hash64/HlpXXHash3Dispatch.pas index 53796315..608f9c2e 100644 --- a/HashLib/src/Hash64/HlpXXHash3Dispatch.pas +++ b/HashLib/src/Hash64/HlpXXHash3Dispatch.pas @@ -118,18 +118,18 @@ procedure XXH3_Accumulate_Scalar(AAcc: Pointer; AInput: Pointer; procedure XXH3_Accumulate512_Sse2(AAcc: Pointer; AInput: Pointer; ASecret: Pointer); - {$I ..\Include\Simd\Common\SimdProc3Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc3Begin_i386.inc} {$I ..\Include\Simd\XXH3\XXH3Acc512Sse2_i386.inc} end; procedure XXH3_ScrambleAcc_Sse2(AAcc: Pointer; ASecret: Pointer); - {$I ..\Include\Simd\Common\SimdProc2Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc2Begin_i386.inc} {$I ..\Include\Simd\XXH3\XXH3ScrambleSse2_i386.inc} end; procedure XXH3_InitSecret_Sse2(ACustomSecret: Pointer; ADefaultSecret: Pointer; ASeed: UInt64); - {$I ..\Include\Simd\Common\SimdProc3Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc3Begin_i386.inc} {$I ..\Include\Simd\XXH3\XXH3InitSecretSse2_i386.inc} end; @@ -139,35 +139,35 @@ procedure XXH3_InitSecret_Sse2(ACustomSecret: Pointer; procedure XXH3_Accumulate512_Sse2(AAcc: Pointer; AInput: Pointer; ASecret: Pointer); - {$I ..\Include\Simd\Common\SimdProc3Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc3Begin_x86_64.inc} {$I ..\Include\Simd\XXH3\XXH3Acc512Sse2_x86_64.inc} end; procedure XXH3_ScrambleAcc_Sse2(AAcc: Pointer; ASecret: Pointer); - {$I ..\Include\Simd\Common\SimdProc2Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc2Begin_x86_64.inc} {$I ..\Include\Simd\XXH3\XXH3ScrambleSse2_x86_64.inc} end; procedure XXH3_InitSecret_Sse2(ACustomSecret: Pointer; ADefaultSecret: Pointer; ASeed: UInt64); - {$I ..\Include\Simd\Common\SimdProc3Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc3Begin_x86_64.inc} {$I ..\Include\Simd\XXH3\XXH3InitSecretSse2_x86_64.inc} end; procedure XXH3_Accumulate512_Avx2(AAcc: Pointer; AInput: Pointer; ASecret: Pointer); - {$I ..\Include\Simd\Common\SimdProc3Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc3Begin_x86_64.inc} {$I ..\Include\Simd\XXH3\XXH3Acc512Avx2_x86_64.inc} end; procedure XXH3_ScrambleAcc_Avx2(AAcc: Pointer; ASecret: Pointer); - {$I ..\Include\Simd\Common\SimdProc2Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc2Begin_x86_64.inc} {$I ..\Include\Simd\XXH3\XXH3ScrambleAvx2_x86_64.inc} end; procedure XXH3_InitSecret_Avx2(ACustomSecret: Pointer; ADefaultSecret: Pointer; ASeed: UInt64); - {$I ..\Include\Simd\Common\SimdProc3Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc3Begin_x86_64.inc} {$I ..\Include\Simd\XXH3\XXH3InitSecretAvx2_x86_64.inc} end; @@ -214,18 +214,18 @@ procedure XXH3_Accumulate_Avx2(AAcc: Pointer; AInput: Pointer; procedure XXH3_Accumulate512_Neon(AAcc: Pointer; AInput: Pointer; ASecret: Pointer); - {$I ..\Include\Simd\Common\SimdProc3Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc3Begin_aarch64.inc} {$I ..\Include\Simd\XXH3\XXH3Acc512Neon_aarch64.inc} end; procedure XXH3_ScrambleAcc_Neon(AAcc: Pointer; ASecret: Pointer); - {$I ..\Include\Simd\Common\SimdProc2Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc2Begin_aarch64.inc} {$I ..\Include\Simd\XXH3\XXH3ScrambleNeon_aarch64.inc} end; procedure XXH3_InitSecret_Neon(ACustomSecret: Pointer; ADefaultSecret: Pointer; ASeed: UInt64); - {$I ..\Include\Simd\Common\SimdProc3Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc3Begin_aarch64.inc} {$I ..\Include\Simd\XXH3\XXH3InitSecretNeon_aarch64.inc} end; diff --git a/HashLib/src/Include/Simd/Adler32/Adler32BlocksSse2_i386.inc b/HashLib/src/Include/Simd/Adler32/Adler32BlocksSse2_i386.inc index 6e9b1dab..7691003c 100644 --- a/HashLib/src/Include/Simd/Adler32/Adler32BlocksSse2_i386.inc +++ b/HashLib/src/Include/Simd/Adler32/Adler32BlocksSse2_i386.inc @@ -1,5 +1,5 @@ // SSE2 implementation of Adler-32 block processing (IA-32). -// After SimdProc4Begin_i386: ebx = AData, esi = ANumBlocks, edi = ASums, eax = AConstants. +// After HlpSimdProc4Begin_i386: ebx = AData, esi = ANumBlocks, edi = ASums, eax = AConstants. // ASums: [SumA: UInt32, SumB: UInt32]. Constants: [weights_hi: 16B, weights_lo: 16B] (32 bytes). // Processes num_blocks x 32-byte blocks; caller applies mod 65521. // diff --git a/HashLib/src/Include/Simd/Adler32/Adler32BlocksSse2_x86_64.inc b/HashLib/src/Include/Simd/Adler32/Adler32BlocksSse2_x86_64.inc index c9814ff2..62605209 100644 --- a/HashLib/src/Include/Simd/Adler32/Adler32BlocksSse2_x86_64.inc +++ b/HashLib/src/Include/Simd/Adler32/Adler32BlocksSse2_x86_64.inc @@ -10,7 +10,7 @@ // weight bytes via pmaddwd (SSE2), producing the same 4 x i32 weighted // sums per 16-byte half that pmaddubsw + pmaddwd would yield. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} // Zero constant pxor xmm3, xmm3 @@ -98,4 +98,4 @@ mov dword [r8], eax mov dword [r8 + 4], r10d - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Adler32/Adler32BlocksSsse3_i386.inc b/HashLib/src/Include/Simd/Adler32/Adler32BlocksSsse3_i386.inc index f176d2ba..2fc07bd5 100644 --- a/HashLib/src/Include/Simd/Adler32/Adler32BlocksSsse3_i386.inc +++ b/HashLib/src/Include/Simd/Adler32/Adler32BlocksSsse3_i386.inc @@ -1,5 +1,5 @@ // SSSE3 Adler-32 block processing (IA-32). -// After SimdProc4Begin_i386: ebx = AData, esi = ANumBlocks, edi = ASums, eax = AConstants. +// After HlpSimdProc4Begin_i386: ebx = AData, esi = ANumBlocks, edi = ASums, eax = AConstants. // Constants: [weights_hi: 16B, weights_lo: 16B, ones_16: 16B] (48 bytes; same as x64 SSSE3). // No xmm8 on IA-32: psadbw uses a copy in xmm5 (first half) or xmm4 (second half), then reload weights. // Caller applies mod 65521. diff --git a/HashLib/src/Include/Simd/Adler32/Adler32BlocksSsse3_x86_64.inc b/HashLib/src/Include/Simd/Adler32/Adler32BlocksSsse3_x86_64.inc index 0cd70153..a277affe 100644 --- a/HashLib/src/Include/Simd/Adler32/Adler32BlocksSsse3_x86_64.inc +++ b/HashLib/src/Include/Simd/Adler32/Adler32BlocksSsse3_x86_64.inc @@ -5,7 +5,7 @@ // Processes num_blocks x 32-byte blocks. Does NOT apply mod 65521 (caller does it). // Uses xmm0-xmm8; xmm6-xmm8 are MS x64 non-volatile (saved/restored). - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} // Load constants movdqu xmm4, oword [r9] @@ -76,4 +76,4 @@ mov dword [r8], eax mov dword [r8 + 4], r10d - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Argon2/Argon2FillBlockAvx2_x86_64.inc b/HashLib/src/Include/Simd/Argon2/Argon2FillBlockAvx2_x86_64.inc index bf0d523f..4bff0fe2 100644 --- a/HashLib/src/Include/Simd/Argon2/Argon2FillBlockAvx2_x86_64.inc +++ b/HashLib/src/Include/Simd/Argon2/Argon2FillBlockAvx2_x86_64.inc @@ -15,7 +15,7 @@ // Diagonalize/Undiagonalize via vpermq (cross-lane 64-bit permute). // vzeroupper required before return. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} sub rsp, 2056 @@ -326,4 +326,4 @@ add rsp, 2056 db $C5, $F8, $77 // vzeroupper - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Argon2/Argon2FillBlockSse2_i386.inc b/HashLib/src/Include/Simd/Argon2/Argon2FillBlockSse2_i386.inc index dac97712..ee688b4c 100644 --- a/HashLib/src/Include/Simd/Argon2/Argon2FillBlockSse2_i386.inc +++ b/HashLib/src/Include/Simd/Argon2/Argon2FillBlockSse2_i386.inc @@ -1,5 +1,5 @@ // SSE2 implementation of Argon2 FillBlock. -// IA-32: after SimdProc4Begin_i386 — ebx, esi, edi, eax = Left, Right, Current, WithXor +// IA-32: after HlpSimdProc4Begin_i386 — ebx, esi, edi, eax = Left, Right, Current, WithXor // (parallel to MS x64 ABI: rcx, rdx, r8, r9). // Each pointer addresses 128 QWords (1024 bytes). // Uses xmm0–xmm7; xmm6–xmm7 saved/restored defensively (volatile on i386). diff --git a/HashLib/src/Include/Simd/Argon2/Argon2FillBlockSse2_x86_64.inc b/HashLib/src/Include/Simd/Argon2/Argon2FillBlockSse2_x86_64.inc index d307e4a8..4d696bee 100644 --- a/HashLib/src/Include/Simd/Argon2/Argon2FillBlockSse2_x86_64.inc +++ b/HashLib/src/Include/Simd/Argon2/Argon2FillBlockSse2_x86_64.inc @@ -16,7 +16,7 @@ // register pairs. Right-rotates require a 3-movdqa swap since shufpd // naturally places results in the opposite register for that direction. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} sub rsp, 2056 @@ -555,4 +555,4 @@ @epilogue: add rsp, 2056 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Blake2B/Blake2BCompressNeon_aarch64.inc b/HashLib/src/Include/Simd/Blake2B/Blake2BCompressNeon_aarch64.inc index 808aec25..c72e55d7 100644 --- a/HashLib/src/Include/Simd/Blake2B/Blake2BCompressNeon_aarch64.inc +++ b/HashLib/src/Include/Simd/Blake2B/Blake2BCompressNeon_aarch64.inc @@ -15,7 +15,7 @@ // v21-v23 = rotate / diagonalize temps (b1 gather uses v23) // u64 ror-by-32 uses rev64.4s (vrev64q_u32), not rev64.16b. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_aarch64.inc} .long 0xad400400 // ldp q0, q1, [x0] .long 0xad410c02 // ldp q2, q3, [x0, #32] @@ -1395,5 +1395,5 @@ .long 0xad000400 // stp q0, q1, [x0] .long 0xad010c02 // stp q2, q3, [x0, #32] - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_aarch64.inc} ret diff --git a/HashLib/src/Include/Simd/Blake2B/Blake2BCompressSse2_i386.inc b/HashLib/src/Include/Simd/Blake2B/Blake2BCompressSse2_i386.inc index d9f87d67..18b29deb 100644 --- a/HashLib/src/Include/Simd/Blake2B/Blake2BCompressSse2_i386.inc +++ b/HashLib/src/Include/Simd/Blake2B/Blake2BCompressSse2_i386.inc @@ -1,5 +1,5 @@ // SSE2 implementation of BLAKE2b compress (fully unrolled 12 rounds). -// IA-32: after SimdProc4Begin_i386 — ebx = state, esi = msg, edi = counter+flags, eax = IV +// IA-32: after HlpSimdProc4Begin_i386 — ebx = state, esi = msg, edi = counter+flags, eax = IV // (parallel to MS x64 ABI: rcx, rdx, r8, r9). // XMM8+ from x64 eliminated: xmm4 scratch + stack, xmm0/1 for diagonal work; uses xmm0–xmm7. // Non-volatile xmm6–xmm7 saved in stack frame (sub esp, 128). diff --git a/HashLib/src/Include/Simd/Blake2B/Blake2BCompressSse2_x86_64.inc b/HashLib/src/Include/Simd/Blake2B/Blake2BCompressSse2_x86_64.inc index 8f70d6c8..861c04fc 100644 --- a/HashLib/src/Include/Simd/Blake2B/Blake2BCompressSse2_x86_64.inc +++ b/HashLib/src/Include/Simd/Blake2B/Blake2BCompressSse2_x86_64.inc @@ -5,7 +5,7 @@ // xmm4-5 = row3 (v8-11), xmm6-7 = row4 (v12-15), xmm8-9 = temps. // Reference: BLAKE2/BLAKE2 sse/ by Samuel Neves. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} // Initialize working vector movdqu xmm0, oword [rcx] @@ -1989,4 +1989,4 @@ movdqu oword [rcx + $20], xmm2 movdqu oword [rcx + $30], xmm3 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Blake2S/Blake2SCompressAvx2_x86_64.inc b/HashLib/src/Include/Simd/Blake2S/Blake2SCompressAvx2_x86_64.inc index 7caa8209..55b78f74 100644 --- a/HashLib/src/Include/Simd/Blake2S/Blake2SCompressAvx2_x86_64.inc +++ b/HashLib/src/Include/Simd/Blake2S/Blake2SCompressAvx2_x86_64.inc @@ -7,7 +7,7 @@ // AVX/AVX2 instructions are db-encoded for broad assembler compatibility. // Reference: BLAKE2/BLAKE2 sse/ by Samuel Neves. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} // Initialize working vector db $C5, $FA, $6F, $01 // vmovdqu xmm0, oword [rcx] @@ -993,4 +993,4 @@ db $C5, $F8, $77 // vzeroupper - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Blake2S/Blake2SCompressSse2_i386.inc b/HashLib/src/Include/Simd/Blake2S/Blake2SCompressSse2_i386.inc index 4cc6e3be..17c0c76d 100644 --- a/HashLib/src/Include/Simd/Blake2S/Blake2SCompressSse2_i386.inc +++ b/HashLib/src/Include/Simd/Blake2S/Blake2SCompressSse2_i386.inc @@ -1,5 +1,5 @@ // SSE2 implementation of BLAKE2s compress (fully unrolled 10 rounds). -// IA-32: after SimdProc4Begin_i386 — ebx = state, esi = msg, edi = counter+flags, eax = IV +// IA-32: after HlpSimdProc4Begin_i386 — ebx = state, esi = msg, edi = counter+flags, eax = IV // (parallel to MS x64 ABI: rcx, rdx, r8, r9). // Uses xmm0–xmm6; xmm6 saved/restored defensively (volatile on i386). // Register map: xmm0 = a (v0-3), xmm1 = b (v4-7), xmm2 = c (v8-11), xmm3 = d (v12-15), diff --git a/HashLib/src/Include/Simd/Blake2S/Blake2SCompressSse2_x86_64.inc b/HashLib/src/Include/Simd/Blake2S/Blake2SCompressSse2_x86_64.inc index bf3debf7..6fdfaf6c 100644 --- a/HashLib/src/Include/Simd/Blake2S/Blake2SCompressSse2_x86_64.inc +++ b/HashLib/src/Include/Simd/Blake2S/Blake2SCompressSse2_x86_64.inc @@ -8,7 +8,7 @@ // Message loads via movd + punpcklqdq + shufps. // Reference: BLAKE2/BLAKE2 sse/ by Samuel Neves. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} // Initialize working vector movdqu xmm0, oword [rcx] @@ -1072,4 +1072,4 @@ movdqu oword [rcx], xmm0 movdqu oword [rcx + $10], xmm1 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Blake3/Blake3CompressAvx2_x86_64.inc b/HashLib/src/Include/Simd/Blake3/Blake3CompressAvx2_x86_64.inc index e41cd896..c2c1023f 100644 --- a/HashLib/src/Include/Simd/Blake3/Blake3CompressAvx2_x86_64.inc +++ b/HashLib/src/Include/Simd/Blake3/Blake3CompressAvx2_x86_64.inc @@ -16,7 +16,7 @@ // [rsp + 96..111]: IV staging area (loaded into xmm2) // [rsp +112..119]: padding - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} sub rsp, 24 @@ -584,4 +584,4 @@ add rsp, 24 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Blake3/Blake3CompressSse2_i386.inc b/HashLib/src/Include/Simd/Blake3/Blake3CompressSse2_i386.inc index 2f543428..0fee3c4b 100644 --- a/HashLib/src/Include/Simd/Blake3/Blake3CompressSse2_i386.inc +++ b/HashLib/src/Include/Simd/Blake3/Blake3CompressSse2_i386.inc @@ -1,6 +1,6 @@ // SSE2 implementation of BLAKE3 compress (7 rounds with register-based message scheduling). // Reference: BLAKE3-team/BLAKE3 official SSE2 implementation (blake3_sse2_x86-64_windows_msvc.asm). -// IA-32: after SimdProc4Begin_i386 — ebx = state, esi = msg, edi = CV, eax = counterflags ptr +// IA-32: after HlpSimdProc4Begin_i386 — ebx = state, esi = msg, edi = CV, eax = counterflags ptr // (parallel to MS x64 ABI: rcx, rdx, r8, r9). // Register map: xmm0 = a (v0-3), xmm1 = b (v4-7), xmm2 = c (v8-11), xmm3 = d (v12-15); // IA-32 uses xmm0–7 only — high-XMM temps from x64 are folded into xmm0/1/2 + stack spill; diff --git a/HashLib/src/Include/Simd/Blake3/Blake3CompressSse2_x86_64.inc b/HashLib/src/Include/Simd/Blake3/Blake3CompressSse2_x86_64.inc index 8aaecdb2..396ecb5d 100644 --- a/HashLib/src/Include/Simd/Blake3/Blake3CompressSse2_x86_64.inc +++ b/HashLib/src/Include/Simd/Blake3/Blake3CompressSse2_x86_64.inc @@ -16,7 +16,7 @@ // [rsp + 96..111]: IV staging area (loaded into xmm2) // [rsp +112..119]: padding - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} sub rsp, 24 @@ -637,4 +637,4 @@ add rsp, 24 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Blake3/Blake3Hash4Neon_aarch64.inc b/HashLib/src/Include/Simd/Blake3/Blake3Hash4Neon_aarch64.inc index 36d8eff0..7907c57f 100644 --- a/HashLib/src/Include/Simd/Blake3/Blake3Hash4Neon_aarch64.inc +++ b/HashLib/src/Include/Simd/Blake3/Blake3Hash4Neon_aarch64.inc @@ -18,7 +18,7 @@ // [sp, #320..568] saved CV, counter vectors, IV, block len, AOut ptr, flags // Message transpose uses trn1/trn2 + zip1/zip2 (equivalent to SSE punpck / neon transpose_vecs_128). - {$I ..\Include\Simd\Common\SimdNonVolatileSave_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_aarch64.inc} stp x19, x20, [sp, #-16]! sub sp, sp, #720 @@ -1711,5 +1711,5 @@ add sp, sp, #720 ldp x19, x20, [sp], #16 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_aarch64.inc} ret diff --git a/HashLib/src/Include/Simd/Blake3/Blake3Hash4Sse2_i386.inc b/HashLib/src/Include/Simd/Blake3/Blake3Hash4Sse2_i386.inc index a2721f0f..22904198 100644 --- a/HashLib/src/Include/Simd/Blake3/Blake3Hash4Sse2_i386.inc +++ b/HashLib/src/Include/Simd/Blake3/Blake3Hash4Sse2_i386.inc @@ -4,7 +4,7 @@ // each chunk is processed one at a time with the inline SSE2 compress kernel. // Register map during rounds: xmm0=a(v0-3), xmm1=b(v4-7), xmm2=c(v8-11), xmm3=d(v12-15); // xmm4={m0,m2,m4,m6}, xmm5={m1,m3,m5,m7}, xmm6={m14,m8,m10,m12}, xmm7={m15,m9,m11,m13}. -// After SimdProc6Begin_i386: ebx=P1 (input), esi=P2 (key), edi=P3 (out), eax=P4 (num chunks), +// After HlpSimdProc6Begin_i386: ebx=P1 (input), esi=P2 (key), edi=P3 (out), eax=P4 (num chunks), // ecx=P5_lo, edx=P5_hi (chunk counter). Prologue pushed ebx/esi/edi — epilogue pops them. // Block index (0..15) is kept at [esp+$90] so ebp is never used as a temp (frame-friendly). // Stack layout (148 bytes, esp-relative after sub esp,148): diff --git a/HashLib/src/Include/Simd/Blake3/Blake3Hash4Sse2_x86_64.inc b/HashLib/src/Include/Simd/Blake3/Blake3Hash4Sse2_x86_64.inc index 24a548eb..f17b54fc 100644 --- a/HashLib/src/Include/Simd/Blake3/Blake3Hash4Sse2_x86_64.inc +++ b/HashLib/src/Include/Simd/Blake3/Blake3Hash4Sse2_x86_64.inc @@ -3,7 +3,7 @@ // Each XMM register holds the same 32-bit word from 4 different chunks (inter-chunk SIMD). // 7 rounds per block fully unrolled; 16-block loop with branch for chunk start/end flags. // -// After SimdProc6Begin_x86_64.inc: +// After HlpSimdProc6Begin_x86_64.inc: // rcx = AInput, rdx = AKey, r8 = AOut, // r9 = ANumChunks, r10 = ACounter, r11 = AFlags // @@ -18,7 +18,7 @@ push rbx push rbp - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} sub rsp, 584 @@ -1828,7 +1828,7 @@ add rsp, 584 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} pop rbp pop rbx diff --git a/HashLib/src/Include/Simd/Blake3/Blake3Hash8Avx2_x86_64.inc b/HashLib/src/Include/Simd/Blake3/Blake3Hash8Avx2_x86_64.inc index d57a4093..5f7060da 100644 --- a/HashLib/src/Include/Simd/Blake3/Blake3Hash8Avx2_x86_64.inc +++ b/HashLib/src/Include/Simd/Blake3/Blake3Hash8Avx2_x86_64.inc @@ -4,7 +4,7 @@ // All VEX instructions are db-encoded for broad assembler compatibility. // 7 rounds per block fully unrolled; 16-block loop with branch for chunk start/end flags. // -// After SimdProc6Begin_x86_64.inc: +// After HlpSimdProc6Begin_x86_64.inc: // rcx = AInput, rdx = AKey, r8 = AOut, // r9 = ANumChunks, r10 = ACounter, r11 = AFlags // @@ -18,7 +18,7 @@ // // MS x64 non-volatile saves: xmm6-xmm13. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} push rbx push rbp @@ -1678,4 +1678,4 @@ pop rbp pop rbx - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/CRC/CRCFoldForwardPclmul_x86_64.inc b/HashLib/src/Include/Simd/CRC/CRCFoldForwardPclmul_x86_64.inc index a72d6b15..c68debc1 100644 --- a/HashLib/src/Include/Simd/CRC/CRCFoldForwardPclmul_x86_64.inc +++ b/HashLib/src/Include/Simd/CRC/CRCFoldForwardPclmul_x86_64.inc @@ -2,7 +2,7 @@ // (MSB-first) CRCs with width 8..64. // PCLMULQDQ instructions are db-encoded for broad assembler compatibility. // -// Function signature (included after SimdProc4Begin_x86_64.inc): +// Function signature (included after HlpSimdProc4Begin_x86_64.inc): // function CRC_Fold_Forward_Pclmul(AData: PByte; ALength: UInt32; // AState: Pointer; AConstants: Pointer): UInt64; // @@ -29,7 +29,7 @@ // pshufb xmm_dst, xmm_src (SSSE3): // 66 0F 38 00 ModRM - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} // BswapMask is always needed (kept in xmm6 throughout) movdqu xmm6, dqword ptr [r9 + 64] // BswapMask @@ -195,4 +195,4 @@ // movq rax, xmm0: 66 48 0F 7E C0 db $66, $48, $0F, $7E, $C0 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/CRC/CRCFoldForwardSse2_i386.inc b/HashLib/src/Include/Simd/CRC/CRCFoldForwardSse2_i386.inc index 63f6cd8e..0f96efff 100644 --- a/HashLib/src/Include/Simd/CRC/CRCFoldForwardSse2_i386.inc +++ b/HashLib/src/Include/Simd/CRC/CRCFoldForwardSse2_i386.inc @@ -1,6 +1,6 @@ // MSB-first 64-bit CRC: 16-byte slice (IA-32; SSE2 not required — same as x64 MSB path). // x64 counterpart: CRCFoldForwardSse2_x86_64.inc. -// After SimdProc4Begin_i386: ebx = AData, esi = ALength, edi = AState, eax = Ctx. +// After HlpSimdProc4Begin_i386: ebx = AData, esi = ALength, edi = AState, eax = Ctx. // Ctx: FoldConstants.CrcBits at +80, TableRow at +96. CrcMask derived from width. // Result UInt64 in edx:eax. diff --git a/HashLib/src/Include/Simd/CRC/CRCFoldForwardSse2_x86_64.inc b/HashLib/src/Include/Simd/CRC/CRCFoldForwardSse2_x86_64.inc index 8a4e82ae..6bdbd6ba 100644 --- a/HashLib/src/Include/Simd/CRC/CRCFoldForwardSse2_x86_64.inc +++ b/HashLib/src/Include/Simd/CRC/CRCFoldForwardSse2_x86_64.inc @@ -1,6 +1,6 @@ // MSB-first 64-bit CRC: 16-byte slice (slicing-by-16) using SSE2 for load only. // IA-32 counterpart: CRCFoldForwardSse2_i386.inc. -// Signature (after SimdProc4Begin_x86_64.inc): +// Signature (after HlpSimdProc4Begin_x86_64.inc): // function CRC_Fold_Forward_Sse2(AData: PByte; ALength: UInt32; // AState: Pointer; AConstants: Pointer): UInt64; // MS x64: rcx=AData, edx=ALength, r8=AState, r9=Ctx. diff --git a/HashLib/src/Include/Simd/CRC/CRCFoldForwardVpclmul_x86_64.inc b/HashLib/src/Include/Simd/CRC/CRCFoldForwardVpclmul_x86_64.inc index 3abd489a..a00c3550 100644 --- a/HashLib/src/Include/Simd/CRC/CRCFoldForwardVpclmul_x86_64.inc +++ b/HashLib/src/Include/Simd/CRC/CRCFoldForwardVpclmul_x86_64.inc @@ -3,7 +3,7 @@ // AVX2/VPCLMULQDQ/SSSE3 instructions are db-encoded for broad assembler // compatibility. // -// Function signature (included after SimdProc4Begin_x86_64.inc): +// Function signature (included after HlpSimdProc4Begin_x86_64.inc): // function CRC_Fold_Forward_Vpclmul(AData: PByte; ALength: UInt32; // AState: Pointer; AConstants: Pointer): UInt64; // @@ -26,7 +26,7 @@ // 2-byte: C5 [R.vvvv.L.pp] // 3-byte: C4 [R.X.B.mmmmm] [W.vvvv.L.pp] - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} cmp edx, 128 jb @xmm_path @@ -240,4 +240,4 @@ // movq rax, xmm0: 66 48 0F 7E C0 db $66, $48, $0F, $7E, $C0 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/CRC/CRCFoldReflected32Sse2_i386.inc b/HashLib/src/Include/Simd/CRC/CRCFoldReflected32Sse2_i386.inc index 45ed5e7e..186f1904 100644 --- a/HashLib/src/Include/Simd/CRC/CRCFoldReflected32Sse2_i386.inc +++ b/HashLib/src/Include/Simd/CRC/CRCFoldReflected32Sse2_i386.inc @@ -1,5 +1,5 @@ // CRC32 reflected (PKZIP-style) 16-byte slice (IA-32 SSE2 + dword table XOR). -// After SimdProc4Begin_i386: ebx = AData, esi = ALength, edi = AState, eax = Ctx. +// After HlpSimdProc4Begin_i386: ebx = AData, esi = ALength, edi = AState, eax = Ctx. // Little-endian host only. PUInt32 rows at Ctx + 96. // d0 xor CRC saved at [esp+12]; d1 in edx; d2/d3 on stack. Result eax, edx=0. diff --git a/HashLib/src/Include/Simd/CRC/CRCFoldReflected32Sse2_x86_64.inc b/HashLib/src/Include/Simd/CRC/CRCFoldReflected32Sse2_x86_64.inc index fb532963..6a51c09a 100644 --- a/HashLib/src/Include/Simd/CRC/CRCFoldReflected32Sse2_x86_64.inc +++ b/HashLib/src/Include/Simd/CRC/CRCFoldReflected32Sse2_x86_64.inc @@ -1,6 +1,6 @@ // CRC32 reflected (PKZIP-style) 16-byte slice: SSE2 movdqu + dword table XOR. // Little-endian host only (x86/x64 asm reads 32-bit words directly from memory). -// Signature (after SimdProc4Begin_x86_64.inc): +// Signature (after HlpSimdProc4Begin_x86_64.inc): // function CRC_Fold_Reflected32_Sse2(AData: PByte; ALength: UInt32; // AState: Pointer; AConstants: Pointer): UInt64; // State: low UInt32 of qword at AState is the running CRC. diff --git a/HashLib/src/Include/Simd/CRC/CRCFoldReflectedPclmul_x86_64.inc b/HashLib/src/Include/Simd/CRC/CRCFoldReflectedPclmul_x86_64.inc index a4fd5acc..49a9521d 100644 --- a/HashLib/src/Include/Simd/CRC/CRCFoldReflectedPclmul_x86_64.inc +++ b/HashLib/src/Include/Simd/CRC/CRCFoldReflectedPclmul_x86_64.inc @@ -2,7 +2,7 @@ // CRCs with width 8..64. CRC-64 uses a special Barrett path for the 65-bit G. // PCLMULQDQ instructions are db-encoded for broad assembler compatibility. // -// Function signature (included after SimdProc4Begin_x86_64.inc): +// Function signature (included after HlpSimdProc4Begin_x86_64.inc): // function CRC_Fold_Reflected_Pclmul(AData: PByte; ALength: UInt32; // AState: Pointer; AConstants: Pointer): UInt64; // @@ -26,7 +26,7 @@ // xmm0=000 xmm1=001 xmm2=010 xmm3=011 xmm4=100 // xmm5=101 xmm6=110 xmm7=111 - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} // fold_1x128 is always needed (fold-by-1 loop and Barrett step 1) movdqu xmm7, dqword ptr [r9 + 16] // fold_1x128 @@ -194,4 +194,4 @@ // pextrq rax, xmm0, 1: 66 48 0F 3A 16 C0 01 db $66, $48, $0F, $3A, $16, $C0, $01 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/CRC/CRCFoldReflectedSse2_i386.inc b/HashLib/src/Include/Simd/CRC/CRCFoldReflectedSse2_i386.inc index 4a15a396..e8612d10 100644 --- a/HashLib/src/Include/Simd/CRC/CRCFoldReflectedSse2_i386.inc +++ b/HashLib/src/Include/Simd/CRC/CRCFoldReflectedSse2_i386.inc @@ -1,5 +1,5 @@ // Reflected (LSB-first) 64-bit CRC: 16-byte slice (IA-32 SSE2 + GPR table XOR). -// After SimdProc4Begin_i386: ebx = AData, esi = ALength, edi = AState, eax = Ctx. +// After HlpSimdProc4Begin_i386: ebx = AData, esi = ALength, edi = AState, eax = Ctx. // TableRow[i] at Ctx + 96; each entry is a 32-bit (untyped) Pointer. // Result UInt64 in edx:eax (high:low). Preserves Delphi/FPC i386 frame via push/pop ebp. diff --git a/HashLib/src/Include/Simd/CRC/CRCFoldReflectedSse2_x86_64.inc b/HashLib/src/Include/Simd/CRC/CRCFoldReflectedSse2_x86_64.inc index d55189e9..3aa4034a 100644 --- a/HashLib/src/Include/Simd/CRC/CRCFoldReflectedSse2_x86_64.inc +++ b/HashLib/src/Include/Simd/CRC/CRCFoldReflectedSse2_x86_64.inc @@ -1,5 +1,5 @@ // Reflected (LSB-first) 64-bit CRC: 16-byte slice using SSE2 loads + GPR table XOR. -// Signature (after SimdProc4Begin_x86_64.inc): +// Signature (after HlpSimdProc4Begin_x86_64.inc): // function CRC_Fold_Reflected_Sse2(AData: PByte; ALength: UInt32; // AState: Pointer; AConstants: Pointer): UInt64; // MS x64: rcx=AData, edx=ALength, r8=AState, r9=Ctx (PCRCFoldRuntimeCtx). diff --git a/HashLib/src/Include/Simd/CRC/CRCFoldReflectedVpclmul_x86_64.inc b/HashLib/src/Include/Simd/CRC/CRCFoldReflectedVpclmul_x86_64.inc index 8bd13b9a..ea35440a 100644 --- a/HashLib/src/Include/Simd/CRC/CRCFoldReflectedVpclmul_x86_64.inc +++ b/HashLib/src/Include/Simd/CRC/CRCFoldReflectedVpclmul_x86_64.inc @@ -2,7 +2,7 @@ // CRCs with width 8..64. CRC-64 uses a special Barrett path for the 65-bit G. // AVX2/VPCLMULQDQ instructions are db-encoded for broad assembler compatibility. // -// Function signature (included after SimdProc4Begin_x86_64.inc): +// Function signature (included after HlpSimdProc4Begin_x86_64.inc): // function CRC_Fold_Reflected_Vpclmul(AData: PByte; ALength: UInt32; // AState: Pointer; AConstants: Pointer): UInt64; // @@ -25,7 +25,7 @@ // 2-byte: C5 [R.vvvv.L.pp] // 3-byte: C4 [R.X.B.mmmmm] [W.vvvv.L.pp] - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} cmp edx, 128 jb @xmm_path @@ -216,4 +216,4 @@ db $C5, $F8, $77 // vzeroupper db $C4, $E3, $F9, $16, $C0, $01 // vpextrq rax, xmm0, 1 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Common/SimdNonVolatileRestore_aarch64.inc b/HashLib/src/Include/Simd/Common/HlpSimdNonVolatileRestore_aarch64.inc similarity index 74% rename from HashLib/src/Include/Simd/Common/SimdNonVolatileRestore_aarch64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdNonVolatileRestore_aarch64.inc index b7f37aaa..4762963a 100644 --- a/HashLib/src/Include/Simd/Common/SimdNonVolatileRestore_aarch64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdNonVolatileRestore_aarch64.inc @@ -1,7 +1,7 @@ -// Shared nonvolatile-SIMD restore (AArch64). Mirror of SimdNonVolatileSave_aarch64.inc: +// Shared nonvolatile-SIMD restore (AArch64). Mirror of HlpSimdNonVolatileSave_aarch64.inc: // restores d8..d15 and frees the 64-byte save frame. Include it at the kernel's // restore point (after the last use of v8..v15, before returning), in any -// procedure that included SimdNonVolatileSave_aarch64.inc. Restoring d8..d15 +// procedure that included HlpSimdNonVolatileSave_aarch64.inc. Restoring d8..d15 // zeroes the upper halves of v8..v15, which is fine since those are caller-saved. .long 0x6d412fea // ldp d10, d11, [sp, #16] .long 0x6d4237ec // ldp d12, d13, [sp, #32] diff --git a/HashLib/src/Include/Simd/Common/SimdNonVolatileRestore_x86_64.inc b/HashLib/src/Include/Simd/Common/HlpSimdNonVolatileRestore_x86_64.inc similarity index 79% rename from HashLib/src/Include/Simd/Common/SimdNonVolatileRestore_x86_64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdNonVolatileRestore_x86_64.inc index bd4f12eb..2f548e0f 100644 --- a/HashLib/src/Include/Simd/Common/SimdNonVolatileRestore_x86_64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdNonVolatileRestore_x86_64.inc @@ -1,7 +1,7 @@ -// Shared nonvolatile-XMM restore (x86-64). Mirror of SimdNonVolatileSave_x86_64.inc: +// Shared nonvolatile-XMM restore (x86-64). Mirror of HlpSimdNonVolatileSave_x86_64.inc: // restores xmm6..xmm15 and frees the 160-byte save frame. Include it at the // kernel's restore point (after the last use of xmm6..15, and after any vzeroupper, -// before returning), in any procedure that included SimdNonVolatileSave_x86_64.inc. +// before returning), in any procedure that included HlpSimdNonVolatileSave_x86_64.inc. // Legacy movups here is safe because a ymm kernel has already issued vzeroupper, // and a VEX-128-only kernel leaves the upper halves clean. No-op on SysV x86-64. {$IFNDEF HASHLIB_SYSV_X64_ABI} diff --git a/HashLib/src/Include/Simd/Common/SimdNonVolatileSave_aarch64.inc b/HashLib/src/Include/Simd/Common/HlpSimdNonVolatileSave_aarch64.inc similarity index 93% rename from HashLib/src/Include/Simd/Common/SimdNonVolatileSave_aarch64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdNonVolatileSave_aarch64.inc index 8ea5657d..9b74d5ac 100644 --- a/HashLib/src/Include/Simd/Common/SimdNonVolatileSave_aarch64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdNonVolatileSave_aarch64.inc @@ -1,6 +1,6 @@ // Shared nonvolatile-SIMD save (AArch64). Opt-in by inclusion: a kernel that // clobbers any of v8..v15 includes this at its save point (before it first -// writes those registers), and the matching SimdNonVolatileRestore_aarch64.inc +// writes those registers), and the matching HlpSimdNonVolatileRestore_aarch64.inc // at its restore point (after the last use, before returning). Kernels that // touch only v0..v7 / v16..v31 do NOT include it. // diff --git a/HashLib/src/Include/Simd/Common/SimdNonVolatileSave_x86_64.inc b/HashLib/src/Include/Simd/Common/HlpSimdNonVolatileSave_x86_64.inc similarity index 93% rename from HashLib/src/Include/Simd/Common/SimdNonVolatileSave_x86_64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdNonVolatileSave_x86_64.inc index d7e3c44b..a3603766 100644 --- a/HashLib/src/Include/Simd/Common/SimdNonVolatileSave_x86_64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdNonVolatileSave_x86_64.inc @@ -1,6 +1,6 @@ // Shared nonvolatile-XMM save (x86-64). Opt-in by inclusion: a kernel that uses // any of xmm6..xmm15 includes this at its save point (before it first writes -// those registers), and the matching SimdNonVolatileRestore_x86_64.inc at its restore +// those registers), and the matching HlpSimdNonVolatileRestore_x86_64.inc at its restore // point (after the last use, before returning). Light kernels that touch only // xmm0..xmm5 do NOT include it. // diff --git a/HashLib/src/Include/Simd/Common/SimdProc1Begin_aarch64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc1Begin_aarch64.inc similarity index 91% rename from HashLib/src/Include/Simd/Common/SimdProc1Begin_aarch64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc1Begin_aarch64.inc index 5c0eafdd..0f6b1057 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc1Begin_aarch64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc1Begin_aarch64.inc @@ -5,7 +5,7 @@ // is needed. // Usage: // procedure MyProc(P1: Pointer); -// {$I SimdProc1Begin_aarch64.inc} +// {$I HlpSimdProc1Begin_aarch64.inc} // // ... SIMD instructions using x0 ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc1Begin_i386.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc1Begin_i386.inc similarity index 90% rename from HashLib/src/Include/Simd/Common/SimdProc1Begin_i386.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc1Begin_i386.inc index bab23984..8e2ddae6 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc1Begin_i386.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc1Begin_i386.inc @@ -3,7 +3,7 @@ // FPC and Delphi Win32 share the same i386 register convention here. // Usage: // procedure MyProc(P1: Pointer); -// {$I SimdProc1Begin_i386.inc} +// {$I HlpSimdProc1Begin_i386.inc} // // ... SIMD instructions using ebx ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc1Begin_x86_64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc1Begin_x86_64.inc similarity index 91% rename from HashLib/src/Include/Simd/Common/SimdProc1Begin_x86_64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc1Begin_x86_64.inc index c14cf0f0..b83aa27b 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc1Begin_x86_64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc1Begin_x86_64.inc @@ -3,7 +3,7 @@ // When HASHLIB_SYSV_X64_ABI is defined, remaps rdi -> rcx. // Usage: // procedure MyProc(P1: Pointer); -// {$I SimdProc1Begin_x86_64.inc} +// {$I HlpSimdProc1Begin_x86_64.inc} // // ... SIMD instructions using rcx ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc2Begin_aarch64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc2Begin_aarch64.inc similarity index 92% rename from HashLib/src/Include/Simd/Common/SimdProc2Begin_aarch64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc2Begin_aarch64.inc index d916e40c..ae32f230 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc2Begin_aarch64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc2Begin_aarch64.inc @@ -5,7 +5,7 @@ // SysV/MS variants) is needed. // Usage: // procedure MyProc(P1, P2: Pointer); -// {$I SimdProc2Begin_aarch64.inc} +// {$I HlpSimdProc2Begin_aarch64.inc} // // ... SIMD instructions using x0, x1 ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc2Begin_i386.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc2Begin_i386.inc similarity index 91% rename from HashLib/src/Include/Simd/Common/SimdProc2Begin_i386.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc2Begin_i386.inc index 68070e5f..6909baeb 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc2Begin_i386.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc2Begin_i386.inc @@ -3,7 +3,7 @@ // Callee-saved EBX, ESI - epilogue must pop ESI, EBX. // Usage: // procedure MyProc(P1, P2: Pointer); -// {$I SimdProc2Begin_i386.inc} +// {$I HlpSimdProc2Begin_i386.inc} // // ... SIMD instructions using ebx, esi ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc2Begin_x86_64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc2Begin_x86_64.inc similarity index 91% rename from HashLib/src/Include/Simd/Common/SimdProc2Begin_x86_64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc2Begin_x86_64.inc index 92418455..9614d9f7 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc2Begin_x86_64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc2Begin_x86_64.inc @@ -3,7 +3,7 @@ // When HASHLIB_SYSV_X64_ABI is defined, remaps rdi,rsi -> rcx,rdx. // Usage: // procedure MyProc(P1, P2: Pointer); -// {$I SimdProc2Begin_x86_64.inc} +// {$I HlpSimdProc2Begin_x86_64.inc} // // ... SIMD instructions using rcx, rdx ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc3Begin_aarch64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc3Begin_aarch64.inc similarity index 92% rename from HashLib/src/Include/Simd/Common/SimdProc3Begin_aarch64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc3Begin_aarch64.inc index 07bdd411..b4d73136 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc3Begin_aarch64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc3Begin_aarch64.inc @@ -5,7 +5,7 @@ // (unlike the x86 SysV/MS variants) is needed. // Usage: // procedure MyProc(P1, P2, P3: Pointer); -// {$I SimdProc3Begin_aarch64.inc} +// {$I HlpSimdProc3Begin_aarch64.inc} // // ... SIMD instructions using x0, x1, w2 ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc3Begin_i386.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc3Begin_i386.inc similarity index 92% rename from HashLib/src/Include/Simd/Common/SimdProc3Begin_i386.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc3Begin_i386.inc index 6e64d81b..aea3e114 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc3Begin_i386.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc3Begin_i386.inc @@ -3,7 +3,7 @@ // Callee-saved EBX, ESI, EDI - epilogue must pop EDI, ESI, EBX. // Usage: // procedure MyProc(P1, P2, P3: Pointer); -// {$I SimdProc3Begin_i386.inc} +// {$I HlpSimdProc3Begin_i386.inc} // // ... SIMD instructions using ebx, esi, edi ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc3Begin_x86_64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc3Begin_x86_64.inc similarity index 93% rename from HashLib/src/Include/Simd/Common/SimdProc3Begin_x86_64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc3Begin_x86_64.inc index 72a725a8..b753b215 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc3Begin_x86_64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc3Begin_x86_64.inc @@ -4,7 +4,7 @@ // Move order avoids register clobbering: save rdx before overwriting. // Usage: // procedure MyProc(P1, P2, P3: Pointer); -// {$I SimdProc3Begin_x86_64.inc} +// {$I HlpSimdProc3Begin_x86_64.inc} // // ... SIMD instructions using rcx, rdx, r8 ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc4Begin_aarch64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc4Begin_aarch64.inc similarity index 93% rename from HashLib/src/Include/Simd/Common/SimdProc4Begin_aarch64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc4Begin_aarch64.inc index 0473f8ee..ec052077 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc4Begin_aarch64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc4Begin_aarch64.inc @@ -5,7 +5,7 @@ // register remapping (unlike the x86 SysV/MS variants) is needed. // Usage: // procedure MyProc(P1, P2, P3: Pointer; P4: Pointer); -// {$I SimdProc4Begin_aarch64.inc} +// {$I HlpSimdProc4Begin_aarch64.inc} // // ... SIMD instructions using x0, x1, w2, x3 ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc4Begin_i386.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc4Begin_i386.inc similarity index 95% rename from HashLib/src/Include/Simd/Common/SimdProc4Begin_i386.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc4Begin_i386.inc index f1643b34..5ba1bb19 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc4Begin_i386.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc4Begin_i386.inc @@ -7,7 +7,7 @@ // the EBX push but before the ESI / EDI pushes (see asm). // Usage: // procedure MyProc(P1, P2, P3: Pointer; P4: Int32); -// {$I SimdProc4Begin_i386.inc} +// {$I HlpSimdProc4Begin_i386.inc} // // ... SIMD instructions using ebx, esi, edi, eax ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc4Begin_x86_64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc4Begin_x86_64.inc similarity index 93% rename from HashLib/src/Include/Simd/Common/SimdProc4Begin_x86_64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc4Begin_x86_64.inc index c40d7880..c67a8e67 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc4Begin_x86_64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc4Begin_x86_64.inc @@ -5,7 +5,7 @@ // Move order avoids register clobbering: save rcx and rdx first. // Usage: // procedure MyProc(P1, P2, P3: Pointer; P4: Int32); -// {$I SimdProc4Begin_x86_64.inc} +// {$I HlpSimdProc4Begin_x86_64.inc} // // ... SIMD instructions using rcx, rdx, r8, r9 ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc5Begin_aarch64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc5Begin_aarch64.inc similarity index 94% rename from HashLib/src/Include/Simd/Common/SimdProc5Begin_aarch64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc5Begin_aarch64.inc index 078539ef..da1fac06 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc5Begin_aarch64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc5Begin_aarch64.inc @@ -8,7 +8,7 @@ // ANumBlocks) are read through the wN view of the same register. // Usage: // procedure MyProc(P1, P2: Pointer; P3: UInt32; P4, P5: Pointer); -// {$I SimdProc5Begin_aarch64.inc} +// {$I HlpSimdProc5Begin_aarch64.inc} // // ... SIMD instructions using x0, x1, w2, x3, x4 ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc5Begin_i386.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc5Begin_i386.inc similarity index 96% rename from HashLib/src/Include/Simd/Common/SimdProc5Begin_i386.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc5Begin_i386.inc index 3b716b3f..c1d109ea 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc5Begin_i386.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc5Begin_i386.inc @@ -6,7 +6,7 @@ // Callee-saved EBX, ESI, EDI — epilogue must pop EDI, ESI, EBX. // Usage: // procedure MyProc(P1, P2: Pointer; P3, P4: Int32; P5: Pointer); -// {$I SimdProc5Begin_i386.inc} +// {$I HlpSimdProc5Begin_i386.inc} // // ... SIMD instructions using ebx, esi, edi, eax, ecx ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc5Begin_x86_64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc5Begin_x86_64.inc similarity index 94% rename from HashLib/src/Include/Simd/Common/SimdProc5Begin_x86_64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc5Begin_x86_64.inc index 82efa29f..41576237 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc5Begin_x86_64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc5Begin_x86_64.inc @@ -5,7 +5,7 @@ // On MS x64, param5 is loaded from [rsp+40] (above 32-byte shadow space + 8-byte return addr). // Usage: // procedure MyProc(P1, P2: Pointer; P3, P4: Int32; P5: Pointer); -// {$I SimdProc5Begin_x86_64.inc} +// {$I HlpSimdProc5Begin_x86_64.inc} // // ... SIMD instructions using rcx, rdx, r8, r9, r10 ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc6Begin_aarch64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc6Begin_aarch64.inc similarity index 95% rename from HashLib/src/Include/Simd/Common/SimdProc6Begin_aarch64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc6Begin_aarch64.inc index a41e9bdc..c09a2568 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc6Begin_aarch64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc6Begin_aarch64.inc @@ -9,7 +9,7 @@ // the same register. // Usage: // procedure MyProc(P1, P2, P3: Pointer; P4: Int32; P5: UInt64; P6: UInt32); -// {$I SimdProc6Begin_aarch64.inc} +// {$I HlpSimdProc6Begin_aarch64.inc} // // ... SIMD instructions using x0, x1, x2, x3, x4, x5 ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc6Begin_i386.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc6Begin_i386.inc similarity index 97% rename from HashLib/src/Include/Simd/Common/SimdProc6Begin_i386.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc6Begin_i386.inc index d578d926..229122b4 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc6Begin_i386.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc6Begin_i386.inc @@ -7,7 +7,7 @@ // Callee-saved EBX, ESI, EDI — epilogue must pop EDI, ESI, EBX; SIMD bodies may adjust ESP for locals. // Usage: // procedure MyProc(P1, P2, P3: Pointer; P4: Int32; P5: UInt64; P6: UInt32); -// {$I SimdProc6Begin_i386.inc} +// {$I HlpSimdProc6Begin_i386.inc} // // ... SIMD instructions using ebx, esi, edi, eax, ecx, edx (load param6 from stack if needed) ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/Common/SimdProc6Begin_x86_64.inc b/HashLib/src/Include/Simd/Common/HlpSimdProc6Begin_x86_64.inc similarity index 95% rename from HashLib/src/Include/Simd/Common/SimdProc6Begin_x86_64.inc rename to HashLib/src/Include/Simd/Common/HlpSimdProc6Begin_x86_64.inc index 820486b0..85902a98 100644 --- a/HashLib/src/Include/Simd/Common/SimdProc6Begin_x86_64.inc +++ b/HashLib/src/Include/Simd/Common/HlpSimdProc6Begin_x86_64.inc @@ -6,7 +6,7 @@ // On MS x64, param5/6 are loaded from [rsp+40]/[rsp+48] (above shadow space + return addr). // Usage: // procedure MyProc(P1, P2, P3: Pointer; P4: Int32; P5: UInt64; P6: UInt32); -// {$I SimdProc6Begin_x86_64.inc} +// {$I HlpSimdProc6Begin_x86_64.inc} // // ... SIMD instructions using rcx, rdx, r8, r9, r10, r11 ... // end; {$IFDEF FPC} diff --git a/HashLib/src/Include/Simd/CpuFeatures/CpuIdQuery.inc b/HashLib/src/Include/Simd/CpuFeatures/HlpCpuIdQuery.inc similarity index 100% rename from HashLib/src/Include/Simd/CpuFeatures/CpuIdQuery.inc rename to HashLib/src/Include/Simd/CpuFeatures/HlpCpuIdQuery.inc diff --git a/HashLib/src/Include/Simd/CpuFeatures/XGetBvQuery.inc b/HashLib/src/Include/Simd/CpuFeatures/HlpXGetBvQuery.inc similarity index 100% rename from HashLib/src/Include/Simd/CpuFeatures/XGetBvQuery.inc rename to HashLib/src/Include/Simd/CpuFeatures/HlpXGetBvQuery.inc diff --git a/HashLib/src/Include/Simd/SHA1/SHA1CompressAvx2_x86_64.inc b/HashLib/src/Include/Simd/SHA1/SHA1CompressAvx2_x86_64.inc index e31dab39..fbb5b201 100644 --- a/HashLib/src/Include/Simd/SHA1/SHA1CompressAvx2_x86_64.inc +++ b/HashLib/src/Include/Simd/SHA1/SHA1CompressAvx2_x86_64.inc @@ -4,16 +4,16 @@ // vector and integer units run in parallel. AVX2 and BMI (rorx/andn/shlx) // instructions are db-encoded for broad assembler compatibility (every AVX2 CPU // also provides BMI). -// Expects MS x64 ABI (after SimdProc4Begin): rcx = state ptr, rdx = data ptr, +// Expects MS x64 ABI (after HlpSimdProc4Begin): rcx = state ptr, rdx = data ptr, // r8d = numblocks, r9 = K_SHA1_Doubled ptr (the four SHA-1 round constants each // replicated across 256 bits, then the byte-swap mask and a reverse mask; see // K_SHA1_Doubled). The masks are read unaligned, so the const needs no alignment. // -// MS x64 non-volatile saves: xmm6-xmm15 via the shared SimdNonVolatileSave/Restore +// MS x64 non-volatile saves: xmm6-xmm15 via the shared HlpSimdNonVolatileSave/Restore // include (no-op on SysV); rbx, rbp, rdi, rsi, r12-r14 in the local frame; r11 // holds the caller rsp across the kernel for the unwind. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} mov r11, rsp push r9 @@ -1679,4 +1679,4 @@ mov rbx, qword [r11 - $10] lea rsp, [r11] - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/SHA1/SHA1CompressShaNi_x86_64.inc b/HashLib/src/Include/Simd/SHA1/SHA1CompressShaNi_x86_64.inc index c027009f..3f8fa1bd 100644 --- a/HashLib/src/Include/Simd/SHA1/SHA1CompressShaNi_x86_64.inc +++ b/HashLib/src/Include/Simd/SHA1/SHA1CompressShaNi_x86_64.inc @@ -7,7 +7,7 @@ // pipelined into rounds 64-79 and the data pointer is advanced branchlessly // (cmovnz). // -// Expects MS x64 ABI (after SimdProc5Begin): rcx = state ptr, rdx = data ptr, +// Expects MS x64 ABI (after HlpSimdProc5Begin): rcx = state ptr, rdx = data ptr, // r8d = numblocks, r9 = round-constant ptr (unused - sha1rnds4 has the round // constants built in), r10 = byte-swap mask ptr (16 bytes; see BSWAP32_MASK, // matching OpenSSL K_XX_XX+0xa0). @@ -31,10 +31,10 @@ // xmm8 = ABCD_SAVE // xmm9 = E_SAVE // -// MS x64 non-volatile saves: xmm6-xmm15 via the shared SimdNonVolatileSave/Restore +// MS x64 non-volatile saves: xmm6-xmm15 via the shared HlpSimdNonVolatileSave/Restore // include (no-op on SysV); the kernel itself uses only volatile GPRs (rcx/rdx/r8-r11). - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} test r8d, r8d jz @sha1ni_done @@ -203,4 +203,4 @@ @sha1ni_done: - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/SHA1/SHA1CompressSse2_i386.inc b/HashLib/src/Include/Simd/SHA1/SHA1CompressSse2_i386.inc index 8b1041f6..3cfb9fd4 100644 --- a/HashLib/src/Include/Simd/SHA1/SHA1CompressSse2_i386.inc +++ b/HashLib/src/Include/Simd/SHA1/SHA1CompressSse2_i386.inc @@ -4,9 +4,9 @@ // OpenSSL's only SSSE3-only op is the pshufb input byte-swap, emulated in SSE2 as // psrlw/psllw/por + pshuflw/pshufhw (the freed byte-swap-mask register xmm6 is the // scratch); the W-schedule uses no palignr. -// Expects (after SimdProc4Begin_i386): ebx = state, esi = data, edi = numblocks, +// Expects (after HlpSimdProc4Begin_i386): ebx = state, esi = data, edi = numblocks, // eax = doubled-K_SHA1 ptr (read at a 32-byte stride so the duplicated halves -// are skipped; see K_SHA1_Doubled). SimdProc4Begin pushes ebx/esi/edi; ebp is +// are skipped; see K_SHA1_Doubled). HlpSimdProc4Begin pushes ebx/esi/edi; ebp is // pushed here as the K pointer, then reused as the data pointer and for the // state writeback. diff --git a/HashLib/src/Include/Simd/SHA1/SHA1CompressSse2_x86_64.inc b/HashLib/src/Include/Simd/SHA1/SHA1CompressSse2_x86_64.inc index 18a4ebc0..7562a955 100644 --- a/HashLib/src/Include/Simd/SHA1/SHA1CompressSse2_x86_64.inc +++ b/HashLib/src/Include/Simd/SHA1/SHA1CompressSse2_x86_64.inc @@ -5,15 +5,15 @@ // the pshufb input byte-swap, which is emulated in SSE2 (psrlw/psllw/por + // pshuflw/pshufhw; xmm12 is a free scratch); the W-schedule uses no palignr. The // appended masks go unused - the byte-swap is computed, not shuffled. -// Expects MS x64 ABI (after SimdProc4Begin): rcx = state ptr, rdx = data ptr, +// Expects MS x64 ABI (after HlpSimdProc4Begin): rcx = state ptr, rdx = data ptr, // r8d = numblocks, r9 = doubled-K_SHA1 ptr (read 128-bit at a 32-byte stride, // r14 = K + 64, so the duplicated halves are skipped; see K_SHA1_Doubled). // -// MS x64 non-volatile saves: xmm6-xmm15 via the shared SimdNonVolatileSave/Restore +// MS x64 non-volatile saves: xmm6-xmm15 via the shared HlpSimdNonVolatileSave/Restore // include (no-op on SysV); rbx, rbp, rdi, rsi, r12-r14 in the local frame; r11 // holds the caller rsp across the kernel for the unwind. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} mov r11, rsp push r9 @@ -1228,4 +1228,4 @@ mov rbx, qword [r11 - $10] lea rsp, [r11] - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/SHA256/SHA256CompressAvx2_x86_64.inc b/HashLib/src/Include/Simd/SHA256/SHA256CompressAvx2_x86_64.inc index 5d92f891..0eb5c276 100644 --- a/HashLib/src/Include/Simd/SHA256/SHA256CompressAvx2_x86_64.inc +++ b/HashLib/src/Include/Simd/SHA256/SHA256CompressAvx2_x86_64.inc @@ -5,16 +5,16 @@ // blocks at once is what makes this faster than the single-block AVX path. AVX2 // and BMI2 (rorx/andn) instructions are db-encoded for broad assembler // compatibility (every AVX2 CPU also provides BMI2). -// Expects MS x64 ABI (after SimdProc4Begin): rcx = state ptr, rdx = data ptr, +// Expects MS x64 ABI (after HlpSimdProc4Begin): rcx = state ptr, rdx = data ptr, // r8d = numblocks, r9 = doubled-K256 ptr (each 128-bit K256 quadruple stored // twice so one table feeds both 256-bit lanes, with the byte-swap and two // message-schedule masks appended; see K256_Doubled). The masks are read // unaligned, so the Pascal const needs no special alignment. // -// MS x64 non-volatile saves: xmm6-xmm15 via the shared SimdNonVolatileSave/Restore +// MS x64 non-volatile saves: xmm6-xmm15 via the shared HlpSimdNonVolatileSave/Restore // include (no-op on SysV); rbx, rbp, rdi, rsi, r12-r15 in the local frame. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} mov rax, rsp push r9 @@ -1252,4 +1252,4 @@ lea rsp, [rsi] mov rsi, rax - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/SHA256/SHA256CompressShaNi_x86_64.inc b/HashLib/src/Include/Simd/SHA256/SHA256CompressShaNi_x86_64.inc index f8a663ef..640ed16e 100644 --- a/HashLib/src/Include/Simd/SHA256/SHA256CompressShaNi_x86_64.inc +++ b/HashLib/src/Include/Simd/SHA256/SHA256CompressShaNi_x86_64.inc @@ -5,7 +5,7 @@ // BSWAP32_MASK (a plain per-dword swap - SHA-256 consumes its words in natural // order, so no dword reversal is needed). // -// Expects MS x64 ABI (after SimdProc5Begin): rcx = state ptr, rdx = data ptr, +// Expects MS x64 ABI (after HlpSimdProc5Begin): rcx = state ptr, rdx = data ptr, // r8d = numblocks, r9 = K256 ptr (64 UInt32 round constants), r10 = byte-swap // mask ptr (16 bytes; see BSWAP32_MASK). // @@ -27,10 +27,10 @@ // xmm8 = ABEF_SAVE // xmm9 = CDGH_SAVE // -// MS x64 non-volatile saves: xmm6-xmm15 via the shared SimdNonVolatileSave/Restore +// MS x64 non-volatile saves: xmm6-xmm15 via the shared HlpSimdNonVolatileSave/Restore // include (no-op on SysV); the kernel itself uses only volatile GPRs (rcx/rdx/r8-r10). - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} test r8d, r8d jz @shani_done @@ -255,4 +255,4 @@ @shani_done: - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/SHA256/SHA256CompressSse2_i386.inc b/HashLib/src/Include/Simd/SHA256/SHA256CompressSse2_i386.inc index 2dc895d7..e994d133 100644 --- a/HashLib/src/Include/Simd/SHA256/SHA256CompressSse2_i386.inc +++ b/HashLib/src/Include/Simd/SHA256/SHA256CompressSse2_i386.inc @@ -5,9 +5,9 @@ // (IA-32 has too few GPRs to keep all eight in registers). OpenSSL's two SSSE3-only // ops are emulated in SSE2: the pshufb dword byte-swap becomes psrlw/psllw/por + // pshuflw/pshufhw, and palignr becomes psrldq/pslldq/por. -// Expects (after SimdProc4Begin_i386): ebx = state, esi = data, edi = numblocks, +// Expects (after HlpSimdProc4Begin_i386): ebx = state, esi = data, edi = numblocks, // eax = doubled-K256 ptr (read at a 32-byte stride so the duplicated halves are -// skipped; see K256_Doubled). SimdProc4Begin pushes ebx/esi/edi; ebp is pushed +// skipped; see K256_Doubled). HlpSimdProc4Begin pushes ebx/esi/edi; ebp is pushed // here as the K256 walk pointer; state loads into eax/ebx/ecx and the frame. push ebp diff --git a/HashLib/src/Include/Simd/SHA256/SHA256CompressSse2_x86_64.inc b/HashLib/src/Include/Simd/SHA256/SHA256CompressSse2_x86_64.inc index 3d4b54a6..11fcdc13 100644 --- a/HashLib/src/Include/Simd/SHA256/SHA256CompressSse2_x86_64.inc +++ b/HashLib/src/Include/Simd/SHA256/SHA256CompressSse2_x86_64.inc @@ -5,15 +5,15 @@ // SSSE3-only ops are emulated in SSE2: the pshufb dword byte-swap becomes // psrlw/psllw/por + pshuflw/pshufhw, and palignr becomes psrldq/pslldq/por // (xmm8 is a free scratch). -// Expects MS x64 ABI (after SimdProc4Begin): rcx = state ptr, rdx = data ptr, +// Expects MS x64 ABI (after HlpSimdProc4Begin): rcx = state ptr, rdx = data ptr, // r8d = numblocks, r9 = doubled-K256 ptr (read at a 32-byte stride so the // duplicated halves are skipped; see K256_Doubled). No byte-swap mask table is // needed - the swap is computed, not shuffled. // -// MS x64 non-volatile saves: xmm6-xmm15 via the shared SimdNonVolatileSave/Restore +// MS x64 non-volatile saves: xmm6-xmm15 via the shared HlpSimdNonVolatileSave/Restore // include (no-op on SysV); rbx, rbp, rdi, rsi, r12-r15 in the local frame. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} mov rax, rsp push r9 @@ -1150,4 +1150,4 @@ lea rsp, [rsi] mov rsi, rax - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/SHA3/KeccakF1600Avx2Absorb_x86_64.inc b/HashLib/src/Include/Simd/SHA3/KeccakF1600Avx2Absorb_x86_64.inc index 0f9002fb..9174094e 100644 --- a/HashLib/src/Include/Simd/SHA3/KeccakF1600Avx2Absorb_x86_64.inc +++ b/HashLib/src/Include/Simd/SHA3/KeccakF1600Avx2Absorb_x86_64.inc @@ -8,7 +8,7 @@ // Uses "plane-per-register" technique: 25 Keccak lanes packed into 7 YMM registers. // All VEX instructions are db-encoded for broad assembler compatibility. // -// After SimdProc5Begin_x86_64.inc: +// After HlpSimdProc5Begin_x86_64.inc: // rcx = state ptr (25 x UInt64, standard layout) // rdx = data ptr (input bytes, little-endian UInt64 words) // r8d = block count @@ -52,7 +52,7 @@ push rdi push rsi - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} sub rsp, 264 @@ -393,7 +393,7 @@ add rsp, 264 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} pop rsi pop rdi diff --git a/HashLib/src/Include/Simd/SHA3/KeccakF1600Avx2_x86_64.inc b/HashLib/src/Include/Simd/SHA3/KeccakF1600Avx2_x86_64.inc index 7e649bbd..e40f3091 100644 --- a/HashLib/src/Include/Simd/SHA3/KeccakF1600Avx2_x86_64.inc +++ b/HashLib/src/Include/Simd/SHA3/KeccakF1600Avx2_x86_64.inc @@ -24,7 +24,7 @@ // [rsp+ 32..191]: xmm6-xmm15 save area // [rsp+192..223]: padding - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} sub rsp, 64 @@ -274,4 +274,4 @@ add rsp, 64 - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/SHA3/KeccakF1600CryptoExtAbsorb_aarch64.inc b/HashLib/src/Include/Simd/SHA3/KeccakF1600CryptoExtAbsorb_aarch64.inc index 9647698a..fc514f01 100644 --- a/HashLib/src/Include/Simd/SHA3/KeccakF1600CryptoExtAbsorb_aarch64.inc +++ b/HashLib/src/Include/Simd/SHA3/KeccakF1600CryptoExtAbsorb_aarch64.inc @@ -9,7 +9,7 @@ // v25-v30 = permutation scratch // v31 = loaded input lane - {$I ..\Include\Simd\Common\SimdNonVolatileSave_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_aarch64.inc} .long 0x6d400400 // ldp d0, d1, [x0] .long 0x6d410c02 // ldp d2, d3, [x0, #16] .long 0x6d421404 // ldp d4, d5, [x0, #32] @@ -200,5 +200,5 @@ .long 0x6d0a5414 // stp d20, d21, [x0, #160] .long 0x6d0b5c16 // stp d22, d23, [x0, #176] .long 0xfd006018 // str d24, [x0, #192] - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_aarch64.inc} ret diff --git a/HashLib/src/Include/Simd/SHA3/KeccakF1600CryptoExt_aarch64.inc b/HashLib/src/Include/Simd/SHA3/KeccakF1600CryptoExt_aarch64.inc index 0c0db336..7728a65e 100644 --- a/HashLib/src/Include/Simd/SHA3/KeccakF1600CryptoExt_aarch64.inc +++ b/HashLib/src/Include/Simd/SHA3/KeccakF1600CryptoExt_aarch64.inc @@ -11,7 +11,7 @@ // v26 = iota round constant (ld1r) // v30-v31 = Rho/Pi scratch - {$I ..\Include\Simd\Common\SimdNonVolatileSave_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_aarch64.inc} .long 0x6d400400 // ldp d0, d1, [x0] .long 0x6d410c02 // ldp d2, d3, [x0, #16] .long 0x6d421404 // ldp d4, d5, [x0, #32] @@ -109,5 +109,5 @@ .long 0x6d0a5414 // stp d20, d21, [x0, #160] .long 0x6d0b5c16 // stp d22, d23, [x0, #176] .long 0xfd006018 // str d24, [x0, #192] - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_aarch64.inc} ret diff --git a/HashLib/src/Include/Simd/SHA512/SHA512CompressAvx2_x86_64.inc b/HashLib/src/Include/Simd/SHA512/SHA512CompressAvx2_x86_64.inc index 5300c044..7195dee9 100644 --- a/HashLib/src/Include/Simd/SHA512/SHA512CompressAvx2_x86_64.inc +++ b/HashLib/src/Include/Simd/SHA512/SHA512CompressAvx2_x86_64.inc @@ -4,16 +4,16 @@ // scheduling two blocks at once is what makes this faster than the single-block // AVX path. AVX2 and BMI2 (rorx/andn) instructions are db-encoded for broad // assembler compatibility (every AVX2 CPU also provides BMI2). -// Expects MS x64 ABI (after SimdProc4Begin): rcx = state ptr, rdx = data ptr, +// Expects MS x64 ABI (after HlpSimdProc4Begin): rcx = state ptr, rdx = data ptr, // r8d = numblocks, r9 = doubled-K512 ptr (each 128-bit K512 pair stored twice // so one table feeds both 256-bit lanes, with the BSWAP64 mask appended; see // K512_Doubled). The mask is read unaligned, so the Pascal const needs no // special alignment. // -// MS x64 non-volatile saves: xmm6-xmm15 via the shared SimdNonVolatileSave/Restore +// MS x64 non-volatile saves: xmm6-xmm15 via the shared HlpSimdNonVolatileSave/Restore // include (no-op on SysV); rbx, rbp, rdi, rsi, r12-r15 in the local frame. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} mov rax, rsp push r9 @@ -1344,4 +1344,4 @@ lea rsp, [rsi] mov rsi, rax - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/SHA512/SHA512CompressSse2_i386.inc b/HashLib/src/Include/Simd/SHA512/SHA512CompressSse2_i386.inc index bb128372..5af39e55 100644 --- a/HashLib/src/Include/Simd/SHA512/SHA512CompressSse2_i386.inc +++ b/HashLib/src/Include/Simd/SHA512/SHA512CompressSse2_i386.inc @@ -2,8 +2,8 @@ // (CRYPTOGAMS). The 64-bit state and message schedule are held in xmm0-xmm7 (low // 64 bits) and computed entirely in SSE2 (paddq/psrlq/psllq/pxor), so the whole // hash runs in the vector unit - avoiding IA-32's 32-bit-GPR bottleneck. -// Expects (after SimdProc4Begin_i386): ebx = state, esi = data, edi = numblocks, -// eax = K512 ptr (80 UInt64). SimdProc4Begin pushes ebx/esi/edi; ebp is pushed +// Expects (after HlpSimdProc4Begin_i386): ebx = state, esi = data, edi = numblocks, +// eax = K512 ptr (80 UInt64). HlpSimdProc4Begin pushes ebx/esi/edi; ebp is pushed // here as the K512 walk pointer; state is loaded into xmm0-xmm7. push ebp diff --git a/HashLib/src/Include/Simd/SHA512/SHA512CompressSse2_x86_64.inc b/HashLib/src/Include/Simd/SHA512/SHA512CompressSse2_x86_64.inc index 62a46c15..c16de395 100644 --- a/HashLib/src/Include/Simd/SHA512/SHA512CompressSse2_x86_64.inc +++ b/HashLib/src/Include/Simd/SHA512/SHA512CompressSse2_x86_64.inc @@ -3,16 +3,16 @@ // in 128-bit SSE2 and is interleaved with the 64-bit GPR compression rounds, so // the vector and integer units run in parallel. This is much faster than a scalar // message schedule. -// Expects MS x64 ABI (after SimdProc4Begin): rcx = state ptr, rdx = data ptr, +// Expects MS x64 ABI (after HlpSimdProc4Begin): rcx = state ptr, rdx = data ptr, // r8d = numblocks, r9 = doubled-K512 ptr (K512_Doubled: each 128-bit K512 pair // stored twice, read at a 32-byte stride). The big-endian input byte-swap is // emulated with pshuflw/pshufhw/psrlw/psllw/por (SSE2 has no pshufb), so no mask // table is needed. // -// MS x64 non-volatile saves: xmm6-xmm15 via the shared SimdNonVolatileSave/Restore +// MS x64 non-volatile saves: xmm6-xmm15 via the shared HlpSimdNonVolatileSave/Restore // include (no-op on SysV); rbx, rbp, rdi, rsi, r12-r15 in the local frame. - {$I ..\Include\Simd\Common\SimdNonVolatileSave_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileSave_x86_64.inc} push rbx push rbp @@ -1295,4 +1295,4 @@ pop rbp pop rbx - {$I ..\Include\Simd\Common\SimdNonVolatileRestore_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdNonVolatileRestore_x86_64.inc} diff --git a/HashLib/src/Include/Simd/Scrypt/ScryptSalsa8Sse2_i386.inc b/HashLib/src/Include/Simd/Scrypt/ScryptSalsa8Sse2_i386.inc index 5c6cd20a..8803aca1 100644 --- a/HashLib/src/Include/Simd/Scrypt/ScryptSalsa8Sse2_i386.inc +++ b/HashLib/src/Include/Simd/Scrypt/ScryptSalsa8Sse2_i386.inc @@ -7,7 +7,7 @@ // enabling lane-parallel SIMD processing of column and row quarter-rounds // with pshufd-based diagonalize/undiagonalize between them. // -// IA-32: after SimdProc2Begin_i386 — ebx = State ptr, esi = Input ptr +// IA-32: after HlpSimdProc2Begin_i386 — ebx = State ptr, esi = Input ptr // (parallel to MS x64 ABI: rcx, rdx). // Each pointer addresses 16 UInt32 (64 bytes) in permuted order: // xmm0 = A = {w0,w5,w10,w15}, xmm1 = B = {w4,w9,w14,w3}, diff --git a/HashLib/src/Include/Simd/XXH3/XXH3Acc512Sse2_i386.inc b/HashLib/src/Include/Simd/XXH3/XXH3Acc512Sse2_i386.inc index 216dd05a..ab7d5b61 100644 --- a/HashLib/src/Include/Simd/XXH3/XXH3Acc512Sse2_i386.inc +++ b/HashLib/src/Include/Simd/XXH3/XXH3Acc512Sse2_i386.inc @@ -1,5 +1,5 @@ // SSE2 implementation of XXH3_accumulate_512 (fully unrolled, 4 x 16-byte chunks). -// IA-32: after SimdProc3Begin_i386 — ebx = acc, esi = input, edi = secret +// IA-32: after HlpSimdProc3Begin_i386 — ebx = acc, esi = input, edi = secret // (parallel to MS x64 ABI: rcx, rdx, r8). // Uses only volatile XMM: xmm0–xmm5. // Reference: official xxHash C - XXH3_accumulate_512_sse2 in xxhash.h diff --git a/HashLib/src/Include/Simd/XXH3/XXH3InitSecretSse2_i386.inc b/HashLib/src/Include/Simd/XXH3/XXH3InitSecretSse2_i386.inc index efe6b406..cad3d2e7 100644 --- a/HashLib/src/Include/Simd/XXH3/XXH3InitSecretSse2_i386.inc +++ b/HashLib/src/Include/Simd/XXH3/XXH3InitSecretSse2_i386.inc @@ -1,5 +1,5 @@ // SSE2 implementation of XXH3_initCustomSecret (fully unrolled, 12 x 16-byte chunks). -// IA-32: after SimdProc3Begin_i386 — ebx = customSecret, esi = defaultSecret, edi = seed.lo32, +// IA-32: after HlpSimdProc3Begin_i386 — ebx = customSecret, esi = defaultSecret, edi = seed.lo32, // dword [esp+16] = seed.hi32 (UInt64 third parameter; high dword on stack). // (parallel to MS x64 ABI: rcx, rdx, r8). // Uses only volatile XMM: xmm0–xmm2. diff --git a/HashLib/src/Include/Simd/XXH3/XXH3ScrambleSse2_i386.inc b/HashLib/src/Include/Simd/XXH3/XXH3ScrambleSse2_i386.inc index 20270289..16ed7be8 100644 --- a/HashLib/src/Include/Simd/XXH3/XXH3ScrambleSse2_i386.inc +++ b/HashLib/src/Include/Simd/XXH3/XXH3ScrambleSse2_i386.inc @@ -1,5 +1,5 @@ // SSE2 implementation of XXH3_scrambleAcc (fully unrolled, 4 x 16-byte chunks). -// IA-32: after SimdProc2Begin_i386 — ebx = acc, esi = secret +// IA-32: after HlpSimdProc2Begin_i386 — ebx = acc, esi = secret // (parallel to MS x64 ABI: rcx, rdx). // Uses only volatile registers: xmm0–xmm5, eax. // Algorithm per 128-bit chunk: diff --git a/HashLib/src/KDF/HlpArgon2Dispatch.pas b/HashLib/src/KDF/HlpArgon2Dispatch.pas index 95c253de..260a6ff6 100644 --- a/HashLib/src/KDF/HlpArgon2Dispatch.pas +++ b/HashLib/src/KDF/HlpArgon2Dispatch.pas @@ -113,7 +113,7 @@ procedure Argon2_FillBlock_Scalar(ALeft, ARight, ACurrent: Pointer; AWithXor: In {$IFDEF HASHLIB_I386_ASM} procedure Argon2_FillBlock_Sse2(ALeft, ARight, ACurrent: Pointer; AWithXor: Int32); - {$I ..\Include\Simd\Common\SimdProc4Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_i386.inc} {$I ..\Include\Simd\Argon2\Argon2FillBlockSse2_i386.inc} end; @@ -122,12 +122,12 @@ procedure Argon2_FillBlock_Sse2(ALeft, ARight, ACurrent: Pointer; AWithXor: Int3 {$IFDEF HASHLIB_X86_64_ASM} procedure Argon2_FillBlock_Sse2(ALeft, ARight, ACurrent: Pointer; AWithXor: Int32); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Argon2\Argon2FillBlockSse2_x86_64.inc} end; procedure Argon2_FillBlock_Avx2(ALeft, ARight, ACurrent: Pointer; AWithXor: Int32); - {$I ..\Include\Simd\Common\SimdProc4Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_x86_64.inc} {$I ..\Include\Simd\Argon2\Argon2FillBlockAvx2_x86_64.inc} end; @@ -136,7 +136,7 @@ procedure Argon2_FillBlock_Avx2(ALeft, ARight, ACurrent: Pointer; AWithXor: Int3 {$IFDEF HASHLIB_AARCH64_ASM} procedure Argon2_FillBlock_Neon(ALeft, ARight, ACurrent: Pointer; AWithXor: Int32); - {$I ..\Include\Simd\Common\SimdProc4Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc4Begin_aarch64.inc} {$I ..\Include\Simd\Argon2\Argon2FillBlockNeon_aarch64.inc} end; diff --git a/HashLib/src/KDF/HlpScryptDispatch.pas b/HashLib/src/KDF/HlpScryptDispatch.pas index bc65f77e..8d0450c1 100644 --- a/HashLib/src/KDF/HlpScryptDispatch.pas +++ b/HashLib/src/KDF/HlpScryptDispatch.pas @@ -178,7 +178,7 @@ procedure Scrypt_SalsaXor_Scalar(AState, AInput: Pointer); {$IFDEF HASHLIB_I386_ASM} procedure Scrypt_SalsaXor_Sse2(AState, AInput: Pointer); - {$I ..\Include\Simd\Common\SimdProc2Begin_i386.inc} + {$I ..\Include\Simd\Common\HlpSimdProc2Begin_i386.inc} {$I ..\Include\Simd\Scrypt\ScryptSalsa8Sse2_i386.inc} end; @@ -187,12 +187,12 @@ procedure Scrypt_SalsaXor_Sse2(AState, AInput: Pointer); {$IFDEF HASHLIB_X86_64_ASM} procedure Scrypt_SalsaXor_Sse2(AState, AInput: Pointer); - {$I ..\Include\Simd\Common\SimdProc2Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc2Begin_x86_64.inc} {$I ..\Include\Simd\Scrypt\ScryptSalsa8Sse2_x86_64.inc} end; procedure Scrypt_SalsaXor_Avx2(AState, AInput: Pointer); - {$I ..\Include\Simd\Common\SimdProc2Begin_x86_64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc2Begin_x86_64.inc} {$I ..\Include\Simd\Scrypt\ScryptSalsa8Avx2_x86_64.inc} end; @@ -201,7 +201,7 @@ procedure Scrypt_SalsaXor_Avx2(AState, AInput: Pointer); {$IFDEF HASHLIB_AARCH64_ASM} procedure Scrypt_SalsaXor_Neon(AState, AInput: Pointer); - {$I ..\Include\Simd\Common\SimdProc2Begin_aarch64.inc} + {$I ..\Include\Simd\Common\HlpSimdProc2Begin_aarch64.inc} {$I ..\Include\Simd\Scrypt\ScryptSalsa8Neon_aarch64.inc} end; diff --git a/HashLib/src/Utils/HlpX86SimdFeatures.pas b/HashLib/src/Utils/HlpX86SimdFeatures.pas index 460a1583..228a3dee 100644 --- a/HashLib/src/Utils/HlpX86SimdFeatures.pas +++ b/HashLib/src/Utils/HlpX86SimdFeatures.pas @@ -74,11 +74,11 @@ TCpuIdResult = record {$IFDEF HASHLIB_X86_SIMD} procedure CpuIdQuery(ALeaf, ASubLeaf: UInt32; out AResult: TCpuIdResult); - {$I ..\Include\Simd\CpuFeatures\CpuIdQuery.inc} + {$I ..\Include\Simd\CpuFeatures\HlpCpuIdQuery.inc} end; procedure XGetBvQuery(out AResult: UInt64); - {$I ..\Include\Simd\CpuFeatures\XGetBvQuery.inc} + {$I ..\Include\Simd\CpuFeatures\HlpXGetBvQuery.inc} end; {$ENDIF}