diff --git a/catalog/list.json b/catalog/list.json
index 32a59db..4a8e6d4 100644
--- a/catalog/list.json
+++ b/catalog/list.json
@@ -1,6 +1,78 @@
 {
-    "num": 87,
+    "num": 90,
     "designs": [
+        {
+            "id": "-",
+            "title": "Agilex 7 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.3.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 7 FPGA.",
+            "rich_description": "<p>This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/img/block_diagram.png\"/></p>",
+            "category": "AI",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1-v1.0/agilex7_niosv_g_tinyml_liteRT.zip",
+            "downloadUrl": "agilex7_niosv_g_tinyml_liteRT.zip",
+            "documentations": [
+                {
+                    "title": "Design Document",
+                    "downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/docs/Nios_Vg_Processor_TinyML_Design_on_Agilex_7_FPGA.md"
+                }
+            ],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/344658973",
+            "Q_GITHUB_RELEASE": "25.3.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 7 FPGA - Nios V/m Transceiver Loopback design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.3.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF027F1ES",
+            "device_part": "AGFD023R24C2E1VC",
+            "description": "F-Tile Transceiver loopback design on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)",
+            "rich_description": "<p>This design demonstrates the serial loopback via QSFPDD on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/img/niosv_xcver.png\"/></p>",
+            "category": "Transceiver",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1-v1.0/agilex7_xcver_loopback.zip",
+            "downloadUrl": "agilex7_xcver_loopback.zip",
+            "documentations": [
+                {
+                    "title": "Design Document",
+                    "downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/docs/Nios_Vm_Processor_PAM4_8x53Gbps_with_QSFPDD_Serial_loopback_design.md"
+                }
+            ],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/344685849",
+            "Q_GITHUB_RELEASE": "25.3.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 7 FPGA - Lockstep Example Design Example on Nios® V/g Processor",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.3.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios® V/g Processor-based Lockstep example design on the Agilex® 7 FPGA.",
+            "rich_description": "<p>This design demonstrates the working of NiosV/g lockstep feature through the standard fail safe control mechanism using by injecting root faults and reading alarms with Nios® V/m as the system supervisor on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.1/agf014ea-dev-devkit/niosv_g/lockstep/img/block_diagram.png\"/></p>",
+            "category": "Nios V",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1-v1.0/agilex7_niosv_g_lockstep.zip",
+            "downloadUrl": "agilex7_niosv_g_lockstep.zip",
+            "documentations": [
+                {
+                    "title": "Design Document",
+                    "downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.1/agf014ea-dev-devkit/niosv_g/lockstep/docs/Nios_Vg_Processor_Lockstep_Design_on_Agilex_7_FPGA.md"
+                }
+            ],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/344655307",
+            "Q_GITHUB_RELEASE": "25.3.1-v1.0",
+            "Q_VALIDATED": true
+        },
         {
             "id": "-",
             "title": "Agilex 7 FPGA - Lockstep Example Design Example on Nios V/g Processor",