From d3abb98694003642fcf045c958db0db17dd90cf7 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Tue, 12 May 2026 19:18:30 +0200 Subject: [PATCH 1/3] recovery_receiver: do not jump to Error state on address change Signed-off-by: Karol Gugala --- src/recovery/recovery_receiver.sv | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/recovery/recovery_receiver.sv b/src/recovery/recovery_receiver.sv index 2511ea3d1..aa9d8adfd 100644 --- a/src/recovery/recovery_receiver.sv +++ b/src/recovery/recovery_receiver.sv @@ -786,13 +786,19 @@ module recovery_receiver TxDesc: begin tx_pec_soft_rst_n_o = 1'b1; - if (bus_stop_i || other_target_start_i || (virtual_target_start_i && !bus_addr_i[0])) begin + if (bus_stop_i || (virtual_target_start_i && !bus_addr_i[0])) begin // Protocol errors: // - STOP instead of Sr (incomplete read transaction) - // - Sr + Addr to different target (abandoned our transaction) // - Sr + Addr+W (expected read but got write) unsupported_err = unsupported_err_det_en_i; state_d = Error; + end else if (other_target_start_i) begin + unsupported_err = unsupported_err_det_en_i; + // - Sr + Addr to different target (abandoned our transaction) + // We can switch to our regular target, so we're not jumping to the Error state + // Error state keeps the width converter in soft reset, preventing any + // data to enter RX FIFO. To prevent loosing this data we jump to Done. + state_d = Done; end else if (tx_desc_ready_i) begin state_d = TxLenL; tx_pec_enable_o = 1'b1; From 45f40ca1320144fe4490ab5321462e7a4b0cb6b1 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Tue, 12 May 2026 19:26:16 +0200 Subject: [PATCH 2/3] test_recovery: uncomment take_bus_control Signed-off-by: Karol Gugala --- verification/cocotb/top/lib_i3c_top/test_recovery.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verification/cocotb/top/lib_i3c_top/test_recovery.py b/verification/cocotb/top/lib_i3c_top/test_recovery.py index 5660ababa..de46ecb70 100644 --- a/verification/cocotb/top/lib_i3c_top/test_recovery.py +++ b/verification/cocotb/top/lib_i3c_top/test_recovery.py @@ -5389,7 +5389,7 @@ async def test_ri_read_interrupted_by_ccc(dut): # uncommented, the controller sends actual S + Addr+W + CMD + PEC + Sr, in that case # the recovery_receiver enters Error state and keeps RX Queue in soft reset state # which blocks it from receiving data sent to main target on I3C bus. - # await i3c_controller.take_bus_control() + await i3c_controller.take_bus_control() # Start RI write phase: S + Addr+W (to virtual target) await i3c_controller.send_start() From 3234f63f35a9feb960d5f124008d14511dc35dff Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Thu, 14 May 2026 07:03:06 +0200 Subject: [PATCH 3/3] Update recovery_receiver waivers to match RTL change --- verification/waivers/exclusion.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/verification/waivers/exclusion.yaml b/verification/waivers/exclusion.yaml index fb991e5e8..c1141dfda 100644 --- a/verification/waivers/exclusion.yaml +++ b/verification/waivers/exclusion.yaml @@ -3663,7 +3663,7 @@ exclusions: branch: - 17: [7] # unique case (state_q) line: - - 1143 # unique case (state_q) + - 1149 # unique case (state_q) Read only interface: cond: @@ -3681,17 +3681,17 @@ exclusions: This would require controller to send Sr while target is in PP mode which is illegal: line: - - 810 # TxDesc: state_d = Done; // Controller aborted read via Sr + - 816 # TxDesc: state_d = Done; // Controller aborted read via Sr branch: - 3: # unique case (state_q) - - 41 # TxDesc: if (bus_rstart_i) begin + - 42 # TxDesc: if (bus_rstart_i) begin cond: - 40: [2 "01"] # if ((tx_data_ready_i && tx_data_valid_o) || bus_rstart_i) begin Not needed else: branch: - 3: # unique case (state_q) - - 52 # TxData: if (tx_data_valid_o) begin + - 53 # TxData: if (tx_data_valid_o) begin Upper bits of a counter: toggle: