From b7d78d510cba9fa62ca488d4d0b0f306ba53ce63 Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Wed, 22 Oct 2025 13:00:56 +0000 Subject: [PATCH 1/2] Read DAT/DCT memories only on valid state --- src/hci/dxt.sv | 48 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/src/hci/dxt.sv b/src/hci/dxt.sv index 4d46560e3..efa83d894 100644 --- a/src/hci/dxt.sv +++ b/src/hci/dxt.sv @@ -49,6 +49,9 @@ module dxt logic [DatAw-1:0] dat_index_sw; logic dat_word_index_sw; + logic dat_rd_req; + logic dat_wr_req; + logic dat_rd_ack; logic dat_wr_ack; @@ -99,14 +102,19 @@ module dxt if (~rst_ni) begin csr_dat_hwif_o.rd_data <= '0; end else begin - case (dat_word_index_sw) - 1'd0: csr_dat_hwif_o.rd_data <= dat_mem_src_i.rdata[31:0]; - 1'd1: csr_dat_hwif_o.rd_data <= dat_mem_src_i.rdata[63:32]; - default: csr_dat_hwif_o.rd_data <= '0; - endcase + if (dat_mem_src_i.rvalid) + case (dat_word_index_sw) + 1'd0: csr_dat_hwif_o.rd_data <= dat_mem_src_i.rdata[31:0]; + 1'd1: csr_dat_hwif_o.rd_data <= dat_mem_src_i.rdata[63:32]; + default: csr_dat_hwif_o.rd_data <= '0; + endcase + else csr_dat_hwif_o.rd_data <= '0; end end + assign dat_rd_req = csr_dat_hwif_i.req & ~csr_dat_hwif_i.req_is_wr & ~dat_read_valid_hw_i; + assign dat_wr_req = csr_dat_hwif_i.req & csr_dat_hwif_i.req_is_wr; + always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin dat_rd_ack <= 1'b0; @@ -114,10 +122,10 @@ module dxt csr_dat_hwif_o.rd_ack <= 1'b0; csr_dat_hwif_o.wr_ack <= 1'b0; end else begin - dat_rd_ack <= csr_dat_hwif_i.req & ~csr_dat_hwif_i.req_is_wr & ~dat_read_valid_hw_i; + dat_rd_ack <= dat_rd_req; csr_dat_hwif_o.rd_ack <= dat_rd_ack; - dat_wr_ack <= csr_dat_hwif_i.req & csr_dat_hwif_i.req_is_wr; + dat_wr_ack <= dat_wr_req; csr_dat_hwif_o.wr_ack <= dat_wr_ack; end end @@ -131,6 +139,9 @@ module dxt logic [DctAw-1:0] dct_index_sw; logic [1:0] dct_word_index_sw; + logic dct_rd_req; + logic dct_wr_req; + logic dct_rd_ack; logic dct_wr_ack; @@ -165,16 +176,21 @@ module dxt if (~rst_ni) begin csr_dct_hwif_o.rd_data <= '0; end else begin - case (dct_word_index_sw) - 2'd0: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[31:0]; - 2'd1: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[63:32]; - 2'd2: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[95:64]; - 2'd3: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[127:96]; - default: csr_dct_hwif_o.rd_data <= '0; - endcase + if (dct_mem_src_i.rvalid) + case (dct_word_index_sw) + 2'd0: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[31:0]; + 2'd1: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[63:32]; + 2'd2: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[95:64]; + 2'd3: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[127:96]; + default: csr_dct_hwif_o.rd_data <= '0; + endcase + else csr_dct_hwif_o.rd_data <= '0; end end + assign dct_rd_req = csr_dct_hwif_i.req & ~csr_dct_hwif_i.req_is_wr & ~dct_read_valid_hw_i; + assign dct_wr_req = csr_dct_hwif_i.req & csr_dct_hwif_i.req_is_wr; + always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin dct_rd_ack <= 1'b0; @@ -182,10 +198,10 @@ module dxt csr_dct_hwif_o.rd_ack <= 1'b0; csr_dct_hwif_o.wr_ack <= 1'b0; end else begin - dct_rd_ack <= csr_dct_hwif_i.req & ~csr_dct_hwif_i.req_is_wr & ~dct_read_valid_hw_i; + dct_rd_ack <= dct_rd_req; csr_dct_hwif_o.rd_ack <= dct_rd_ack; // ACK write requests to remove CPU stall, even though they're illegal to DCT - dct_wr_ack <= csr_dct_hwif_i.req & csr_dct_hwif_i.req_is_wr; + dct_wr_ack <= dct_wr_req; csr_dct_hwif_o.wr_ack <= dct_wr_ack; end end From 43b2677112ae18b45d36dca77220d4126c10fbce Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Wed, 22 Oct 2025 13:01:21 +0000 Subject: [PATCH 2/2] Add support for initializing memories --- src/i3c_wrapper.sv | 11 ++++++++--- src/libs/mem/prim_generic_ram_1p.sv | 6 +++--- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/i3c_wrapper.sv b/src/i3c_wrapper.sv index d3d7059dc..7eeda923b 100644 --- a/src/i3c_wrapper.sv +++ b/src/i3c_wrapper.sv @@ -18,7 +18,10 @@ module i3c_wrapper #( parameter int unsigned DctAw = i3c_pkg::DctAw, parameter int unsigned CsrAddrWidth = I3CCSR_pkg::I3CCSR_MIN_ADDR_WIDTH, - parameter int unsigned CsrDataWidth = I3CCSR_pkg::I3CCSR_DATA_WIDTH + parameter int unsigned CsrDataWidth = I3CCSR_pkg::I3CCSR_DATA_WIDTH, + + parameter string DatMemInitFile = "", + parameter string DctMemInitFile = "" ) ( input clk_i, // clock input rst_ni, // active low reset @@ -242,7 +245,8 @@ module i3c_wrapper #( prim_ram_1p_adv #( .Depth(`DAT_DEPTH), .Width(64), - .DataBitsPerMask(32) + .DataBitsPerMask(32), + .MemInitFile(DatMemInitFile) ) dat_memory ( .clk_i, .rst_ni, @@ -260,7 +264,8 @@ module i3c_wrapper #( prim_ram_1p_adv #( .Depth(`DCT_DEPTH), .Width(128), - .DataBitsPerMask(32) + .DataBitsPerMask(32), + .MemInitFile(DctMemInitFile) ) dct_memory ( .clk_i, .rst_ni, diff --git a/src/libs/mem/prim_generic_ram_1p.sv b/src/libs/mem/prim_generic_ram_1p.sv index 032780a09..c160e673c 100644 --- a/src/libs/mem/prim_generic_ram_1p.sv +++ b/src/libs/mem/prim_generic_ram_1p.sv @@ -73,7 +73,7 @@ module prim_generic_ram_1p import prim_ram_1p_pkg::*; #( end end end - -// `include "prim_util_memload.svh" -// `endif +`ifndef SYNTHESIS + `include "caliptra_prim_util_memload.svh" +`endif endmodule